Abstract: A semiconductor device has a leadframe with a structure made of a base metal (105), wherein the structure consists of a chip mount pad (302) and a plurality of lead segments (303). Covering the base metal are, consecutively, a continuous nickel layer (201) on the base metal, a layer of palladium on the nickel, wherein the palladium layer (203) on the chip side of the structure is thicker than the palladium layer (202) opposite the chip, and a gold layer (204) on the palladium layer (202) opposite the chip. A semiconductor chip (310) is attached to the chip mount pad and conductive connections (312) span from the chip to the lead segments. Polymeric encapsulation compound (320) covers the chip, the connections, and portions of the lead segments, but leaves other segment portions available for solder reflow attachment to external parts.

Abstract: An insulating substrate includes a metal base as a base member, an insulating layer which is a room temperature, aerosol deposited shock solidification film formed on the metal base, and a circuit pattern which is a cold sprayed thermal spray coating formed on the insulating layer. A semiconductor device incorporates the insulating substrate, and thereby has improved heat radiation characteristics.

Abstract: A process for preparing an electronic package comprising: (a) providing a ceramic housing defining an internal cavity for receiving a micro device and having one or more interface portions; (b) treating the housing to form a tungsten layer on the interface portions; and (c) overlaying a palladium layer on the tungsten layer.

Abstract: A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal; an adherent film of palladium on said nickel layer; and an adherent layer of palladium on said palladium film, selectively covering areas of said leadframe suitable for bonding wire attachment and solder attachment.

Abstract: A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, with at least one semiconductor chip being placed on each of the header regions. A conductive member link is placed on top of the two chips to electrically and mechanically interconnect the chips.

Abstract: A dense semiconductor flip-chip device assembly is provided with a heat sink/spreading/dissipating member that is formed as a paddle of a metallic paddle frame in a strip of paddle frames. Semiconductor dice are bonded to the paddles by, e.g., conventional semiconductor die attachment methods, enabling bump attachment and testing to be conducted before detachment from the paddle frame strip.

Abstract: A packaged integrated circuit includes a die surrounded by an encapsulant in which leads are used to electrically connect the die, which is internal to the encapsulant, externally. The leads have a primary metal that is used for electrical conduction and physical support. The external portion of the lead is coated with another metal, typically tin, that is useful for soldering. This tin layer is formed in a manner that ensures that it is porous. Although porous is generally thought to be a bad characteristic, it turns out to be very effective in absorbing stress and thus retarding whisker growth. Whisker growth, which can short adjacent leads together as well as cause other deleterious effects, has been a major source of failures in packaged integrated circuits. An additional layer of very thin tin that is non-porous can be added before or after the porous tin layer has been deposited.

Abstract: Packaging assembly method and systems include the use of a plastic substrate and one or more compliant fasteners, which can be connected to the plastic substrate, such that the compliant fastener provides an electrical connection to one or more electrical components. A plastic leadframe can therefore be formed, which is based upon the plastic substrate and the compliant fastener for attachment to other electrical components. The plastic substrate itself can function as a plastic trace or plastic substrate trace, and can be formed from plastic material such as thermoplastic or a thermoset material. The compliant fastener itself can be pushed into the plastic substrate at a connection point thereof for attachment of the compliant fastener to the plastic substrate. The connection point can be formed in the plastic substrate as one or more round holes, slots, rectangular holes or complex shapes. An interface is therefore for med between the plastic trace and the compliant fastener.

Abstract: A plastic substrate can be provided and thereafter a plurality of metal-to-metal connections can be ultrasonically bonded to the plastic substrate. One or more dies and a plurality of conductive components thereof can then be respectively connected to the metal-to-metal connections in order to provide a plastic leadframe package structure that includes electronic circuitry thereon. The plurality of conductive components can be configured as discrete components, while the die itself can be configured as a Flip Chip On Plastic Leadframe component. By utilizing plastic as the basis for a substrate and, ultrasonic bonding of the metal-to-metal connections, a complex substrate formed from plastic can provide a structure, particularly a plastic leadframe structure, that allows for the use of parts and components that are much less expensive than presently utilized parts and components.

Abstract: A configuration for a conventional lead frame for conserving limited leads and for allowing the location of bond pads anywhere on the periphery of the semiconductor device and for reducing the cost of tooling changes by permitting the use of current tooling. The present invention utilizes an extended lead finger that extends along the periphery of a semiconductor device to provide a power source or ground so that any number of bond pads may be used in any position without requiring additional leads or tooling changes.

Abstract: A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 ?m, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected. A solder containing Pb as a main composition metal is provided at a portion outside a portion molded by the resin.

Abstract: Systems and methods are disclosed to dissipate heat from a semiconductor substrate. A package for integrated circuit includes a chip having a plurality of chip pads adapted to receive the variety of signals from or to output the same to an external circuit; a lead frame having a plurality of contact points each corresponding to a chip pad; and nano ceramic material in thermal communication with the chip for removing heat from the chip.

Abstract: A conductive plastic lead frame and method of manufacturing the same, suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal; an adherent film of palladium on said nickel layer; and an adherent layer of palladium on said palladium film, selectively covering areas of said leadframe suitable for bonding wire attachment and solder attachment.

Abstract: A lead pin with an Au—Ge based brazing material including a lead pin made of a copper-containing metal is provided. The lead pin including a joining surface to a substrate, at least the joining surface of the lead pin being plated with nickel and gold, and including an Au—Ge based brazing material being fused on top of the gold plating, wherein the lead pin after plated with nickel is subjected to heat-treatment and then plated with gold to fuse the brazing material.

Abstract: Arrangements are provided to effectively prevent wire disconnection generated due to an increase of heat applied to a semiconductor integrated circuit device. The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 ?m is provided in the connecting member.

Abstract: A film carrier tape for mounting an electronic part comprising an insulating film and a wire pattern which is made of a conductive metal and is provided on the surface of the insulating film, wherein an undercoating layer containing nickel as a main constituent is formed on at least a part of the surface of the wiring pattern made of a conductive metal, an intermediate layer containing palladium as a main constituent is formed on the surface of he undercoating layer, a surface layer containing gold as a main constituent is formed on the surface of the intermediate layer, and the average thickness of the intermediate layer containing palladium as a main constituent is not more than 0.04 ?m.

Abstract: Stacked metal sections serve as two leads of an IC package. In one embodiment, an IC chip is mounted on one section serving as the terminal for the bottom electrode of the chip, and the top electrode of the chip is wire-bonded to the other section serving as another terminal for the chip. The thin sheet metal permits narrower etched separation between the two metal sections. Stacking of two pre-etched thin sheet metals strengthens the substrate. The package is covered with glue to hold the two sections together. The stacked pre-etched metal sheets can serve as a common substrate for a matrix of IC packages, which can later be cut in two orthogonal directions to yield individual packages.

Abstract: A lead frame used for the production of a semiconductor package, wherein each of terminals of the lead frame to be wire-bonded to electrodes provided on the top surface of the semiconductor device has one or two groove(s) for limiting a plating area of noble metal. Since grooves are provided in each terminal, the accuracy of the plating area can be easily checked visually. Further, the grooves absorb stress applied to the terminal when the molded semiconductor packages are individually separated from each other by punching or dicing, and the situation where molding compound comes off of the terminal is prevented. In addition, since the grooves absorb vibrational stress applied to the terminal after mounting a semiconductor on the printed circuit board, the reliability of assembly is improved.

Abstract: For a leadframe for use with integrated circuit chips, a continuous strip of sheet-like base metal is pre-plated with a layer of nickel fully covering the base metal, further on one surface with a palladium layer in a thickness suitable for bonding wire attachment, and on the opposite surface with a layer of either palladium or lead-free solder in a thickness suitable for parts attachment. The leadframe structure is then stamped from the sheet so that the base metal is exposed at the stamped edges, enhancing adhesion to molding compounds.

Abstract: There are provided the steps of forming a plurality of opening portions by punching predetermined portions of a metal plate, forming crushed portions by pushing crushed margin portions, which are defined in vicinity of both side edge portions of the opening portions of the metal plate, to reduce a thickness, defining a width W3 between a side surface portion and a center portion to assure an interval between lead portions and also defining a width of a top end portion and a width of a base portion by punching center portions of the crushed portions except predetermined both-side portions and portions in vicinity of peripheral portions in which the crushed portions of the opening portions of the metal plate are not present, and defining the top end portions by punching a predetermined portion of the top end portion.

Abstract: At least a part of the inner leads 1a of a lead frame 1 is covered with a plating for a metallic fine wire connection, at least the entire portion where the lead frame 1 joins with the adhesive layer 2 is covered by at least one metal or alloy thereof different from the metallic fine wire connecting use plating. The metal or alloy is selected from the group consisting of gold, platinum, iridium, rhodium, palladium, ruthenium, indium, tin, molybdenum, tungsten, gallium, zinc, chromium, niobium, tantalum, titanium and zirconium. Thereby, generation of defects, such as leakage and shorting, due to ion migration can be prevented.

Abstract: A stress shield made of a material having a CTE similar to that of the material used in the fabrication of a microelectronic die, including but not limited silicon, molybdenum, and aluminum nitride, which abuts at least one corner and/or edge of the microelectronic die. When the stress shield is positioned to abut the microelectronic die corners and/or edges, the mechanical stresses on the microelectronic die are greatly reduced or substantially eliminated.

Abstract: A configuration of fuses in a semiconductor structure having Cu metallization planes is provided. The semiconductor structure has an Al metal layer on the topmost interconnect plane for providing Al bonding pads. The fuses are configured as Al fuses and, in the semiconductor structure having Cu metallization planes, are provided above the diffusion barrier of the topmost Cu metallization plane but below a passivation layer.

Abstract: A conductive plastic lead frame and method of manufacturing, the same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: An integrated circuit package is disclosed. The package comprises a plurality of leads, each lead having a first face and a second face opposite to the first face. The package also comprises a die pad having a first face and a second face opposite to the first face. The second face of the die pad is orthogonally offset from the second face of the leads so that the second face of the die pad and the second face of the leads are not coplanar. The package also comprises an integrated circuit chip substantially laterally disposed between the plurality of leads, and having a first face and a second face opposite to the first face. The first face of the integrated circuit chip is proximate to the second face of the die pad and the first face of the integrated circuit chip is coupled to the second face of the die pad. The package further comprises a plurality of wires that link the plurality of leads to the integrated circuit chip.

Abstract: The invention concerns a semiconductor component and a method for identifying a semiconductor component that comprises at least one semiconductor substrate equipped with electronic/electromechanical components, which said semiconductor substrate—except for its leads—is embedded in a housing part made of plastic. It is proposed to equip the semiconductor substrate located in the housing part with an identifier located directly or indirectly thereon that makes it possible to distinguish the semiconductor component from other similarly-designed semiconductor components, and which can be read out from outside the housing part using ultrasound.

Abstract: A conductive plastic lead frame and method of manufacturing same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of pure tin on said nickel layer, selectively covering areas of said leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding wire attachment.

Abstract: A photoelectric structure for surface mounting on a circuit board having a plurality of insertion holes includes at least a pair of fixation pins integrally extended downwards from a periphery of the mounting photoelectric element, and a pair of bended connections integrally extended downwards from a periphery of the mounting photoelectric element such that they are connected with the circuit board by welding, so as to facilitate the other pair of fixation pins to be inserted into the insertion holes of the circuit board for locating securely the photoelectric element for use in Surface Mount Device, SMD, and for enhancing effectively the position of the detection point as well as the degree of precision of the light emitting signal.

Abstract: Surface applied passive devices for use on electronic circuit boards are formed by applying layers of conductive, insulating, and other material to a thin polymer film carrier. The surface applied passives are thin enough to fit underneath standard integrated circuit packages in order to conserve space on the circuit board. Resistors, capacitors, inductors and other passive circuits may be formed on thin polymer films, less than 8 mils thick. This significantly aids in conserving space on an electronic circuit board.

Abstract: A method of making a Fe-Ni strip whose chemical composition comprises, by weight: 36% ≦Ni+Co≦43%; 0%≦Co≦3%; 0.05%≦C≦0.4%; 0.2%≦Cr≦1.5%; 0.4%≦Mo≦3%; Cu≦3%; Si≦0.3%, Mn≦0.3%; the rest being iron and impurities, the alloy having an elastic limit Rp0.2 more than 750 Mpa and a distributed elongation Ar more than 5%. The alloy is optionally recast under slag. The strip is obtained by hot-rolling above 950° C., then cold-rolling and carrying out a hardening treatment between 450° C. and 850° C., the hardening heat treatment being preceded by a reduction of at least 40%. The invention is useful for making integrated circuit support grids and electronic gun grids.

Abstract: A chip carrier tape, which includes a tape member and a plurality of pockets, is provided. The plurality of pockets are formed in and along the tape member. Each of the pockets includes a first portion and a second portion. The first portion has a shape and size adapted to fit a first chip size therein. The second portion has a shape and size adapted to fit a second chip size therein. The first chip size differs from the second chip size. The first portion has a first pocket volume that is not part of the second portion, and the second portion has a second pocket volume that is not part of the first portion. There may be a second and different plurality of pockets formed in and along the tape member as well. Also a method of selling integrated circuit chips is provided.

Abstract: The present invention relates to a lead frame for semiconductor devices having an outer lead part improved in solder wettability which comprises i. a substrate comprising an alloy comprising at least one member selected from the group consisting of nickel, copper, iron and (nickel and copper and iron), ii. an inner lead part having a surface treated layer A, the surface treated layer A comprising silver or an alloy comprising silver, and iii. an outer lead part having a surface treated layer B, the surface treated layer B comprising silver and tin, or copper and tin, wherein the surface treated layer B has on its surface an oxidized layer comprising tin and oxygen, the atomic ratio of oxygen to tin in the oxidized layer is 0.5-1.8 and the thickness of the layer is not more than 20 nm.

Abstract: A semiconductor device lead frame made of copper or a copper alloy used for a resin sealing type semiconductor device, comprising a lead frame body made of copper or a copper alloy, a double-layer under plating film formed on the lead frame body and comprising a lower layer made of zinc or a copper-zinc alloy and an upper layer made of copper having a thickness of 0.02 to 0.4 &mgr;m and a precious metal plating film formed on at least a wire bonding portion of an inner lead of the copper upper layer of the under plating film. This lead frame is excellent in adhesion with a sealing resin, is free from contaminate a precious metal plating solution (particularly a silver plating solution), has a good appearance of the precious metal plating film, is excellent in corrosion resistance and moisture resistance, and has a good appearance and adhesion of an external solder plating film.

Abstract: A stress shield made of a material having a coefficient of thermal expansion similar to that of the material used in the fabrication of a microelectronic die, including but not limited to silicon, molybdenum, and aluminum nitride. The stress shield abuts at least one corner and/or edge of the microelectronic die. When the stress shield is positioned to abut the microelectronic die comers and/or edges, the mechanical stresses on the microelectronic die are greatly reduced or substantially eliminated.

Abstract: A lead frame device having a lead frame made of copper, copper alloy or copper compound having a die pad area, within which a chip is to be mounted, and having a multiplicity of leads, which are arranged around the die pad area; and having a die pad made of silicon which is mounted in the die pad area on the lead frame to accommodate the chip.

Abstract: A lead frame for a semiconductor device includes a sheet-like body and a Pd coating plated on the sheet-like body. The Pd coating includes Ni in an amount of not more than 2%. In another embodiment, the Pd coating includes Cu in an amount of not more than 0.12%. By virtue of limiting the amount of Ni or Cu to these particular levels, the solderability of the lead frame is remarkably enhanced.

Abstract: A lead frame comprising a plurality of leads and a die pad disposed at a position surrounded by top ends on one side of the leads, wherein at least the outermost layer on the obverse of the die pad comprises a nickel plated layer, as well as a semiconductor device comprising the lead frame and a semiconductor element mounted by way of a bonding agent on the nickel plated layer at the obverse of the die pad.

Abstract: A lead frame for a semiconductor package includes a base metal layer made of copper (Cu), Cu alloy or iron-nickel (Fe-Ni) alloy, an underlying plating layer formed on at least one surface of the base metal layer and made of Ni or Ni alloy, an intermediate plating layer formed on the underlying plating layer to a thickness of about 0.00025 to about 0.1 &mgr;m (about 0.1 to about 4 microinches) and made of palladium (Pd) or Pd alloy, and an outer plating layer formed in the intermediate plating layer to a thickness of about 0.05 to about 0.75 &mgr;m (about 2 to 30 microinches) and made of silver (Ag) or Ag alloy. Since an Ag plated layer is formed as the outer plating layer, excellent oxidation resistance and corrosion resistance can be exhibited even under a high-temperature thermal condition, thereby improving wire bondability, solderability and good adhesion with epoxy for use in the semiconductor package, and preventing heel crack at a wire bonding portion.

Abstract: In accordance with a first aspect of the invention, a metal substrate is provided with a layer of tin or tin alloy that is coated under tensile stress to inhibit the growth of tin whiskers. The tensile stressed tin and tin alloy is preferably coated with a grain size larger than 1 micrometer. Advantageously the tin or tin alloy is coated on an underlayer chosen to maintain or generate the tensile stress state in the tin coating. The tensile stress inhibits whisker growth, and the resulting structure is particularly useful as a part of an electrical connector or lead frame. In a second aspect of the invention, the tensile stress of tin coatings is monitored to provide coatings of reduced tendency toward whisker growth.

Abstract: A multilayer lead frame for decoupling a power supply to a semiconductor die includes overlaying first and second lead frame bodies having an insulator disposed therebetween and at least one main lead finger extending from each body. The bodies act as a capacitor to decouple the power supply to the die. One of the bodies and respective finger provides one of power supply and ground connections for wire bonding with the die, and the other of the bodies provides the other of power supply and ground connections for wire bonding with the die. The first body includes a die paddle for supporting the die, and the second body includes a plate for overlaying the paddle with the insulator disposed between the paddle and plate, thereby providing an electrical decoupling effect therebetween upon supplying power and ground connections, respectively.

Abstract: A leadframe for use with integrated circuit chips comprising a plated layer of gold selectively covering areas of said leadframe intended for solder attachment; and said gold layer providing a visual distinction to said areas.

Abstract: In accordance with the invention, a metal substrate is coated with a multilayer finish comprising a layer of tin or tin alloy and one or more outer metal layers. An optional metal underlayer may be disposed between the substrate and the tin. In an exemplary embodiment the metal substrate comprises copper alloy coated with a nickel underlayer, a layer of tin and an outer metal layer of palladium. The resulting structure is particularly useful as an electrical connector or lead frame.

Abstract: Flexible leads for making electrical connection in microelectronic components includes two metallic layers. The structural or core layer of the lead is formed having a hardness greater than the hardness of the second layer. The relative hardness between the first and second layers is achieved by controlling the grain size during deposition of the respective layers from an electroless or electroplating bath.

Abstract: In a lead frame used for forming semiconductor package, a roughened plating layer 10 with excessive uneven surface is formed at least on the surface of lead frame brought into contact with molding compound 7 and metallic plating is made on areas of the rough surface 10 needed for wire bonding to form plating portions for connection. The surface of lead frame at least brought into contact with molding compound is covered with roughened plating layer 10 with excessive uneven surface so that the adhesion of molding compound to the lead frame is excellent due to the function of the roughened plating layer anchoring molding compound 7 to the lead frame. Therefore, the package crack and the cut of wires do not occur.

Abstract: A lead frame for a semiconductor package and a method for manufacturing the lead frame. In the manufacture of the lead frame, a protective layer is formed with nickel (Ni) or Ni alloy on a metal substrate, an intermediate layer is then formed with palladium (Pd) or Pd alloy on the protective layer. Then, Pd and gold (Au) are alternately plated on the surface of the intermediate layer to form an outermost layer including both Pd and Au particles thereon.

Abstract: In accordance with the invention, a packaged electronic device comprises at least one electronic device and leads sealed within a protective package. The leads comprise a conductive metal substrate having a composite metal finish with a total thickness of 1000 Å or less. The finish comprises, in succession from the substrate, 25-750 Å of palladium alloy and 5-250 Å of wirebondable and solderable material. The substrate is advantageously nickel-plated copper alloy or Fe—Ni alloy. The content of palladium in the palladium alloy coating can range from 10-95 weight percent. This finish meets requirements of wirebonding and solderability at a thickness surprisingly lower than previously used packaging finishes.

Abstract: A lead frame, for a plastic molded type semiconductor package, comprises a plurality of leads and a die pad surrounded by the leads wherein a surface of the die pad is adapted for mounting a semiconductor chip. Areas on the leads adapted for wire bonding are plated with at least one noble metal. The lead frame is characterized in that the at least one noble metal is plated on the surface of die pad in a manner that a central region as well as at least a portion of the brim region of the die pad are kept un-plated. In the lead frame of the present invention, bare copper surface on the un-plated region of the die pad provides improved adhesion to molding compound thereby enhancing the reliability of the finished package. The lead frame may be further provided with a rectangular groove, cavities, mesh-type notches, or through-holes formed in the un-plated brim region of the die pad thereby providing mechanical interlock mechanism to strengthen the bonding between the die pad and the package body.

Abstract: The substrate according to the present invention is comprised of a silver/gold/grain element alloy layer, wherein the alloy forms an outside layer of the product. The grain element is selected from a group consisting of selenium, antimony, bismuth, nickel, cobalt, indium and combination thereof. The present invention has a particular application in forming the outside layer of various items, including a lead frame, a ball grid array, a header, a printed circuit board, a reed switch and a connector.