Abstract: A leadframe for use in the assembly of integrated circuit chips comprising a base metal structure having an adherent layer of nickel covering said base metal; an adherent film of palladium on said nickel layer; and an adherent layer of palladium on said palladium film, selectively covering areas of said leadframe suitable for bonding wire attachment and solder attachment.

Abstract: A semiconductor chip is bonded with a polyimide bonding agent to a lead frame of a copper alloy which has been plated with copper. The electrode of the semiconductor chip is connected to each terminal of the lead frame with a wire mainly comprising gold or copper and bonded portions between the semiconductor chip and the wires and between the lead frame and the wires are sealed with a resin. Thus, a semiconductor device can be manufactured.

Abstract: The present invention is directed to a lead frame in which the metal lead frame substrate is copper, copper alloy, or iron alloy. The lead frame substrate is coated with a conformable nickel coating that is crack-resistant when the lead frame is bent to an angle of at least about 82 degrees with a bend radius of about 100 &mgr;m to about 300 &mgr;m. Bending the lead frame in this manner causes surface deformations in the lead frame substrate. Cracks do not appear through the thickness of the conformable nickel coating of the present invention when the depth of the deformations that result from this bending do not exceed about 5 &mgr;m.

Abstract: A lead frame made from Ni, a Ni alloy, Cu, a Cu alloy, Fe or an Fe alloy, comprising an inner lead part with a surface treatment layer of Ag or a Ag-containing alloy and an outer lead part with a surface treatment layer of an alloy containing Ag and Sn, wherein the latter surface treatment layer has a brightness of not less than 0.6 and Sn has the body-centered tetragonal lattice with the crystal orientation indices of from 1.5 to 5 at the (220) plane, not more than 0.9 at the (211) plane and not less than 0.5 at the (200) plane. The surface treatment layer is plated with utilization of a plating solution which contains one or more selected from alkane sulfonic acid, alkanol sulfonic acid and sulfamine acid as the acid component, one or more of tin methane-sulfonate and SnO as a tin salt, and one or more slected from silver methane-sulfonate, Ag2O and AgO as a silver salt.

Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal; a plated layer of lead-free solder on the nickel layer, selectively covering areas of the leadframe intended for attachment to other parts; a plated layer of palladium on the nickel layer, selectively covering areas of the leadframe intended for bonding wire attachment, and a plated layer of silver on both the palladium and solder layers, the silver on the solder intended to dissolve completely into the solder upon heating.

Abstract: A leadframe for use with integrated circuit chips Comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding wire attachment; and a plated layer of solder on said nickel layer, selectively covering areas of said leadframe intended for parts attachment.

Abstract: A lead frame comprises: outer leads formed by a metal base member; first interconnection film portions formed by a metal plating layer, each of which is disposed inside the outer leads in such a manner as to be connected to an inner end of one principal plane of the corresponding one of the outer leads, and at least one second interconnection film portion formed by the metal plating layer, which is disposed inside the outer leads in such a manner as not to be connected to the outer leads; and an insulating film formed to cover planes, opposed to the outer leads, of the first and second interconnection film portions, thereby holding the first and second interconnection film portions; wherein planes, opposed to the insulating film, of the first and second interconnection film portions are taken as semiconductor element mounting planes.

Abstract: In accordance with the invention, a metal substrate is coated with a multilayer surface finish comprising, in succession, an amorphous metal underlayer, a corrosion-resistent metal middle layer and one or more outer layers of precious metal. In an exemplary embodiment the metal substrate comprises copper alloy, the amorphous metal underlayer is Ni—P, the middle layer is nickel and the outer layer is palladium. The resulting structure is particularly useful as an electrical connector.

Abstract: A metal frame patterned by die stamping has the outermost end portion of each patterned pin extending freely, without constraints, from a line of metal bridge connections (dam bar). The end face of each pin is also covered, as well as other surfaces of the frame, by a coating layer or multilayer of metals different from the metal of the die stamped frame. The coating layer or multilayer contains at least on its outer surface, a noble metal such as palladium or gold. The tip of the pins are not subject to cutting and/or trimming after plating the die stamped frame. The pins are not even cut or trimmed during separation of the patterned frame from the surrounding metal at the end of the encapsulation process, when the pins are then eventually bent into shape.

Abstract: A conductive plastic lead frame and method of manufacturing same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment, the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A conductive plastic lead frame and method of manufacturing same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A method of assembling a substrate and an electrical or electronic component, the component having electrically conductive leads with surfaces of an alloy from the list consisting of tin, nickel, tin copper, tin silver, nickel palladium, gold palladium, and silver palladium, and the leads being soldered to copper-based terminals of the substrate by a solder alloy, the solder alloy comprising, by weight, 99.3% tin and 0.7% copper. The soldering takes place in a chamber having a nitrogen inert atmosphere. Lead solder is thus avoided.

Abstract: A multi-layer lead frame for decoupling a power supply to a semiconductor die includes overlaying first and second lead frame bodies having an insulator disposed therebetween and at least one main lead finger extending from each body. The bodies act as a capacitor to decouple the power supply to the die. One of the bodies and respective finger provides one of power supply and ground connections for wire bonding with the die, and the other of the bodies provides the other of power supply and ground connections for wire bonding with the die. The first body includes a die paddle for supporting the die, and the second body includes a plate for overlaying the paddle with the insulator disposed between the paddle and plate, thereby providing an electrical decoupling effect therebetween upon supplying power and ground connections, respectively.

Abstract: A molded elecronic component such as a solid electrolyte capacitor comprising a capacitor element including a cathode layer, an anode lead, a pre-plated anode lead terminal connected to the anode lead, a pre-plated cathode lead terminal connected to the cathode layer, and an insulating member which encapsulates the capacitor element and leaves a portion of the anode and cathode lead terminals exposed. The encapsulated portions of the pre-plated anode and cathode lead terminals have a plating layer formed thereon containing organic substances in an amount of 0.03 wt. % or less. Also disclosed is a process for manufacturing the solid electrolyte capacitor.

Abstract: The invention provides means for effectively preventing a wire disconnection generated due to an increase of calorie applied to a semiconductor integrated circuit device. The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 &mgr;m is provided in the connecting member.

Abstract: A layered lead is disclosed including a layer of structural material which has top and bottom sides, a layer of fatigue-resistant material on the top and bottom surfaces and a layer of bonding material covering the fatigue-resistant layer on the bottom surface for connection to a contact on a chip. An asymmetrical distribution of bonding material on the top and bottom sides may be used to provide reinforcement of the lead against stress. The fatigue-resistant material also acts as a barrier against diffusion between the metal layers.

Abstract: A palladium plated lead frame (34) for integrated circuit devices has a nickel strike (36) and a palladium/nickel alloy layer (38) separating the copper base metal (28) from the nickel intermediate layer (40) in order to prevent a galvanic potential from drawing copper ions from the base metal layer (28) to the top layer (42). The nickel strike (36) and palladium/nickel alloy layer (38) also reduce the number of paths through which a copper ion could migrate to the top surface resulting in corrosion.

Abstract: A multi-chip chip scale package. A film carrier is in use. Two chips with different sizes can be disposed on the same film carrier. The flip chip technique is used to arrange each chip on each side of the film carrier face to face. A bump is formed on each chip to electrically connect with the film carrier. An insulation material is infilled between the chips to leave one side of each chip exposed. The conductive wires of the film carrier are connected with the chip directly without going through other carrier.

Abstract: A leadframe is provided which has an integrated resistive element incorporated within the leadframe. The resistive element suitably comprises a material that can provide a temperature coefficient of under 500 ppm/° C., preferably approximating 100 ppm/° C. or less. Exemplary embodiments of the resistive material may include Constantan or Manganin. The leadframe and integrated resistive element may be utilized in a variety of integrated circuit applications, such as a current monitoring circuit. Accordingly, variations in temperature will not dramatically affect the accuracy of any integrated circuit devices during operation. Additionally, after encapsulation of the leadframe and integrated resistive element and any such integrated circuit device, the gain of the encapsulated circuit may be suitably adjusted by various calibration techniques.

Abstract: Disclosed is a semiconductor device provided with a heat-sink. The semiconductor device comprises a laminated insulating film formed on the heat-sink, a lead-frame mounted on the laminated insulating film, a semiconductor chip mounted to the lead-frame, and a molding resin for molding the semiconductor chip. The laminated insulating film comprises a first insulating resin layer formed on the side of the heat-sink and a second insulating resin layer formed on the side of the lead-frame. The first insulating resin layer is made of an epoxy resin containing 80 wt % of a heat dissipating filler. Also, the second insulating resin layer is made of an epoxy resin containing 70 wt % of a heat dissipating filler.

Abstract: A wafer frame for fixing and handling 200 mm wafers is produced with a significantly reduced weight as compared to a metal wafer frame, while maintaining mechanical and thermal material properties. This is accomplished by producing the wafer frame from a plastic with a glass fiber content of from 1 to 40% by weight.

Abstract: A semiconductor package, and a method for fabricating the package are provided. The package includes a semiconductor die, a lead frame, and a metal foil die mounting plate adapted to mount the die to the lead frame. In addition, the die mounting plate provides a thermally conductive path from the die to terminal leads of the package. Further, the die mounting plate can be configured to perform electrical functions, such as providing ground/power planes for the package, and adjusting an impedance of signal paths through the package. In a first embodiment the package can be fabricated using a tape under frame lead frame. In a second embodiment the package can be fabricated using a lead under chip lead frame.

Abstract: A tin-nickel alloy containing not less than 75 wt % and less than 100 wt % of tin with the balance of nickel. The alloy is used, for example, for formation of a surface treatment layer of an electronic component which is to be soldered onto a substrate with the use of the surface mount technology. The surface treatment layer preferably has a thickness of not less than 0.1 &mgr;m and less than 0.5 &mgr;m. The electronic component preferably further includes a nickel deposit layer as an underlying layer interposed between a base of the component and the surface treatment layer.

Abstract: A leadframe having the desirable features of palladium plated leadframes, such as compatibility with both wire bonding and solder reflow, as well as good adhesion to molding compounds is provided by plating the interior lead frame portions with one microinch of palladium and the external leads which contact solder with three microinches of palladium. A low cost method for fabricating the leadframe based on a unique combination of proven processes is provided.

Abstract: An integrated circuit package for improved warp resistance and heat dissipation is described. The LOC package includes: an integrated circuit die having an upper, active face, and a multi-layered, substantially planar lead frame mounted to the active face of the die, where the lead frame is preferably comprised of layers configured as Cu/INVAR/Cu or Cu/Alloy 42/Cu. The choice of the middle layer of the lead frame is selected to minimize the warping forces on the package such that the coefficient of thermal expansion of the composite lead frame approximates that of silicon. The copper layers of the lead frame provide improved heat dissipation.

Abstract: A lead frame lead and method of fabrication of the leadframe. A leadframe is formed from one of copper or copper-based material having a layer of an alloy of palladium and nickel and a coating of palladium formed over the alloy on the leadframe. The coating of palladium is from about 3 to about 10 microinches and preferably about 3 microinches. The palladium/nickel layer is from about 10 to about 40 microinches and preferably about 10 microinches and is an alloy having from about 40 to about 90 percent by weight nickel and the remainder essentially palladium. A preferred ratio is 75 percent by weight nickel and 25 percent by weight palladium. A semiconductor device is fabricated by providing a copper or copper-based leadframe and forming a layer of the palladium/nickel alloy over the entire leadframe followed by a palladium layer thereover while maintaining the assembly temperature below about 180 degrees C during subsequent device assembly.

Abstract: A semiconductor-chip is bonded to a chip-carrier substrate by way of a gold-to-gold bonding interface. A vacuum chuck is provided to physically hold the semiconductor-chip in physical contact with, the chip-carrier substrate as static force, ultrasonic power, and an elevated temperature are applied to two mating gold surfaces that are formed by two continuous and physically mating gold layers. The bonded assembly is encased in a potting ceramic, or the bonded assembly is encased in a housing that includes a transparent cover that enables use as an optoelectronic semiconductor device.

Abstract: In one embodiment, the present invention relates to a method of forming a silicon-on-insulator substrate involving providing a metal wafer; forming a low melting point oxide layer over the metal wafer; forming a first insulation layer over the low melting point oxide layer to provide a first structure; providing a second structure comprising a silicon layer and a second insulation layer; bonding the first structure and the second structure together so that the first insulation layer is adjacent the second insulation layer forming a buried insulation layer; and removing a portion of the silicon layer thereby providing the silicon-on-insulator substrate comprising a silicon device layer, the buried insulation layer, the low melting point oxide layer, and the metal wafer.

Abstract: A multi-layer plated lead frame is provided. The lead frame has a structure in which a first precious metal plating layer, an intermediate plating layer, and a second precious metal plating layer are sequentially formed on a substrate made of ferroalloy. The lead frame shows improvement in all properties including wire bonding, anti-corrosion, and solderability.

Abstract: A lead frame plating method including the steps of (a) forming an intermediate layer on the upper surface of a metal substrate, (b) submerging the metal substrate into a plating solution, and (c) forming a passive layer to a thickness of 0.01 to 1.5 microinches on the upper surface of the intermediate layer by applying a modulated current to the plating solution and the metal substrate.

Abstract: Disclosed are a lead frame for a semiconductor device, and a semiconductor device using the lead frame. Inner leads and outer leads of the lead frame are formed to have such a sectional structure that a film of Pd or a Pd alloy is formed on both surfaces or a rear surface of a lead frame directly or through an undercoat, and an Au-plated film is formed on a part of the film of Pd or a Pd alloy. Pd and Au are not applied to unnecessary areas, thus resulting in higher economical and production efficiency. The lead frame has good quality, is economical and has superior productivity. Wires connecting a semiconductor chip and the inner leads have a good connection property and joint portions of the outer leads to an external device also have a good connection property.

Abstract: A differential pressure sensor (10) has a sensor die (30) eutectically attached to a mounting flag (14). The mounting flag has a similar coefficient of thermal expansion to the sensor die. The eutectic attachment provides a hermetic seal between the mounting flag and the sensor die. Pressure is applied to sensor die port (20). A molded housing (12) is molded around the sensor die-mounting flag assembly. Port (22) in the molded housing is filled with a silicone gel (52). A second pressure source is transferred by way of the silicone gel to the sensor die. Any media entering port (20) contacts the first surface of the sensor die to assert pressure against a piezoresistive transducer circuit (32) to generate the electrical signals representative of the applied pressure but are isolated from the sensitive interconnects by the hermetic seal.

Abstract: A high temperature metallization system for use with a semiconductor device (23). The semiconductor device (23) has a multi-layer metallization system (36). An adhesion layer (37) of the metallization system (36) is formed on a semiconductor substrate (20). A barrier layer (38) that contains a nickel alloy is formed on the adhesion layer (37). A protective layer (39) is formed on the barrier layer (38). The barrier layer (38) inhibits solder components from diffusing toward the semiconductor substrate (20) during high temperature processing.

Abstract: A multi-layer lead frame for decoupling a power supply to a semiconductor die includes overlaying first and second lead frame bodies having an insulator disposed therebetween and at least one main lead finger extending from each body. The bodies act as a capacitor to decouple the power supply to the die. One of the bodies and respective finger provides one of power supply and ground connections for wire bonding with the die, and the other of the bodies provides the other of power supply and ground connections for wire bonding with the die. The first body includes a die paddle for supporting the die, and the second body includes a plate for overlaying the paddle with the insulator disposed between the paddle and plate, thereby providing an electrical decoupling effect therebetween upon supplying power and ground connections, respectively.

Abstract: An integrated circuit heat transfer element (6,30) is made by selecting thermally conductive fibers having aspect ratios of length to diameter of more than 1, selecting a resin and combining the fibers and the resin to create a formable resin/fiber compound. The resin/fiber compound is formed into a composite material in part by applying pressure to the formable resin/fiber compound, which aligns the fibers, and when cured creates a thermally anisotropic composite material to maximize heat conduction along the aligned fibers. The thermally anisotropic composite material has a coefficient of thermal expansion (CTE) of less than about 10.times.10.sup.-6 cm/cm/.degree. C. The composite material has a thermal conductivity in the direction of the carbon fibers of at least 50 W/m.degree. K. The IC device is preferably secured to the heat transfer element using a thermally conductive adhesive.

Abstract: In a semiconductor device having a lead-on-chip structure, a thin plate is arranged in an outer peripheral area of a semiconductor element and has a thickness substantially the same as that of the semiconductor element.

Abstract: In a lead frame formed out of at least one metal selected from the group consisting of nickel and nickel alloys, copper and copper alloys and iron and iron alloys, the inner lead part is provided with a surface treatment layer of Ag or an alloy containing silver and the outer lead part is provided at least with a surface treatment layer of an alloy containing silver and tin of the body-centered cubic structure preferentially oriented in the (101) plane and/or the (211) plane. According to the above-mentioned structure, a semiconductor device that uses a lead frame for electronic parts which does not contain lead, one of the environmentally harmful pollutants, has good characteristics including solder wettability and bonding strength and is of low cost and a process for producing the device are provided.

Abstract: The lead frame includes outer leads plated with tin (Sn) alloy so as to withstand the high temperatures generated during a subsequent semiconductor packaging process. In addition to the outer leads, the lead frame includes a die pad and inner leads composed of a base metal, such as copper (Cu), a copper alloy, or a nickel alloy. The die pad and the inner leads are plated with silver for improved conductivity. In order to withstand relatively high temperatures as well as to resist corrosion and have good solder wettability, the outer leads are preferably plated with a tin antimony alloy, such as a tin-antimony alloy consisting of 90.+-.5 weight percent of tin and 10.+-.5 weight percent antimony. Alternatively, the outer leads can be plated with a tin-antimony-lead alloy, such as a tin-antimony-lead alloy consisting of 10.+-.5 weight percent of tin, 10.+-.5 weight percent of antimony and 80.+-.10 weight percent of lead. A method of plating a lead frame is also provided.

Abstract: Disclosed is a plastic package for storing a chip, the plastic package being further improved in moisture resistance and reduced in manufacturing costs. The plastic package comprises a plastic package body for storing a chip and a lead electrically connected with the chip, wherein an oxide layer is formed on the surface of a part of the intermediate portion of the lead, the part of the intermediate portion being allowed to adhere to a plastic.

Abstract: A multi-leadframe die assembly is disclosed including a die bonded to a die paddle. A second lead frame including leads is superimposed and bonded onto the first lead frame. Also disclosed is a method for fabricating the multi part lead frame assembly which utilizes equipment designed for single lead frame processing. If desired, the materials for the multi part lead frame may be dissimilar.

Abstract: A platform carries an integrated circuit (IC) (20) for handling and alignment through wire bonding operations, provides interconnections, and supports the shielded IC with uniform, controlled adhesive thickness. The platform base (10) has a flat portion which may have a slot (30) extending the length of a chip with wire-bond pads (140). The IC is mounted to the platform base with cast or contained adhesive, epoxy, or tape (50), which provides at least one adhesive surface. For several rows of wire-bond pads, there may be several slots. If the platform carries more than one chip, the platform base may have one or more slots (30, 40) per chip. A platform may carry other components (110, 120). Circuitry (90) may be printed on one or both sides of the platform base, with moderate resistivity to damp ringing of noise signals. Wire bonds are made through the slot (30), connecting IC pads with circuitry.

Abstract: A functionally gradient material having desired characteristics without having any joining section is efficiently obtained by means of integration effected by a sintering treatment, the functionally gradient material comprising a metal part composition containing predetermined components based on a basic composition of tungsten and copper and a ceramic part composition containing predetermined components based on a basic composition of aluminum nitride and aluminum. Therefore, the metal and the ceramic are integrated into one unit without providing any joining section to give a high joining reliability and high thermal conductivity.

Abstract: A semiconductor lead frame and a fabricating method thereof are provided. The semiconductor lead frame includes a metal substrate, and a multi-layered plating layer including a copper-nickel alloy layer formed on the metal substrate, and a palladium or palladium alloy layer formed on the copper-nickel alloy layer.

Abstract: A lead frame for a semiconductor device, made of a copper alloy, capable of preventing the creation of delamination between encapsuling resin and attributable to a lead frame without sacrificing the wire bondability and, a process for producing the lead frame and a semiconductor device using the lead frame. According to the present invention, (1) there is provided a lead frame for a plastic molded type semiconductor device, made of a copper alloy material partially plated with at least one noble metal, for wire bonding or die bonding purposes, selected from silver, gold, and palladium, wherein the whole area or a predetermined area of the surface of the copper at least on its side to be contacted with a encapsuling resin has a thin noble metal plating of at least one member selected from silver, gold, platinum, and palladium.

Abstract: The present invention relates to a semiconductor device, and more particularly, it aims at providing a semiconductor device which is excellent in workability of assembly and reduces the assembly cost in a semiconductor device packaging a power device and a control device controlling this power device.In order to attain the aforementioned object, it shows a lead frame (10) before mounting a power device (PD) and a control device (CD), and a region where a gold wire (W2) is arranged and a region where the power device (PD) is arranged are silver-plated regions (A). Further, a region where an aluminum wire (W1) is arranged is a nickel-plated region (B). Further, a power device die pad (1A) is connected to a tie bar (5) and a frame (6) by suspension leads (40 to 45), and supported in three directions. Further, an intermediate lead (3A to 3D) is formed in the vicinity of the control device (CD).

Abstract: A leadframe for an IC package and a method of manufacturing the same are provided. The leadframe can be manufactured in such a manner as to provide suitable bondability, molding compound characteristic, and solderability. The leadframe includes a base structure made from a conductive material. A silver plating is formed over the base structure of the leadframe, and a palladium plating is formed over the silver plating. Depending on actual requirements, a copper layer and a nickel plating can be formed between the silver plating and the base structure of the leadframe, and a palladium/nickel plating can be formed between the silver and palladium platings. Further, a gold layer can be formed over the palladium plating. The palladium plating and the palladium/nickel plating can be formed all over the leadframe or selectively formed only in the external-lead area of the leadframe.

Abstract: A method for manufacturing a lead frame includes degreasing and activating the surface of a metal sheet, providing the plating solution containing nickel(II) sulfamate tetrahydrate, (Ni(H.sub.2 NSO.sub.3).sub.2.4H.sub.2 O), manganese(II) sulfamate tetrahydrate (Mn(H.sub.2 NSO.sub.3).sub.2.4H.sub.2), nickel (II) chloride hexahydrate (NiCl.sub.2.6H.sub.2 O) and boric acid, plating the metal sheet in the plating solution to form a Ni--Mn alloy layer, and forming a Pd or Pd alloy layer on the Ni--Mn alloy layer.

Abstract: A multi-layer lead frame for decoupling a power supply to a semiconductor die includes overlaying first and second lead frame bodies having an insulator disposed therebetween and at least one main lead finger extending from each body. The bodies act as a capacitor to decouple the power supply to the die. One of the bodies and respective finger provides one of power supply and ground connections for wire bonding with the die, and the other of the bodies provides the other of power supply and ground connections for wire bonding with the die. The first body includes a die paddle for supporting the die, and the second body includes a plate for overlaying the paddle with the insulator disposed between the paddle and plate, thereby providing an electrical decoupling effect therebetween upon supplying power and ground connections, respectively.

Abstract: A lead frame has a metal substrate directly coated with a palladium alloy layer to prevent diffusion of metal molecules from the metal substrate. The lead frame does not contain a nickel intermediate layer, thereby preventing the diffusion of nickel molecules which makes soldering difficult, and enhancing production.

Abstract: An integrated circuit package for improved warp resistance and heat dissipation is described. The LOC package includes: an integrated circuit die having an upper, active face, and a multi-layered, substantially planar lead frame mounted to the active face of the die, where the lead frame is preferably comprised of layers configured as Cu/INVAR/Cu or Cu/Alloy 42/Cu. The choice of the middle layer of the lead frame is selected to minimize the warping forces on the package such that the coefficient of thermal expansion of the composite lead frame approximates that of silicon. The copper layers of the lead frame provide improved heat dissipation.