Abstract: A chip package includes: a substrate having a first and a second surfaces; a device region formed in or disposed on the substrate; a dielectric layer disposed on the first surface; at least one conducting pad disposed in the dielectric layer and electrically connected to the device region; a planar layer disposed on the dielectric layer, wherein a vertical distance between upper surfaces of the planar layer and the conducting pad is larger than about 2 ?m; a transparent substrate disposed on the first surface; a first spacer layer disposed between the transparent substrate and the planar layer; and a second spacer layer disposed between the transparent substrate and the substrate and extending into an opening of the dielectric layer to contact with the conducting pad, wherein there is substantially no gap between the second spacer layer and the conducting pad.

Abstract: An optical sensor package has a transparent substrate with a redistribution layer formed on a face thereof, which includes a window and a plurality of electrically conductive traces. A semiconductor substrate, including an optical sensor and a plurality of contact terminals on a face thereof, is positioned on the transparent substrate in a face-to-face arrangement, with the optical sensor directly opposite the window, and with each of the contact terminals electrically coupled to a respective one of the electrically conductive terminals. The transparent substrate has larger overall dimensions than the semiconductor substrate, so that one or more edges of the transparent substrate extend beyond the corresponding edges of the semiconductor substrate. A plurality of solder balls are positioned on the face of the transparent substrate, each in electrical contact with a respective one of the electrically conductive terminals.

Abstract: A method for producing a rollable web with successive antennas, where an electronic chip is attached to an antenna in a predetermined position. The position of an electronic chip changes with respect to the antenna when compared to at least some of the chips within individual and successive antennas. A rollable web includes successive antennas, where electronic chips are attached to antennas in a predetermined position. In the rollable web, the position of a chip changes with respect to the antenna compared to at least some of the chips within individual and successive antennas.

Abstract: A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.

Abstract: To provide a package for light emitting element accommodation that realizes enhanced reflectance without application of a metal plating onto a ceramic. There is provided a package for light emitting element accommodation comprising ceramic substrate (2) having conductor mounting region (8) for mounting of light emitting element (1) on its upper surface; frame (4) of a light reflecting material containing 74.6 mass % or more of alumina whose average particle diameter after sintering is 2.5 ?m or less, the frame (4) disposed on an upper surface of the substrate (2) in such a fashion that internal circumferential surface (7) of through-hole (3) expands outward; and light emitting element (1) mounted on the conductor mounting region (8) of the substrate (2). Thus, the reflectance of the frame (4) is enhanced without application of a metal plating thereonto.

Abstract: An electrooptical device substrate, contains: a first insulating film provided on a substrate; two or more pixels; a first concave portion provided in the first insulating film over the two or more pixels; a second concave portion provided on the bottom surface of the first concave portion; a thin film transistor containing an organic semiconductor layer provided in the second concave portion, a gate insulating film provided on the organic semiconductor layer, and a gate electrode provided on the gate insulating film and being matched to one pixel among the two or more pixels; a scanning line which is provided at an upper side with respect to the gate insulating film and provided in the first concave portion over the two or more pixels; and a data line electrically connected to the thin film transistor.

Abstract: A semiconductor device includes a multilayer wiring substrate and a double-sided multi-electrode chip. The double-sided multi-electrode chip includes a semiconductor chip and has multiple electrodes on both sides of the semiconductor chip. The double-sided multi-electrode chip is embedded in the multilayer wiring substrate in such a manner that the double-sided multi-electrode chip is not exposed outside the multilayer wiring substrate. The electrodes of the double-sided multi-electrode chip are connected to wiring layers of the multilayer wiring substrate.

Abstract: A semiconductor device includes an IPD structure, a first semiconductor die mounted to the IPD structure with a flipchip interconnect, and a plurality of first conductive posts that are disposed adjacent to the first semiconductor die. The semiconductor device further includes a first molding compound that is disposed over the first conductive posts and first semiconductor die, a core structure bonded to the first conductive posts over the first semiconductor die, and a plurality of conductive TSVs disposed in the core structure. The semiconductor device further includes a plurality of second conductive posts that are disposed over the core structure, a second semiconductor die mounted over the core structure, and a second molding compound disposed over the second conductive posts and the second semiconductor die. The second semiconductor die is electrically connected to the core structure.

Abstract: A semiconductor package includes a print circuit part, a lower chip, an upper chip, a thermal conductivity part, and an encapsulation resin. The lower chip and the upper chip are mounted on the print circuit part through wire bonding connection. The thermal conductivity part efficiently dissipates heat from the chips to the outside of the package. The encapsulation resin entirely seals the package while exposing the thermal conductivity part. A adhesive sheet is hardened to form a bonding layer between the thermal conductivity part and the upper chip, a bonding layer between the semiconductor chips, and a bonding layer between the semiconductor chip and the wired component. The configuration contributes to miniaturization, high integration, and heat resistance reduction of a semiconductor package using high-heat-generating ICs.

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The central region of the second surface can be disposed between the first and second axes. The terminals can be configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of a memory storage array within the microelectronic elements.

Abstract: A semiconductor device 1 has a semiconductor chip 10. The semiconductor chip 10 is constituted as having a semiconductor substrate 12 and an interlayer insulating film 14 on the semiconductor substrate 12. The semiconductor substrate 12 has a plurality of through electrodes 22 (first through electrodes) and a plurality of through electrodes 24 (second through electrodes) formed therein. On the top surface S1 (first surface) of the semiconductor chip 10, there are provided connection terminals 32 (first connection terminals) and connection terminals 34 (second connection terminals). The connection terminals 32, 34 are connected to the through electrodes 22, 24, respectively. The connection terminals 32 herein are disposed at positions overlapping the through electrodes 22 in a plan view. On the other hand, the connection terminals 34 are disposed at positions not overlapping the through electrodes 24 in a plan view.

Abstract: A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The second surface can have a central region disposed between the first and second axes. Each microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. The terminals can be configured to carry all of the address signals transferred to the microelectronic package.

Abstract: In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region.

Abstract: A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.

Abstract: The present invention provides a semiconductor device which is formed at low cost and has a great versatility, a manufacturing method thereof, and further a semiconductor device with an improved yield, and a manufacturing method thereof. A structure, which has a base including a plurality of depressions having different shapes or sizes, and a plurality of IC chips which are disposed in the depressions and which fit the depressions, is formed. A semiconductor device which selectively includes a function in accordance with an application, by using the base including the plurality of depressions and the IC chips which fit the depressions, can be manufactured at low cost.

Abstract: Provided are a semiconductor package and a method for fabricating the same. The semiconductor package includes a lower package comprising a lower substrate, a lower semiconductor chip mounted on the lower substrate and comprising a redistribution, and a molding layer molding the lower semiconductor chip, an upper package comprising an upper substrate and an upper semiconductor chip mounted on the upper substrate, with the upper package being stacked on the lower package. The semiconductor package further includes an electrical interconnector extending from the upper substrate into the molding layer and connected to the redistribution to electrically connect the upper and lower packages to each other, and a dummy interconnector extending from the upper substrate into the molding layer to physically couple the upper and lower packages to each other.

Abstract: A semiconductor package includes a semiconductor chip having a first surface, a second surface located opposite the first surface, and side surfaces connecting the first and second surfaces. The semiconductor chip includes bonding pads disposed on the first surface and having a molding member formed to cover the first surface of the semiconductor chip. The molding member is formed so as to expose the side surfaces of the semiconductor chip. The semiconductor chip also includes bonding members having first ends electrically connected to the respective bonding pads and second ends that are connected to and opposite the first ends. The second ends are exposed from side surfaces of the molding member after passing through the molding member so as to allow various electrical connections.

Abstract: Packaged microelectronic devices and methods of manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a method of manufacturing a microelectronic device includes forming a stand-off layer over a plurality of microelectronic dies on a semiconductor workpiece, and removing selected portions of the stand-off layer to form a plurality of stand-offs with the individual stand-offs positioned on a backside of a corresponding die. The method further includes cutting the semiconductor workpiece to singulate the dies, and attaching the stand-off on a first singulated die to a second die.

Abstract: Microwave or millimeter wave system packaging having a system with a baseplate, transition board and cover. The baseplate includes microwave or millimeter wave components attached thereto. The transition board includes a first connector attached to a first side thereof and operatively connected to the components, and a second connector attached to a second side thereof and operatively connected to the components through the board. The cover and baseplate form a cavity containing the board and components, and the second connector may be operatively connected to a third connector such as a printed circuit board disposed outside of the cavity and on a higher level assembly. The transition board may further include a fourth connector operatively connected to the components for providing a signal to an external component or device or receiving a signal from an external component or device.

Abstract: In a chip package, semiconductor dies in a vertical stack of semiconductor dies or chips (which is referred to as a ‘plank stack’) are separated by a mechanical spacer (such as a filler material or an adhesive). Moreover, the chip package includes a substrate at a right angle to the plank stack, which is electrically coupled to the semiconductor dies along an edge of the plank stack. In particular, electrical pads proximate to a surface of the substrate (which are along a stacking direction of the plank stack) are electrically coupled to pads that are proximate to edges of the semiconductor dies by an intervening conductive material, such as: solder, stud bumps, plated traces, wire bonds, spring connectors, a conductive adhesive and/or an anisotropic conducting film. Note that the chip package may facilitate high-bandwidth communication of signals between the semiconductor dies and the substrate.

Abstract: This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements.

Abstract: In inlets used for ID tags and the like, a defective connection between an integrated circuit part and an antenna is suppressed by improvement of tolerance for a bending or a pressing pressure. The integrated circuit part includes a semiconductor chip and a multilayer substrate having a concave portion. The semiconductor chip is mounted on the bottom of the concave portion. The multilayer substrate includes a connection electrode at the top surface and a connection electrode connected to the semiconductor chip on the bottom of the concave portion. The connection electrode on the bottom of the concave portion is connected to the connection electrode at the top surface by a penetration electrode inside a multilayer substrate. By such a configuration, the semiconductor chip is connected to the antenna.

Abstract: Disclosed are a fabrication process and a device of a multi-chip package having spliced substrates, characterized in utilizing an incomplete substrate and a substrate block with different dimensions to combine as a spliced complete substrate during the fabrication process. Two kinds of chips with different functions, including memory and controller, are disposed on the incomplete substrate and the substrate block, respectively. Then, the incomplete substrate and the substrate block are then spliced together by joining their spliced portions formed on their substrate sidewalls. Finally, an encapsulant is formed on the incomplete substrate and further formed on the substrate block. Accordingly, it is possible to integrate different functional chips into a single multi-chip package by optimizing packaging processing parameters with optimized materials.

Abstract: A method, in which the semiconductor components forming part of an electronic circuit, or at least some of them, are embedded in a base, such as a circuit board, during the manufacture of the base, when part of the base structure is, as it were, manufactured around the semiconductor components. Through-holes for the semiconductor components are made in the base, in such a way that the holes extend between the first and second surface of the base. After the making of the holes, a polymer film is spread over the second surface of the base structure, in such a way that the polymer film also covers the through-holes made for the semiconductor components from the side of the second surface of the base structure. Before the hardening, or after the partial hardening of the polymer film, the semiconductor components are placed in the holes made in the base, from the direction of the first surface of the base.

Abstract: The disclosure facilitates testing and binning of multiple LED chip or other optoelectronic chip packages fabricated on a single semiconductor wafer. The testing can take place prior to dicing. For example, in one aspect, metallization on the front-side of a semiconductor wafer electrically connects together cathode pads (or anode pads) of adjacent sub-mounts such that the cathode pads (or anode pads) in a given column of sub-mounts are electrically connected together. Likewise, metallization on the back-side of the wafer electrically connects together anode pads (or cathode pads) of adjacent sub-mounts such that the anode pads (or cathode pads) in a given row of sub-mounts are electrically connected together. Probe pads, which can be located one or both sides of the wafer, are electrically connected to respective ones of the rows or columns.

Abstract: A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts.

Abstract: Provided are a lead frame, a semiconductor package, and a method of manufacturing the lead frame and the semiconductor package. The lead frame includes: a die pad on which a semiconductor chip is installable; a plurality of lead patterns formed around a circumference of the die pad; an insulating organic material filling etching spaces interposed between the die pad and the lead patterns and structurally supporting the die pad and the lead patterns; and a pre-plating layer formed on both upper and lower surfaces of the die pad and the lead patterns.

Abstract: A semiconductor device has a base substrate having a plurality of metal traces. A conductive polymer cover is provided having an opening. The conductive polymer cover forms a cavity when attached to the base substrate. At least one die is attached to an interior surface of the conductive polymer cover and positioned over the opening. The conductive polymer cover and the at least one die are electrically coupled to metal traces on the first surface of the base substrate.

Abstract: The present invention discloses a semiconductor device package and the method for the same. The method includes preparing a first substrate and a second substrate; opening a die opening window through the second substrate by using laser or punching; preparing an adhesion material; attaching the first substrate to the second substrate by the adhesion material; aligning a die by using the aligning mark of the die metal pad and attaching the die onto the die metal pad with force by the adhesion material; forming a first dielectric layer on top surfaces of the second substrate and the die and pushing the first dielectric layer into gap between the side wall of the die and the side wall of the die opening window under vacuum condition; opening a plurality of via openings in the first dielectric layer; and forming a redistribution layer in the plurality of via openings and on the first dielectric layer.

Abstract: A multi-wavelength semiconductor laser device includes a block having a rectangular groove with a bottom face and two side faces extending in a predetermined direction; and laser diodes with different light emission wavelengths mounted on the bottom face and the side faces of the groove in the block so that their laser beams are emitted in the predetermined direction.

Abstract: A semiconductor device includes: a first substrate made of semiconductor and having first regions, which are insulated from each other and disposed in the first substrate; and a second substrate having electric conductivity and having second regions and insulation trenches. Each insulation trench penetrates the second substrate so that the second regions are insulated from each other. The first substrate provides a base substrate, and the second substrate provides a cap substrate. The second substrate is bonded to the first substrate so that a sealed space is provided between a predetermined surface region of the first substrate and the second substrate. The second regions include an extraction conductive region, which is coupled with a corresponding first region.

Abstract: A method of manufacturing a printed circuit board having a flow preventing dam, including: applying a dry film resist on a base substrate having a solder pad, and then primarily exposing the dry film resist to light; secondarily exposing the primarily exposed dry film resist formed on a peripheral area of the base substrate to light, thus forming a flow preventing dam; removing the unexposed dry film resist to expose the solder pad, thus forming an opening; printing the opening with a solder paste, and then forming a solder bump through a reflow process; and removing the primarily exposed dry film resist.

Abstract: Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane.

Abstract: In at least one aspect, a semiconductor light emitting device may include a first lead, a second lead provided being apart from the first lead, a semiconductor light emitting element provided on the first lead, a wiring electrically connecting the semiconductor light emitting element and the second lead, a first resin being optically transparent to light from the semiconductor light emitting element, the first resin covering the semiconductor light emitting element, and a second resin provided on the first resin, the first lead and the second lead, and being optically transparent to light from the semiconductor light emitting element, wherein a part of the first lead which is covered with the second resin is symmetric with respect to a vertical line passing through the semiconductor light emitting element in a cross-sectional view cut along a plane, the plane passing the semiconductor light emitting element and being parallel with a direction to which the first lead is extended.

Abstract: An integrated circuit package having a selectively etched leadframe strip defining a die attach pad and a plurality of contact pads, at least one side of the die attach pad having a plurality of spaced apart pad portions; a semiconductor die mounted to the die attach pad and wires bonding the semiconductor die to respective ones of the contact pads; a first surface of the leadframe strip, including the semiconductor die and wire bonds, encapsulated in a molding material such that at least one surface of the leadframe strip is exposed, and wherein solder paste is disposed on said contact pads and said at least one side of said die attach pad.

Abstract: A semiconductor chip (1) is provided having an adhesion-promoting-layer-free three-layer metallization (2). The three-layer metallization (2) has an aluminum layer (4) applied directly on the semiconductor chip (1), a diffusion barrier layer (5) applied directly on the aluminum layer (4), and a solder layer (6) applied directly on the diffusion barrier layer (5). Ti, Ni, Pt or Cr is provided as the diffusion barrier layer (5) and a diffusion solder layer is provided as the solder layer (6). All three layers are applied by sputtering in a process sequence.

Abstract: A substrate structure for an image sensor package includes a bottom base and a frame layer. The bottom base has an upper surface formed with a plurality of first electrodes, and a lower surface formed with a plurality of second electrodes. An insulation layer is coated between the first electrodes and in direct surface contact with the upper surface of the bottom base. A frame layer is arranged on and in direct surface contact with the first electrodes and the insulation layer to form a cavity together with the bottom base. The insulation layer is interposed between the bottom base and the frame layer.

Abstract: A recessed portion is provided in first and second insulating films, the first insulating film being stacked on a semiconductor wafer, the second insulating film being stacked on the first insulating film. The first and second insulating films are processed to form wiring in a formation region of the semiconductor wafer in which an acceleration sensor is to be formed. After a sacrificial film is stacked on the wiring and processed, a conductive film is stacked on the wiring and processed to form a plurality of thin film structures in the formation region. The recessed portion surrounds the formation region.

Abstract: A method for manufacturing a display device includes a first step of preparing a first substrate which has a first area to be etched and a second area located at a periphery of the first area and which has a display element on its surface, a second step of etching and removing the first area of the first substrate, a third step of forming a second substrate on a surface of the first substrate that is opposite to the surface on which the display element is located, and a fourth step of removing the second area of the first substrate.

Abstract: A semiconductor device package die and method of manufacture are disclosed. The device package die may comprise a device substrate having one or more front electrodes located on a front surface of the device substrate and electrically connected to one or more corresponding device regions formed within the device substrate proximate the front surface. A back conductive layer is formed on a back surface of the device substrate. The back conductive layer is electrically connected to a device region formed within the device substrate proximate a back surface of the device substrate. One or more conductive extensions are formed on one or more corresponding sidewalls of the device substrate in electrical contact with the back conductive layer, and extend to a portion of the front surface of the device substrate. A support substrate is bonded to the back surface of the device substrate.

Abstract: An integrated circuit package system is provided including forming a wafer having a back side and an active side, forming a recess in the wafer from the back side, forming a cover in the recess, and singulating the wafer at the recess filled with the cover.

Abstract: A light emitting apparatus includes: a substrate including a first conductive type impurity; a first heatsink and a second heatsink on a first region and a second region of the substrate; second conductive type impurity regions on the substrate and electrically connected to the first heatsink and the second heatsink, respectively; a first electrode electrically connected to the first heatsink on the substrate; a second electrode electrically connected to the second heatsink on the substrate; and a light emitting device electrically connected to the first electrode and the second electrode on the substrate.

Abstract: An embodiment of the invention provides a manufacturing method of a chip package including: providing a semiconductor wafer having a plurality of device regions separated by a plurality of scribe lines; bonding a package substrate to the semiconductor wafer wherein a spacer layer is disposed therebetween and defines a plurality of cavities respectively exposing the device regions and the spacer layer has a plurality of through holes neighboring the edge of the semiconductor wafer; filling an adhesive material in the through holes wherein the material of the spacer layer is adhesive and different from the adhesive material; and dicing the semiconductor wafer, the package substrate and the spacer layer along the scribe lines to form a plurality of chip packages separated from each other.

Abstract: A method for packaging micromachined devices fabricated by MEMS and semiconductor process is disclosed in this invention. The method employed etching technique to etch a trench surrounding the micromachined components on each chip of the first wafer down to the bottom interconnection metal layer. The said trench can accommodate the solder of flip-chip packaging. On each chip of the second wafer, or called as the second chip, a surrounding copper pillar wall corresponding to the trench on the first chip is deposited. By wafer-level packaging, the trench on the first chip is aligned to the pillar wall, and then bonded together with elevated temperature. The face-to-face chamber formed between two chips can allow the movement of the micromachined structures. Further, the signal or power connections between two chips can be established by providing several discrete pillar bumps.

Abstract: A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate is provided. The semiconductor substrate has first and second opposing sides and first and second portions. A tuning depression is formed on the second opposing side and the second portion of the semiconductor substrate. A radio frequency conductor is formed on the first opposing side of the first semiconductor substrate. The radio frequency conductor has a first end on the first portion of the first semiconductor substrate and a second end on the second portion of the first semiconductor substrate. A microelectronic die having an integrated circuit formed therein is attached to the first opposing side and the first portion of the semiconductor substrate such that the integrated circuit is electrically connected to the first end of the radio frequency conductor.

Abstract: The invention relates to a power module (10), preferably for a vehicle, in particular an electric vehicle, characterised in that said module includes two vertically adjacent semiconducting chips (12, 14), each chip having a first surface (20, 22) to be connected to a heat sink substrate (24, 26), and a second surface (28, 30) separate from the first and on which at least one electronic component (38a-44b) is arranged, the module being arranged such that the second surfaces of the chips are arranged opposite one another.

Abstract: An interposer includes a substrate, a conductive structure configured to contact the back side of a semiconductor device and contact pads. The interposer may include first and second sets of contact pads carried by the substrate. The interposer may also include conductive traces carried by the substrate to electrically connect corresponding contact pads of the first and second sets. The receptacles, which may be formed in a surface of the substrate and expose contacts of the second set, may be configured to at least partially receive conductive structures that are secured to the contact pads of the second set. Thus, the interposer may be useful in providing semiconductor device assemblies and packages of reduced height or profile. Such assemblies and packages are also described, as are multi-chip modules including such assemblies or packages.

Abstract: A conductive substrate structure includes a substrate unit, a conductive pad unit, and a conductive layer unit. The substrate unit has a top surface, a bottom surface, two opposite lateral surfaces, and a front surface. The conductive pad unit has at least two first conductive pads separated from each other and disposed on the top surface, and at least two second conductive pads separated from each other and disposed on the bottom surface. The conductive layer unit has at least two first conductive layers formed on the front surface and respectively electrically connected to two front sides of the two first conductive pads, and at least two second conductive layers respectively formed on the two opposite lateral surfaces and respectively electrically connected to two opposite lateral sides of the two second conductive pads. The two first conductive layers are respectively electrically connected with the two second conductive layers.

Abstract: Method and apparatus are provided for semiconductor device packages. In an example, an apparatus can include a first semiconductor device, a ground pad situated on an uppermost portion of the first semiconductor device and configured to electrically couple portions of the first semiconductor device to aground potential, and a second semiconductor device having at least a portion in electrical communication with an uppermost face of the first semiconductor device through a first electrically-conductive adhesive. In an example, the first electrically-conductive adhesive can be electrically coupled to the ground bond pad on the first semiconductor device.

Abstract: An integrated circuit package system comprising: providing a substrate having a cavity; sealing a package over the cavity of the substrate; and forming an encapsulant over the package and a portion of the substrate substantially preventing the encapsulant from forming in the cavity.