Abstract: A first conductive layer is formed. An insulating layer is formed so that at least a part of the insulating layer is disposed on the first conductive layer. A second conductive layer is formed so that at least a part of the second conductive layer is disposed on the insulating layer over the first conductive layer. Each of the first and second conductive layers is formed by discharging drops of a solvent containing fine particles of a conductive material. The insulating layer is formed by discharging drops of a solvent containing fine particles of an insulating material.

Abstract: A thin semiconductor device difficult to cause breakage of a semiconductor chip is disclosed.

Abstract: A storage apparatus 10 is disclosed, that comprises a wiring substrate 11 having a first surface and a second surface, a flat type external connection terminal 12a disposed on the first surface of the wiring substrate 11, a semiconductor device 14 disposed on the second surface of the wiring substrate 11 and having a connection terminal 14a connected to the flat type external connection terminal 12a, a molding resin 15 for coating the semiconductor device 14 on the second surface of the wiring substrate 11, a card type supporting frame 10a having a concave portion or a hole portion fitting the wiring substrate 11, the semiconductor device 14, and the molding resin 15 in such a manner that the flat type external connection terminal 12a is exposed to the first surface of the wiring substrate 11, and adhesive resin a adhering integrally the flat type external connection terminal 12a, the wiring substrate 11, the semiconductor device 14, the molding resin 15, and the card type supporting frame 10a.

Abstract: Microelectronic imagers with curved image sensors and methods for manufacturing curved image sensors. In one embodiment, a microelectronic imager device includes an imager die having a substrate, a curved microelectronic image sensor having a face with a convex and/or concave portion at one side of the substrate, and integrated circuitry in the substrate operatively coupled to the image sensor. The imager die can further include external contacts electrically coupled to the integrated circuitry and a cover over the curved image sensor.

Abstract: The flexible package (100) has between a first (1) and a second side (2) a semiconductor device (20) with a thinned back substrate (10) and an interconnect structure. Contact means (31,33) for external contact and a first resin layer (52) are present at the first side (2) of the package (100), which contact means (31,33) are coupled to the interconnect structure. At the second side (2) the semiconductor device (20) is at least substantially covered with a second resin layer (12). The contact means (31,33) are present on the first resin layer (52) and are coupled to the interconnect structure with redistribution tracks (32,34) extending through the first resin layer (52). A passivation layer (55) covers the first resin layer (52) and the redistribution tracks (32,34) at least substantially.

Abstract: A semiconductor device has a semiconductor substrate having first and second surface, a first resin film formed on the first surface of the semiconductor substrate and a second resin film formed on the second surface of the semiconductor substrate. A projection electrode or an interconnection is formed on the first surface of the semiconductor substrate, the second resin film is made of low elastic resin which is capable of absorbing an impact applied to the second surface of the semiconductor substrate and the second resin film is thinner than the semiconductor substrate.

Abstract: The present invention stacks packaged integrated circuits into modules that conserve PWB or other board surface area. The invention provides techniques and structures for aggregating chip scale-packaged integrated circuits (CSPs) or leaded packages with other CSPs or with monolithic or stacked leaded packages into modules that conserve PWB or other board surface area. The present invention can be used to advantage with packages of a variety of sizes and configurations ranging from larger packaged base elements having many dozens of contacts to smaller packages such as, for example, die-sized packages such as DSBGA. In a preferred embodiment devised in accordance with the present invention, a base element CSP and a support element CSP are aggregated through a flex circuit having at least two conductive layers that are patterned to selectively connect the two CSP elements.

Abstract: Disclosed are a semiconductor device, a method for manufacturing the same, and a method for mounting the same.

Abstract: A novel micro optical system as a platform technology for electrical and optical interconnections, thermal and mechanical assembly and integration of electronic, optoelectronic, passive and active components. This platform provides optical coupling and chip-to-chip interconnection by microwave electrical, optical guided and unguided waves, and power or bias electrical contacts or interfaces by a novel chip in flexible circuit, rigid or inflexible embodiments.

Abstract: An interface module for connecting LSI packages includes a connecting member which is to be mounted on an LSI package including an LSI chip and which includes lines to be electrically connected to the LSI package, an optoelectronic transducer which is mounted on the connecting member, which is connected to the lines of the connecting member, and which converts optical signal to electric signal or converts electric signal to optical signal, an optical waveguide which includes an optical input end and an optical output end, one of which is optically connected to the optoelectronic transducer, and a reinforcing film which is adhered to the optical waveguide, covering at least one side of the optical waveguide, and which is secured at one end to the connecting member.

Abstract: A semiconductor package, includes: element substrate having first surface, including: functional element on first surface, and extracting electrode on first surface and configured to output a signal of functional element, extracting electrode being disposed around functional element; rim substrate shaped into a frame, and configured to have first junction with element substrate to surround functional element, rim substrate including: first through hole through rim substrate, and connecting electrode which is: formed by packing first through hole with first conductor material, configured to seal signal extracting aperture of extracting electrode, and configured to electrically connect signal extracting aperture with takeout electrode; and cover substrate configured to have second junction with rim substrate to block aperture of rim substrate, cover substrate including: second through hole through cover substrate, and takeout electrode which is: formed by packing second through hole with second conductor materi

Abstract: A device comprises a first substrate, a second substrate and a compliant element. The compliant element is composed of a first, compliant material between the first substrate and the second substrate and has a side surface coated at least in part with a layer of a second material. The compliant element exhibits deformation consistent with the first substrate and a second side having been pressed together. In some embodiments, the second material is electrically conductive such that the compliant element provides a reliable electrical connection between the substrates. In other embodiments, the second material increases the hermeticity of the compliant element such that the compliant element provides a better hermetic seal between the substrates.

Abstract: A chip stack employing BGA or FBGA integrated circuit chip packages is provided. Two chip packages have bottom surfaces attached with sets of electrical contacts, which are oriented towards each other and are electrically connected to conductive patterns formed within the same flex substrate. One set contacts a conductive pattern on a top surface, the other set contacts a pattern on a bottom surface of the flex substrate within a same end portion. The other end portion has a conductive pattern, and is connected to a third set of electrical contacts. The flex substrate is wrapped around an edge of the chip package to connect the third set with the other two sets. Thereby, four chip packages are provided with this design, the layout of conductive traces formed within at least one of the flex substrates is meandered to compensate for length differences with respect to the other flex substrate.

Abstract: A package substrate includes signal pads provided on a main surface of the package substrate, footpads provided on a backside of the package substrate, and a sealing electrode provided on the main surface to surround the signal pads, the signal pads being electrically coupled to the footpads, the sealing electrode being insulated from the footpads.

Abstract: An organic electroluminescent device includes: first and second substrates facing each other and spaced apart from each other, the first and second substrates having a central portion and a peripheral portion; an array layer on the first substrate, the array layer including a thin film transistor; an organic electroluminescent diode on the second substrate; a connection pattern between the first and second substrates, the connection pattern electrically connecting the thin film transistor and the organic electroluminescent diode; and a seal pattern in the peripheral portion, the seal pattern including a metallic material for attaching the first and second substrates.

Abstract: A semiconductor device in the first embodiment includes: an electrode pad and a resin projection, formed on an active surface; a conductive film deposited from a surface of the electrode pad to a surface of the resin projection; a resin bump formed with the resin projection and with the conductive film. The semiconductor device is conductively connected to the opposing substrate through the resin bump electrode. The testing electrode is formed with the conductive film that is extended and applied to the opposite side of the electrode pad across the resin projection.

Abstract: The present invention describes a rewiring plate for components with connection grids of between approx. 100 nm and 10 ?m, which rewiring plate includes a base body and passages with carbon nanotubes, the lower end of the passages opening out into contact connection surfaces, and the carbon nanotubes forming an electrically conductive connection from the contact connection surfaces to the front surface of the base body.

Abstract: A electronic circuit device is provided with an electronic component provided with an electrode, a substrate having an upper surface on which the electronic component is mounted, external electrode that is formed near the electronic component mounted on the upper surface of the substrate and that is connected to the electrode, an insulating protrusion that is provided across the upper surface of the external electrode, and a sealing resin that seals the electronic component without covering the external electrode. The upper surface of the external electrode is partitioned by the protrusion into a first area that is located on the sealing resin side and a second area that is located the side opposite to the first area. The adherence of fine particles such as flakes of the sealing resin to the external electrode is suppressed, so that a stable electric connection between the external electrode and the electric equipment can be maintained.

Abstract: A connecting element for electrically connecting a semiconductor chip and a superordinate circuit board includes an elastic metal strip that is bent forming two metal limbs with flattened limb ends, thus forming a base between the metal limbs which is suitable for contacting and providing electrical connectivity to a plurality of contact pads of a superordinate circuit board. At least one of the two limb ends is electrically connected to the contact areas of a semiconductor chip, while the other limb end is elastically supported on the top side of the semiconductor chip, thereby enabling the connecting element to be self supporting.

Abstract: A chip size package semiconductor device can have reliable solder mounting and improved mounting reliability. A semiconductor device of one embodiment can include a semiconductor chip (1) mounted to a bottom portion (11) of a metal base (10A). A metal base (10A) can have side portions (12) with connection electrodes (15A) having a surface level higher than that of electrodes (7 and 8) on a surface of the semiconductor chip (1) by a difference (d). The connection electrode (15A) can be formed on a projecting piece (16) that is bent outward away from remaining portions of the side portion (12). The semiconductor device can be mounted face down without abutting the semiconductor chip (1) against a mounting substrate, thereby preventing mechanical damage to a semiconductor chip (1). At the same time, a solder layer can be formed in the gap between electrodes (7 and 8) and the mounting substrate, thereby raising the reliability of the soldering connection.

Abstract: A gate electrode (1a) is formed on the outer peripheral step portion (1?) of a semiconductor substrate (1) so as to face a pressure-contact supporting block (6), and a convex contacting portion (1g) is formed on a predetermined position on the surface of the gate electrode to contact the pressure contact supporting block. The surface area of the gate electrode ranging from the inner periphery to a position adjacent to the convex contacting portion, is coated with an insulation film (1d). The convex contacting portion (1g) is formed of a convex portion integral with the gate electrode or formed of another gate electrode (1a?).

Abstract: In a composite device of the laminate type having a laminate structure of a composite ceramic layer and a dielectric ceramic layer, the composite ceramic layer including a layer portion having the same composition as the dielectric ceramic layer and a plurality of particle portions formed on the surface of the layer portion. The particle portions are made from magnetic ceramic material. This prevents the ceramic layers of the device from cracking and separating when fired.

Abstract: A multi-chip press-connected type semiconductor device comprises: a plurality of active element chips to control an electric current flowing in one direction; a plurality of diode chips that transmit the current in a direction opposite to the current transmitting direction of said active element chip; and electrode plates for said active element chip and for said diode chip, said electrode plates pressing from above and under with said plurality of active element chips and said plurality of diode chips being interposed therebetween; wherein said diode chips are disposed in all of outermost peripheral chip positions with no-existence of other chips adjacent to at least one side of a chip in a chip disposing region, and are disposed in internal layout positions surrounded with the outermost peripheral chip positions, and said diode chips to be disposed in the internal layout positions are arranged in order of a total number of other chips from the smallest that exist adjacently to at least one of a side and a v

Abstract: A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages.

Abstract: The present invention provides a semiconductor device having a structure that can be mounted on a wiring substrate, as for the semiconductor device formed over a thin film-thickness substrate, a film-shaped substrate, or a sheet-like substrate. In addition, the present invention provides a method for manufacturing a semiconductor device that is capable of raising a reliability of mounting on a wiring substrate. One feature of the present invention is to bond a semiconductor element formed on a substrate having isolation to a member that a conductive film is formed via a medium having an anisotropic conductivity.

Abstract: A semiconductor package having a substrate mounted die. The die configured having active circuit components and a top surface having bond pads electrically connected with circuitry of the die. The bond pads commonly being formed above active circuit components. The bond pads being electrically interconnected with wire bonds to establish intra-chip electrical connection between circuitry of the die. Methods of forming such packages are also disclosed.

Abstract: Structures and techniques for mounting semiconductor dies are disclosed. In one embodiment, the invention includes a stack of printed wiring board assemblies that are connected via interconnection components. At least one of the printed wiring board assemblies includes an interposer substrate having a constraining layer that includes carbon.

Abstract: Dielectric rings are configured to be disposed around contact pads on a surface of a semiconductor device or another substrate. The rings may be fabricated or otherwise disposed around the contact pads of a semiconductor device or other substrate before or after conductive structures, such as solder balls, are secured to the contact pads. Upon connecting the semiconductor device face-down to a higher level substrate and establishing electrical communication between contact pads of the semiconductor device and contacts pads of the substrate, the rings prevent the material of solder balls protruding from the semiconductor device from contacting regions of the surface of the semiconductor device that surround the contact pads thereof. The rings may be preformed structures or fabricated on the surface of the semiconductor device or other substrate. For example, stereolithographic techniques may be used to form the rings.

Abstract: A semiconductor stacking structure has a semiconductor device. A flexible substrate is coupled to a bottom surface of the semiconductor device. The flexible substrate is folded over on at least two sides to form flap portions. The flap portions are coupled to an upper surface of the first semiconductor device and covers only a portion of the upper surface of the semiconductor device.

Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.

Abstract: A semiconductor chip includes a semiconductor substrate including first and second surfaces and a plurality of side surfaces, the first and second surfaces being parallel to each other and facing in opposite directions, the side surfaces connecting peripheries of the first and second surfaces. At least one of the side surfaces is an inclined surface with respect to the first and second surfaces, and a groove is formed in the inclined surface. The groove extends in a direction which intersects a plane parallel to the first and second surfaces and extends in a direction which intersects a plane which intersects the first and second surfaces at right angles.

Abstract: A compression assembled semiconductor package for housing a power semiconductor die which includes two major pole pieces in intimate electrical contact with respective major electrodes of a power semiconductor die. The package includes a plastic molded insulation ring disposed around the power semiconductor die. The pole pieces are secured to respective ends of the plastic molded insulation ring. One of the pole pieces may include an annular flange that penetrates the plastic molded insulation ring from an interior wall thereof and is embedded in its body. The annular flange preferably comprises a projection having a squared tab and circular distal end that is received by a receiving groove having a notch (to receive the squared tab) and a cavity (to receive the distal end).

Abstract: A submember for electrical device is disclosed. Said submember is mounted on a chip of electrical device. An embodiment for the submember comprised of an insulator and a plurality of conductive elements, wherein the conductive elements embedded in the insulator and a portion of conductive element exposed to the insulator for electrical connection, then (i). the reliability of submember is enhanced; (ii). the material of insulator enables to be saved; and (iii). the thickness of submember is thinner and the heat dissipation of chip enhanced; moreover, a portion of the conductive element may be protruding the insulator for avoiding a short-circuited problem of conductive wire, moreover, the conductive element may be staircase-shaped, then, not only the reliability of submember is enhanced, but the short circuit problem of conductive wire is also avoided; the conductive element may further include an extending portion, furthermore, the conductive element may be placed in a cavity as required.

Abstract: A rectification chip terminal structure for soldering a rectification chip on a terminal filled with a packaging material to form a secured mounting for the rectification chip is to be inserted in a coupling bore of a circuit board. The structure includes a conductive element which has a buffer portion and a base seat to prevent bending and deformation under external forces, and has a stress buffer zone to prevent the chip from being damaged and moisture from entering. It can be installed easily in the coupling bore of the circuit board and hold the packaging material securely without breaking away.

Abstract: Provided are a flexible film package module and a method of manufacturing the same that can be adapted for manufacture at lower cost and/or to adapt the characteristics of the flexible film package module for specific applications. The lower-cost flexible film package module includes a tape film that combines both a first insulating substrate, typically formed from a higher-cost polyimide material, and a second insulating substrate, typically formed from an insulating material or materials that are less expensive and/or provide modified performance when compared with the first insulating material. Both the first and second substrates will include complementary circuit patterns that will be electrically and physically connected to allow the composite substrate to function as a unitary substrate. The first and second substrates will also include connection regions that may be adapted for connection to printed circuit boards and/or electronic devices such as liquid crystal displays.

Abstract: Various embodiments of an interposer for mounting a semiconductor die, as well as methods for forming the interposer, are disclosed. The interposer includes flexible solder pad elements that are formed from a core material of the interposer, such that the interposer may absorb thermally induced stresses and conform to warped or uneven surfaces. Embodiments of electronic device packages including a semiconductor die mounted to and electrically connected to the interposer, as well as methods for forming the electronic device packages, are also disclosed. In one electronic device package, the semiconductor die is electrically connected to the interposer with wire bonds attached to a routing layer of the interposer. In another electronic device package, the semiconductor die is electrically connected to the interposer by bonding the semiconductor die to the flexible solder pad elements of the interposer in a flip-chip configuration.

Abstract: In an electronic device comprising a first electrodes consisting of a metal oxide and a second electrode consisting of an aluminum alloy film directly contacted and electrically connected to the first electrode, the contact interface between the aluminum alloy film and the first electrode is constructed so that at least a part of alloy components constituting the aluminum alloy film exist as a precipitate or concentrated layer. This construction enables direct contact between the aluminum alloy film and the electrode consisting of a metallic oxide and allows elimination of a barrier metal in such an electronic device, and manufacturing technology therefor.

Abstract: A wired circuit board can control characteristic impedance at connection points between wires of a suspension board with circuit and terminal portions of the wired circuit board connected thereto with a simple structure, to improve signal transmission efficiency even for fine pitch wiring or for high frequency signals. The wired circuit board includes a relay flexible wiring circuit board formed by a first wired circuit board including a first metal substrate, a first insulating base layer, a first conductor layer and a first insulating cover layer which is substantially identical in layer structure with the suspension board with circuit and a second wired circuit board connected with the first wired circuit board for connecting with a control circuit board. Since the suspension board with circuit and the first wired circuit board are rendered substantially identical in layer structure, both characteristic impedances at these connection points can be matched.

Abstract: A lead-bond type chip package includes a multilayer substrate for supporting and electrical interconnecting a semiconductor chip. The multilayer substrate has a slot defined therein. The multilayer substrate comprises an interlayer circuit board having prepregs disposed thereon, a plurality of leads on the prepreg on the upper surface of the interlayer circuit board, and a plurality of solder pads for making external electrical connection on the prepreg on the lower surface of the interlayer circuit board. The leads of the multilayer substrate are bonded to corresponding bonding pads formed on the semiconductor chip. A package body is formed on the multilayer substrate around the semiconductor chip and in the slot of the multilayer substrate. The multilayer substrate is capable of providing a power or ground plane formed therein for enhancing the electrical performance of the package, and providing a high wiring density for packaging a chip with high I/O connections.

Abstract: In a packaged integrated circuit, electrostatic discharge protection is provided by portions of a lead frame on which the integrated circuit is mounted. The lead frame includes a die paddle on which an integrated circuit die is mounted, with plastic or epoxy material encapsulating exposed surfaces of the integrated circuit die except for a sensing surface, and supporting pins or leads formed from the lead frame. Portions of the lead frame extending from the die paddle are folded around sides of the encapsulated integrated circuit die and over, or adjacent to and level with, a peripheral upper surface of the encapsulated integrated circuit die to form an electrostatic discharge ring. The lead frame portions folded around the integrated circuit package are connected to ground through a ground pin, so that charge on a human finger touching the electrostatic discharge ring is dissipated to ground before the finger contacts a sensing surface of the integrated circuit.

Abstract: A semiconductor device comprises a semi-conductor chip bonded on a top surface inside a case electrode by a bonding material and a lead electrode bonded on a top surface of the semiconductor chip by a bonding material with a space of the case electrode filled with an insulating material for sealing the bonded sections, wherein a groove is provided on a top surface of the case electrode from an edge of the semiconductor chip, to thereby reduce heat distortion which is generated on a large scale at an end of the bonding material on account of a difference in coefficients of linear thermal expansion between the semiconductor chip and the case electrode and improve the thermal fatigue life.

Abstract: A semiconductor device includes semiconductor chips, a first conductive pattern, an external terminal and an encapsulating resin. Each of the semiconductor chips has a front side formed with integrated circuits and a back side. The semiconductor chips are stacked each other. The first conductive pattern electrically connects the integrated circuits. The external terminal is electrically connected to the first conductive pattern. The encapsulating resin encapsulates the semiconductor chips and the first conductive pattern.

Abstract: Disclosed is a rectifier diode device. The rectifier diode device includes a conductive base, a semiconductor chip, a conductive lead and insulation resin. A trench and a post are formed in the conductive base in order to increase a bonding surface between the conductive base and the insulating resin and to lengthen a humidity transfer path for the semiconductor chip. Due to the trench and the post, the bonding surface between the conductive base and the insulating resin increases and the humidity transfer path for the semiconductor chip lengthens, thereby improving heat emission performance of the rectifier diode device. A plurality of prismatic protrusions is formed at an outer peripheral wall of the conductive wire so that coupling force between the conductive wire and an external device is improved. A protrusion ring is provided at a lower surface of the conductive wire so that stress applied to the semiconductor chip is minimized when the rectifier diode device is press-fitted into the external device.

Abstract: Disclosed is a substrate for semiconductor package and a wire bonding method using thereof. The substrate is provided with at least one reference mark on its surface to check a loading position and a shift state of a solder mask. The reference mark is composed of a combination of a reference pattern and a solder mask opening and is positioned in any location on an outer peripheral edge of a die attachment region. The reference mark may take various shapes. A method for checking a solder mask shift using the reference mark includes comparing a design value of the reference pattern and the solder mask opening with the reference pattern and the solder mask opening, which are formed in an actual material. After the solder mask shift is calculated, a wire bonding coordinate is newly constructed in consideration of the solder mask shift. This minimizes the wire bonding error.

Abstract: A semiconductor device comprising a substrate. An interconnect pattern is formed over the substrate, and the substrate has a first portion and a second portion to be superposed on the first portion. The first portion has edges as positioning references. The second portion has a shape to be superposed over the first portion except the edges.

Abstract: A rectification chip terminal structure for soldering a rectification chip encased in a glass passivated pallet (GPP) on a terminal filled with a packaging material to form a secured mounting for the rectification chip is to be inserted in a coupling bore of a circuit board. The structure includes a conductive element which has a buffer portion and a base seat to prevent the GPP from fracturing when the packaging material is heated and expanded or prevent the conductive element from bending and deforming under external forces, and has a stress buffer zone to prevent the chip from being damaged and moisture from entering. It can prevent the GPP from fracturing when the packaging material is heated and expanded and be installed easily in the coupling bore of the circuit board and hold the packaging material securely without breaking away.

Abstract: A power device includes a semiconductor die having an upper surface and a lower surface. One or more terminals are coupled to the die. A first substrate is bonded to the upper surface of the die. The first substrate is configured to provide a first heat dissipation path. A second substrate is bonded to the lower surface of the die. The second substrate is configured to provide a second heat dissipation path.

Abstract: A spherical shaped semiconductor device has a protective insulating film thereon and input/output connection openings that are located along a intersected portion on the protective insulating film where a plane face running through a center of the spherical shaped semiconductor device intersects the protective insulating film. More input/output connection openings are provided on the spherical shaped semiconductor device compared with a conventional square semiconductor device. The spherical shaped semiconductor device is connected to a flat circuit substrate through a flexible printed wiring substrate. A lower portion of the flexible printed wiring substrate is cut into divided sections for connecting input/output terminals of the flat circuit substrate. Connection between the spherical shaped semiconductor device and the flat circuit substrate does not cause any cracks or disconnection due to flexibility of the flexible printed wiring substrate.

Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.

Abstract: A gate electrode (1a) is formed on the outer peripheral step portion (1?) of a semiconductor substrate (1) so as to face a pressure-contact supporting block (6), and a convex contacting portion (1g) is formed on a predetermined position on the surface of the gate electrode to contact the pressure contact supporting block. The surface area of the gate electrode ranging from the inner periphery to a position adjacent to the convex contacting portion, is coated with an insulation film (1d). The convex contacting portion (1g) is formed of a convex portion integral with the gate electrode or formed of another gate electrode (1a?).