Abstract: A method of applying a fluorescent material to a surface includes providing a substrate, providing a semiconductor light-emitting stack on the substrate, bonding the substrate to the semiconductor light-emitting stack, and overlaying top and side surfaces of the semiconductor light-emitting stack with the fluorescent material, wherein the fluorescent material contains no binding material.

Abstract: An integrated circuit system, and a method of manufacture thereof, includes an integrated circuit package connected to a package interconnect connectible to an external resistor, wherein the integrated circuit package includes a master integrated circuit and a slave integrated circuit, the master integrated circuit is connectible to the external resistor and the slave integrated circuit, the master integrated circuit includes a master constant current and a slave constant current, the master constant current flows through the external resistor, and the slave constant current is based on the master constant current.

Abstract: A radio front end includes a duplexer, a tunable balancing network, a detector module, and a processing module. The duplexer is operably coupled to an antenna and is operable to provide electrical isolation between an outbound wireless signal and an inbound wireless signal. The tunable balancing network is operably coupled to the duplexer and operable to establish an impedance that substantially matches an impedance of the antenna based on a tuning signal. The detector module is operable to generate an error signal based on an electrical performance characteristic of the duplexer. The processing module is operable to generate the tuning signal based on the error signal.

Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a bottom structure including a heating electrode, data storage materials, each of the data storage materials formed on the bottom structure in a confined structure perpendicular to the bottom structure, and having a lower diameter smaller than an upper diameter, an upper electrode formed on each of the data storage materials, and an insulation unit formed between adjacent data storage materials.

Abstract: The various technologies presented herein relate to a three dimensional manufacturing technique for application with semiconductor technologies. A membrane layer can be formed over a cavity. An opening can be formed in the membrane such that the membrane can act as a mask layer to the underlying wall surfaces and bottom surface of the cavity. A beam to facilitate an operation comprising any of implantation, etching or deposition can be directed through the opening onto the underlying surface, with the opening acting as a mask to control the area of the underlying surfaces on which any of implantation occurs, material is removed, and/or material is deposited. The membrane can be removed, a new membrane placed over the cavity and a new opening formed to facilitate another implantation, etching, or deposition operation. By changing the direction of the beam different wall/bottom surfaces can be utilized to form a plurality of structures.

Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.

Abstract: A monolithic integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate.

Abstract: An organic light-emitting diode display device includes a substrate, a display unit on the substrate, a touch unit facing the substrate, and a sealing portion surrounding the display unit. The sealing portion couples the substrate to the touch unit and includes glass frit. The touch unit includes an encapsulation substrate, a first conductive layer on the encapsulation substrate, an insulating layer on a portion of the first conductive layer and the encapsulation substrate, and a second conductive layer on the first conductive layer and the insulating layer. The insulating layer of the touch unit includes an organosilicon compound and has a thermal decomposition temperature of about 360° C. or more.

Abstract: A monolithic three dimensional memory array is provided that includes a first memory level formed above a substrate, and a second memory level monolithically formed above the first memory level. The first memory level includes a first plurality of substantially parallel, substantially coplanar conductors extending in a first direction, a second plurality of substantially parallel, substantially coplanar conductors extending in a second direction, the second direction different from the first direction, the second conductors above the first conductors, and a first plurality of devices. Each of the first plurality of devices is disposed between one of the first conductors and one of the second conductors, and includes a resistivity-switching binary metal oxide or nitride compound and a silicon, germanium, or silicon-germanium alloy resistor of a single conductivity type. Numerous other aspects are provided.

Abstract: A method of growing an epitaxial silicon layer is provided. The method comprising providing a substrate including an oxygen-terminated silicon surface and forming a first hydrogen-terminated silicon surface on the oxygen-terminated silicon surface. Additionally, the method includes forming a second hydrogen-terminated silicon surface on the first hydrogen-terminated silicon surface through atomic-layer deposition (ALD) epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. The second hydrogen-terminated silicon surface is capable of being added one or more layer of silicon through ALD epitaxy from SiH4 thermal cracking radical assisted by Ar flow and flash lamp annealing continuously. In one embodiment, the method is applied for making devices with thin-film transistor (TFT) floating gate memory cell structures which is capable for three-dimensional integration.

Abstract: A miniaturized, low power RF transmitter with a dual mode active on-chip antenna/inductor is disclosed in which antenna also serves as the oscillator inductor. Also disclosed is a miniaturized low power RF receiver with an on-chip antenna; and a RF transmitter system wherein an on-chip antenna is wirelessly coupled to an off chip patch antenna are disclosed. Advantageously, the TX chip is housed in a low loss, e.g. Low Temperature Co-fired Ceramic (LTCC) package with a patch antenna to provide a System-on-Package implementation comprising electromagnetic coupling between a RF TX chip comprising an integrated on-chip antenna and a package antenna.

Abstract: An electronic device (100), the electronic device (100) comprises a substrate (101), a first electrode (102) formed at least partially on the substrate (101), a second electrode (103) formed at least partially on the substrate (101), a convertible structure (104) connected between the first electrode (102) and the second electrode (103), and a spacer element (105) connected between the first electrode (102) and the second electrode (103) and adapted for spacing the convertible structure (104) with regard to a surface of the substrate (101).

Abstract: The present disclosure provides systems and methods for configuring and constructing a single photo detector or array of photo detectors with all fabrications circuitry on a single side of the device. Both the anode and the cathode contacts of the diode are placed on a single side, while a layer of laser treated semiconductor is placed on the opposite side for enhanced cost-effectiveness, photon detection, and fill factor.

Abstract: Nitrogen-doped MgO insulating layers exhibit voltage controlled resistance states, e.g., a high resistance and a low resistance state. Patterned nano-devices on the 100 nm scale show highly reproducible switching characteristics. The voltage levels at which such devices are switched between the two resistance levels can be systematically lowered by increasing the nitrogen concentration. Similarly, the resistance of the high resistance state can be varied by varying the nitrogen concentration, and decreases by orders of magnitude by varying the nitrogen concentrations by a few percent. On the other hand, the resistance of the low resistance state is nearly insensitive to the nitrogen doping level. The resistance of single Mg50O50-xNx layer devices can be varied over a wide range by limiting the current that can be passed during the SET process. Associated data storage devices can be constructed.

Abstract: An optical device comprising an anode, a cathode, an organic semiconducting material between the anode and the cathode, and an electron transport layer between the cathode and the organic semiconducting material wherein the organic semiconducting material comprises sulfur and the electron transport layer containing barium.

Abstract: Provided is a phase-change memory device including a phase-change material pattern of which strips are shared by neighboring cells. The phase-change memory device includes a plurality of bottom electrodes arranged in a matrix array. The phase-change material pattern is formed on the bottom electrodes, and the strips of the phase-change material pattern are electrically connected to the bottom electrodes. Each strip of the phase-change material pattern is connected to at least two diagonally neighboring bottom electrodes of the bottom electrodes.

Abstract: A method for fabricating a 3-D monolithic memory device. Silicon-oxynitride (SixOyNz) on amorphous carbon is used an effective, easily removable hard mask with high selectivity to silicon, oxide, and tungsten. A silicon-oxynitride layer is etched using a photoresist layer, and the resulting etched SixOyNz layer is used to etch an amorphous carbon layer. Silicon, oxide, and/or tungsten layers are etched using the amorphous carbon layer. In one implementation, conductive rails of the 3-D monolithic memory device are formed by etching an oxide layer such as silicon dioxide (SiO2) using the patterned amorphous carbon layer as a hard mask. Memory cell diodes are formed as pillars in polysilicon between the conductive rails by etching a polysilicon layer using another patterned amorphous carbon layer as a hard mask. Additional levels of conductive rails and memory cell diodes are formed similarly to build the 3-D monolithic memory device.

Abstract: A memory cell device includes a first electrode, phase-change material adjacent the first electrode, a second electrode adjacent the phase-change material, a diffusion barrier adjacent the phase-change material, and isolation material adjacent the diffusion barrier for thermally isolating the phase-change material. The diffusion barrier prevents diffusion of the phase-change material into the isolation material.

Abstract: An electronic packaging system includes an electronic device. The electronic packaging system also includes a flexible material located adjacent a plurality of sides of the electronic device. The electronic device is located in a cavity in the flexible material. The flexible material has a first height and a first width. The electronic device has a second height. The first height is greater than the second height and the first width is greater than the first height so the flexible material protects the electronic device from loading.

Abstract: A device includes: a first electrical contact; a second electrical contact; a semiconducting or semimetallic organic layer disposed at least partially between the first and second electrical contacts; and a tunneling barrier layer disposed at least partially between the semiconducting or semimetallic organic layer and the first electrical contact. The tunneling barrier layer has a thickness effective to enable flow of an electrical current through the tunneling barrier layer responsive to an operative electrical bias applied across the first and second electrical contacts, the electrical current exhibiting negative differential resistance for at least some applied electrical bias values. Circuits are also disclosed that utilize one or more negative differential resistance polymer diodes to implement logic, memory, or mixed signal applications.

Abstract: A bi-directional power switch is formed as a monolithic semiconductor device. The power switch has two MOSFETs formed with separate source contacts to the external package and a common drain. The MOSFETs have first and second channel regions formed over a well region above a substrate. A first source is formed in the first channel. A first metal makes electrical contact to the first source. A first gate region is formed over the first channel. A second source region is formed in the second channel. A second metal makes electrical contact to the second source. A second gate region is formed over the second channel. A common drain region is disposed between the first and second gate regions. A local oxidation on silicon region and field implant are formed over the common drain region. The metal contacts are formed in the same plane as a single metal layer.

Abstract: Provided are magnetic tunnel junction structures having bended tips at both ends thereof, magnetic RAM cells employing the same and photo masks used in formation thereof. The magnetic tunnel junction structures have a pinned layer pattern, a tunneling insulation layer pattern and a free layer pattern, which are stacked on an integrated circuit substrate. At least the free layer pattern has a main body as well as first and second bended tips each protruded from both ends of the main body when viewed from a plan view.

Abstract: A hybrid wafer comprises a single-crystal SixGe1-x layer (15), where 0?x?1, a high thermal conductivity layer (10), and between the single-crystal SixGe1-x layer (15) and the high thermal conductivity layer (10), an intermediate layer (21) having a thickness of between 1 nanometer and 1 micrometer and comprising at least one amorphous or polycrystalline SixGe1-x layer (21a), where 0?x?1.

Abstract: There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.

Abstract: A method for forming a capacitor includes forming a dielectric layer over a substrate. A conductive layer is formed over the dielectric layer. Dopants are implanted through at least one of the dielectric layer and the conductive layer after forming the dielectric layer so as to form a conductive region under the dielectric layer, wherein the conductive layer is a top electrode of the capacitor and the conductive region is a bottom electrode of the capacitor.

Abstract: A multilevel phase change memory may be formed of a chalcogenide material formed between a pair of spaced electrodes. The cross-sectional area of the chalcogenide material may decrease as the material extends from one electrode to another. As a result, the current density decreases from one electrode to the other. This means that a higher current is necessary to convert the material that has the largest cross-sectional area. As a result, different current levels may be utilized to convert different amounts of the chalcogenide material to the amorphous or reset state. A distinguishable resistance may be associated with each of those different amounts of amorphous material, providing the opportunity to engineer a number of different current selectable programmable states.

Abstract: The invention relates to a layered construction for a Gunn diode. The layered construction comprises a series of stacked layers consisting of a first highly doped nd GaAs layer (3), a graded AlGaAs layer (5), which is placed upon the first highly doped layer (3), whereby the aluminum concentration of this layer, starting from the boundary surface to the first nd GaAs layer (3), decreases toward the opposite boundary surface of the AlGaAs layer (5), and of a second highly doped n+ layer (7). An undoped intermediate layer (4, 6) serving as a diffusion or segregation stop layer is placed on at least one boundary surface of the AlGaAs layer (5) to one of the highly doped layers (3, 7) and prevents an unwanted doping of the graded layer.

Abstract: There is provided a monolithic three dimensional TFT mask ROM array. The array includes a plurality of device levels. Each of the plurality of device levels contains a first set of enabled TFTs and a second set of partially or totally disabled TFTs.

Abstract: A method of forming a semiconductor device includes the following steps: providing a plurality of semiconductor layers; providing means for coupling signals to and/or from layers of the device; providing a quantum well disposed between adjacent layers of the device; and providing a layer of quantum dots disposed in one of the adjacent layers, and spaced from the quantum well, whereby carriers can tunnel in either direction between the quantum well and the quantum dots.

Abstract: Briefly, in accordance with an embodiment of the invention, a phase change memory and a method to manufacture a phase change memory is provided. The phase change memory may include a memory material and a first tapered contact adjacent to the memory material. The phase change memory may further include a second tapered contact separated from the first tapered contact and adjacent to the memory material, wherein the first and second tapered contacts are adapted to provide a signal to the memory material.

Abstract: A structure (and method) for a piezoelectric device, including a layer of piezoelectric material. A nanotube structure is mounted such that a change of shape of the piezoelectric material causes a change in a stress in the nanotube structure.

Abstract: A monolithic transceiver integrated circuit that includes a substrate, a transmitter subsystem of one or more subcircuits on the substrate, and a receiver subsystem of one or more subcircuits on the substrate. Also included is a bias current supply coupled to the receiver and transmitter subsystems to provide bias current. The bias current supply includes a first bias circuit on the substrate coupled to, and to supply bias current to, a first subcircuit of the transmitter subsystem. The first bias circuit includes a first current modulator having a first switch input to indicate that the bias current is to start or stop being supplied to the first subcircuit. The first current modulator is to control the rate of change of supplied bias current in response to the first switch input. The first subcircuit may be a power amplifier. The control of the rate of change reduces oscillator pull in at least one oscillator included in the integrated circuit.

Abstract: A semiconductor chip includes a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: Ultra-high-density data-storage media employing indium chalcogenide, gallium chalcogenide, and indium-gallium chalcogenide films to form bit-storage regions that act as photoconductive, photovoltaic, or photoluminescent semiconductor devices that produce electrical signals when exposed to electromagnetic radiation, or to form bit-storage regions that act as cathodoconductive, cathodovoltaic, or cathodoluminescent semiconductor devices that produce electrical signals when exposed to electron beams. Two values of a bit are represented by two solid phases of the data-storage medium, a crystalline phase and an amorphous phase, with transition between the two phases effected by heating the bit storage region.

Abstract: An integrated programmable conductor memory cell and diode device in an integrated circuit comprises a diode and a glass electrolyte element, the glass electrolyte element having metal ions mixed or dissolved therein and being able to selectively form a conductive pathway under the influence of an applied voltage. In one embodiment, both the diode and the memory cell comprise a chalcogenide glass, such as germanium selenide (e.g., Ge2Se8 or Ge25Se75). The first diode element comprises a chalcogenide glass layer having a first conductivity type, the second diode element comprises a chalcogenide glass layer doped with an element such as bismuth and having a second conductivity type opposite to the first conductivity type and the memory cell comprises a chalcogenide glass element with silver ions therein. In another embodiment, the diode comprises silicon and there is a diffusion barrier layer between the diode and the chalcogenide glass memory element.

Abstract: A liquid crystal driver IC comprising: a power circuit; an electric volume for varying an output voltage from the power circuit; a temperature detector; and a correction table for storing an electric volume control value corresponding to a temperature detected by the temperature detector. The power circuit includes: a first power circuit having a first temperature-voltage characteristic; a second power circuit having a second temperature-voltage characteristic; and a temperature gradient selection circuit for outputting a voltage conforming with a desired temperature gradient characteristic based on output voltages from the first and second power circuits. The temperature detector detects an actual temperature based on the first and second temperature-voltage characteristics.

Abstract: A method of forming a semiconductor on insulator structure in a monolithic semiconducting substrate with a bulk semiconductor structure. A first portion of a surface of the monolithic semiconducting substrate is recessed without effecting a second portion of the surface of the monolithic semiconducting substrate. An insulator precursor species is implanted beneath the surface of the recessed first portion of the monolithic semiconducting substrate, and a trench is etched around the implanted and recessed first portion of the monolithic semiconducting substrate. The insulator precursor species is activated to form an insulator layer beneath the surface of the recessed first portion of the monolithic semiconducting substrate. The semiconductor on insulator structure is formed in the first portion of the monolithic semiconducting substrate, and the bulk semiconductor structure is formed in the second portion of the monolithic semiconducting substrate.

Abstract: A semiconductor wafer includes a plurality of passive device units, which are electrically connected across scribe lines. Passive device chips in the wafer that are adjacent to one another in a first direction are electrically connected in parallel, while passive device units adjacent to one another in a second direction are connected in series. By selecting a number of adjacent passive device units extending in the first and second direction, and separating the selected units from the wafer along the corresponding scribe lines, a passive device chip having a desired electrical characteristic (e.g., capacitance or resistance) can be obtained. Such passive device chips may be assembled in a semiconductor package where they are electrically connected to active devices.

Abstract: An AlxGa1−xAs/GaAs/AlxGa1−xAs quantum well exhibiting a bound-to-quasibound intersubband absorptive transition is described. The bound-to-quasibound transition exists when the first excited state has the same energy as the “top” (i.e., the upper-most energy barrier) of the quantum well. The energy barrier for thermionic emission is thus equal to the energy required for intersubband absorption. Increasing the energy barrier in this way reduces dark current. The amount of photocurrent generated by the quantum well is maintained at a high level.

Abstract: There is disclosed a semiconductor light emitting element formed by selective growth and being high in light emitting efficiency, in which at least one GaN-based layer grown by ELO is stacked/formed on a sapphire substrate, and a fluorescent substance for converting an ultraviolet light to a visible light is contained in a selective growth mask material layer for use in this case. Since this fluorescent substance converts the ultraviolet light to the visible light, a binding efficiency of the ultraviolet light to the fluorescent substance is enhanced in either one of a center light emitting type and UV light emitting type of light emitting elements. By further containing the fluorescent substance into a passivation film, the efficiency is further enhanced.

Abstract: The invention concerns a sealing valve which comprises a valve body (1) on which a sealing cylinder (8) is mounted. The sealing cylinder (8) contains a sealing stopper against which a pressure piston (18) abuts. A lever arm (23), which is loaded in terms of force by a spring component (31), presses on the pressure piston (18). The valve can be used within the scope of the interventional catheter technique for sealing a guide catheter. Advantageously it can be sensitively and topically actuated with one hand in an ergonomic manner.

Abstract: A microwave system encapsulated by two layers. The first layer is an arylcyclobutene polymer having a thickness greater than the tallest component of the system and only located in predetermined areas. Overlaying the polymer and other preselected areas of the system is a ceramic glass material. These two layers are applied in two layers coating process steps.

Abstract: This invention is a three layer Si.sub.x Ge.sub.1-x structure formed on a silicon substrate in which a thin, lightly doped Si.sub.x Ge.sub.1-x layer is formed between two heavily doped Si.sub.x Ge.sub.1-x layers. The incorporation of at least 10% germanium in the silicon provides for intervalley scattering of carriers in the conduction band of the Si.sub.x Ge.sub.1-x layers. This intervalley scattering leads to the negative differential conductance necessary for transferred electron device (TED) operation. Additionally, the lightly doped Si.sub.x Ge.sub.1-x layer is made very thin, on the order of 2,000 to 7,000 Angstroms, and the current flow through the this layer is vertical so that a high electric field can be placed across the lightly doped layer without applying a high voltage across the lightly doped layer. The lightly doped layer can be made thin even though it is interposed between two heavily doped layers because the growth of the in-situ doped Si.sub.x Ge.sub.