Abstract: A semiconductor device includes an insulating substrate including a substrate, a metal pattern formed on an upper surface of the substrate, and a metal film formed on a lower surface of the substrate, a semiconductor element fixed on the metal pattern, a case surrounding the metal pattern and having a contact portion maintained in contact with the upper surface of the substrate, and an adhesive with which the case and a portion of the upper surface of the substrate outside a portion maintained in contact with the contact portion are bonded together, wherein a plurality of through holes are formed in a peripheral portion of the case, the through holes extending vertically through the case, and wherein the metal film exists in at least part of a place right below the contact portion.

Abstract: A semiconductor package may be provided. A semiconductor package may include a substrate. The semiconductor package may include a first semiconductor chip and a second semiconductor chip which are disposed adjacent to each other over a first surface of the substrate. The semiconductor package may include first bonding wires which electrically couple the first semiconductor chip and the substrate. The semiconductor package may include an insulation adhesive which is interposed between the second semiconductor chip and the substrate. The first bonding wires may be disposed to pass through the insulation adhesive and electrically couple the first semiconductor chip and the substrate.

Abstract: A semiconductor module including an insulated circuit substrate having a substrate, a circuit layer on a front surface of the substrate, and a metal layer on a back surface of the substrate; a semiconductor element electrically connected to the circuit layer; a cooling unit having a ceiling board bonded to the metal layer, a bottom board opposite the ceiling board, a side wall connecting a periphery of the ceiling board and a periphery of the bottom board, and a fin connecting the ceiling board and bottom board, where thickness of the ceiling board is at least 0.5 mm and at most 2.0 mm and total thickness of the ceiling board and bottom board is at least 3 mm and at most 6 mm; and a solder layer that bonds together the metal layer and the ceiling board by melting at a temperature of at least 200° C. and at most 350° C.

Abstract: An electrical device comprising a ribbed molded body housing an electrical component is provided. The ribbed molded body includes at least one surface or portion having a plurality of ribs along at least a portion of the surface. The electrical component may be a passive or active electrical component. The electrical component may be connected to a lead frame and molded into the ribbed molded body.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.

Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a substrate, a conductive through via, a dielectric layer, and a conductive layer. The substrate has a first surface and a second surface opposite to each other. The conductive through via is disposed in the substrate and extended from the first surface beyond the second surface. The dielectric layer is disposed on the substrate, wherein the dielectric layer has an opening exposing a portion of the conductive through via. The top surface of the conductive through via protrudes from the bottom surface of the opening. The conductive layer is disposed in the opening and connected to the conductive through via.

Abstract: A semiconductor packaging structure includes a copper heat-sink with a shim projection which provides a stress release structure. The heat-sink with the shim projection may be used in conjunction with a pedestal in order to further reduce the thermal stress produced from the mismatch of thermal properties between the copper heat-sink metal and the ceramic frame. The copper heat-sink with a shim projection may also be part of the semiconductor package along with a lead frame, the ceramic frame, a semiconductor device, a capacitor, a wire bond and a ceramic lid or an encapsulation. The copper heat-sink, the ceramic frame and the lead frame are all chosen to be cost effective, and chosen such that the packaging process for the semiconductor device is able to achieve a smaller size while maintaining high reliability, low cost, and suitability for volume manufacturing.

Abstract: A light emitting device includes: a substrate; one or more LED (light emitting diode) elements mounted on a substrate; and a radiator unit made of metal paste and arranged on a rear surface opposite to a principal surface on which the one or more LED elements are mounted. The height Ta of the radiator unit from a rear surface is less than thickness Tb of substrate.

Abstract: A semiconductor package includes an interposer, a semiconductor element installed on a first surface of the interposer, bumps formed on a second surface of the interposer, and a chip component installed on the second surface of the interposer. The interposer is a silicon interposer; the semiconductor element is flip-chip mounted on the first surface of the interposer; the chip component is a thin film passive element formed by carrying out a thin film process on a silicon substrate, and a pad being formed on one surface of the thin film passive element; and the pad of the chip component is connected to a land formed on the second surface of the interposer using a conductive bonding material. According to this structure, the reliability of a bond between the interposer and the chip component of the semiconductor package can be ensured while achieving a small size.

Abstract: An interconnect for electrically coupling pads formed on adjacent chips or on packaging material adjacent the chips, with an electrically conductive heat sink being disposed between the pads, the interconnect comprising a metallic membrane layer disposed between two adjacent pads and disposed or bridging over the electrically conductive heat sink so as to avoid making electrical contact with the electrically conductive heat sink. An electroplated metallic layer is disposed on the metallic membrane layer. Fabrication of interconnect permits multiple interconnects to be formed in parallel using fabrication techniques compatible with wafer level fabrication of the interconnects. The interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.

Abstract: According to various embodiments, a chip carrier may include: a chip supporting region configured to support a chip; a chip contacting region including at least one contact pad for electrically contacting the chip; wherein the chip carrier is thinned in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a die structure formed over the substrate. The semiconductor device structure also includes a lid structure formed over the die structure. The lid structure includes a top portion with a top length and a bottom portion with a bottom length, and the top length is greater than the bottom length. The semiconductor device structure also includes a package layer formed between the lid structure and the die structure, and a sidewall of the bottom portion of the lid structure is not aligned with a sidewall of the die structure.

Abstract: Methods and apparatus are described for heat management in an integrated circuit (IC) package using a device with a textured surface having multiple grooves in an otherwise relatively flat surface. The textured surface of the heat management device is designed, in conjunction with a thermal interface material (TIM), to push gas bubbles out of the flat areas such that the gas bubbles are trapped in the grooves or driven out of the interface between the device and the TIM altogether. The area of the grooves is small relative to the ungrooved areas (i.e., the flat areas), such that when the gas bubbles are trapped in the grooved areas, the ungrooved areas work even better for heat transfer. With the area of the regions for the flat portions being substantially greater than the area of the regions for the grooves, the textured heat management device is designed to lower thermal resistance, increase thermal conductivity, and increase heat transfer from one or more IC dies to a heat sink assembly in an IC package.

Abstract: A fan-out wafer level chip package structure and the manufacturing method thereof are provided. The method includes the steps of providing a supporting plate having a removable tape formed on the supporting plate, placing a plurality of chips on the removable tape, applying an adhesive layer on a back surface of each of the chips, providing a conductive cover for covering all chips and isolating the chips from each other by a plurality of partitions, injecting a molding compound into an inside of the conductive cover and curing the molding compound for forming an encapsulation, separating the encapsulation from the supporting plate, forming a connection layer on an active surface of each of the chips to establish electrical connections, and performing a cutting process to divide the encapsulation into a plurality of the package structures.

Abstract: An electronic device includes at least one chip and an insulating body embedding the chip. The electronic device further includes a heat-sink in contact with the chip. The heat-sink includes a plate having a first thickness. A recess is provided in the plate that defines a central portion of the plate having a second thickness less than the first thickness. The chip is mounted to the central region of the heat-sink within the recess. The insulating body includes a surface, such as a mounting surface, including an opening exposing at least a portion of the heat-sink. The device may further include a reophore extending through a side surface of the insulating body, that reophore being in contact with the heat sink.

Abstract: A power module assembly includes opposing end caps collectively having coolant ports and a row of cards that each have a major side defining a projection extending across the card. A side panel extends between the end caps such that the panel and row define a channel in fluid communication with the ports and configured to convey coolant directly across the cards. The side panel defines a groove that receives the projections.

Abstract: A light emitting device with improved safety in which leaking laser beam from a slit is converted into a visible light. A light emitting device includes a laser light source part and optical member that defines a slit. The optical member is disposed with the slit oriented on an optical path of the laser beam, while disposing a wavelength converting member on an inner wall defining the slit to convert a wavelength of the laser beam into a long-wavelength side visible light.

Abstract: An onboard electronic device includes: an element that generates heat; a member that is provided between the element and a coolant cooling the element, and differs in thermal expansion coefficient from the element; an element temperature sensor that detects the temperature of the element; a coolant temperature sensor that detects the temperature of the coolant; and a controller that controls operation of the element such that the temperature of the element allowed when the temperature of the coolant is a first temperature is lower than the temperature of the element allowed when the temperature of the coolant is a second temperature that is higher than the first temperature.

Abstract: A power conversion device is capable of achieving three requirements to restrict a surge voltage, ensure high radiation performance of SW elements, and restrict ringing at the same time. In a power conversion device, element modules of two SW elements are stacked in a thickness direction via an insulating layer in such a manner that lateral surfaces are aligned parallel to each other in a same orientation, and a positive terminal of one SW element and a negative terminal of the other SW element are disposed so as to overlap each other in the thickness direction.

Abstract: An apparatus including a die including a first side and an opposite second side including a device side with contact points; and a build-up carrier including at least one layer of conductive material disposed on a first side of the die, and a plurality of alternating layers of conductive material and dielectric material disposed on the second side of the die, wherein the at least one layer of conductive material on the first side of the die is coupled to at least one of (1) at least one of the alternating layers of conductive material on the second side of the die and (2) at least one of the contact points of the die. A method including forming a first portion of a build-up carrier adjacent one side of a die, and forming a second portion of the build-up carrier adjacent another side of the die.

Abstract: A semiconductor device with improved heat radiation characteristics. It includes: a wiring board having a chip mounting surface and a plurality of electrode pads formed over the chip mounting surface; a semiconductor chip located over the chip mounting surface of the wiring board, having a plurality of bonding pads; a plurality of wires for coupling the electrode pads and the bonding pads; a heat slug located over the semiconductor chip; and a sealing member covering the chip mounting surface of the wiring board, the semiconductor chip, the wires, and the heat slug. A spacer lies between the chip mounting surface of the wiring board and the semiconductor chip and the sealing member lies between the semiconductor chip and the heat slug.

Abstract: A cooling device includes a mounting surface, a cooling fin on a rear surface side of the mounting surface, and a cooling passage for cooling the cooling fin with a liquid refrigerant. The refrigerant flows from a flow inlet to the cooling passage and discharges from a discharge outlet. The cooling passage comprises a first surface provided with the cooling fin, a second surface opposing the first surface, and a wall portion between the first surface and the second surface, and is longer than a channel connecting the flow inlet and the discharge outlet. The wall portion has a first wall portion extending from the second surface to the first surface, and a second wall portion extending in parallel with the first wall portion from the first surface to a height exceeding a top portion of the first wall.

Abstract: Power modules and power module arrays are disclosed. In one embodiment, a power module includes a module support, a high temperature module, and a module cap. The module support includes a frame member, a heat spreader, a first electrically conductive rail, and a second electrically conductive rail. The high temperature module includes a module substrate, a semiconductor device thermally and/or electrically coupled to a semiconductor surface of the module substrate, a first external connector, and a second external connector. The first and second electrically conductive rails are disposed within a through-hole of the first and second external connectors, respectively. The module cap includes a body portion, a plurality of posts, a first opening, and a second opening. The plurality of posts presses against at least the first external connector, the second external connector, and the module substrate such that the high temperature module is thermally coupled to the heat spreader.

Abstract: A power module has a copper layer composed of copper or a copper alloy on a surface of a circuit layer to which a semiconductor device is bonded, and a solder layer that is formed by using a solder material is formed between the circuit layer and the semiconductor device. An average crystal grain size which is measured by EBSD measurement in a region having a thickness of up to 30 ?m from the surface of the circuit layer in the solder layer is 10 ?m or less, the solder layer has a composition that contains Sn as a main component, 0.01 to 1.0% by mass of Ni, and 0.1 to 5.0% by mass of Cu, and a thermal resistance increase rate when a power cycle is loaded 100,000 times is less than 10% in a power cycle test.

Abstract: A common connecting section for connection to terminals at the same potential in circuits is placed outside a mold section to allow a reduction in size of a semiconductor module 1. Since the common connecting section is a portion of a lead frame which would be placed within such a mold section in a conventional semiconductor module, the mold section can be reduced in size as compared with the conventional one, thereby reducing the amount of mold resin and the material cost.

Abstract: An inertial force sensor that can suppress fluctuation of detection sensitivity even if an external stress is applied to the inertial force sensor. Angular velocity sensor (1), that is, an inertial force sensor includes ceramic substrate (6), lower lid (4) adhering to ceramic substrate (6) with adhesives (11a and 11b) (first adhesives), and sensor element (2) adhering to lower lid (4) with adhesives (10a and 10b) (second adhesives). The elastic moduli of adhesives (11a and 11b) are smaller than those of adhesives (10a and 10b).

Abstract: MEMS packages and modules are described. In an embodiment, a module includes a package mounted within an opening in a module board. The package includes a flexible wiring board mounted to a back surface of the module board and spanning across the opening in the module board. A die is mounted on the flexible wiring board and is encapsulated within an overmold. An air gap exists laterally between the overmold and side surface of the opening in the module board.

Abstract: A semiconductor device may include a multi-layer interconnect board having in stacked relation a lower conductive layer, a dielectric layer, and an upper conductive layer. The dielectric layer may have a recess formed with a bottom and sloping sidewall extending upwardly from the bottom. The upper conductive layer may include upper conductive traces extending across the sloping sidewall, and the lower conductive layer may include lower conductive traces. The semiconductor device may include vias extending between the lower and upper conductive layers, an IC carried by the multi-layer interconnect board in the recess, bond wires coupling upper conductive traces to the IC, and encapsulation material adjacent the IC and adjacent portions of the multi-layer interconnect board.

Abstract: A semiconductor device including power TSVs for stably supplying a power source is described. A semiconductor device includes a chip power pad placed in a first region of a chip, power through silicon vias (TSVs) connected to the chip power pad and placed in the second region of each of the chips, and metal lines configured to couple the chip power pad and the power TSVs.

Abstract: Embodiments of the subject application provide for a circuit comprising: a lead frame having a first plurality of exposed terminals, the lead frame defining a plane; a laminate substrate in the plane defined by the lead frame, adjacent to the lead frame, and electrically coupled to the lead frame, the laminate substrate having a first surface including a second plurality of exposed terminals and a second surface opposite the first surface; a first one or more dies mounted on the lead frame and electrically coupled to the lead frame; and a second one or more dies mounted on the second surface of the laminate substrate and electrically coupled to the laminate substrate.

Abstract: A semiconductor device includes a semiconductor chip which can be a heat-generating semiconductor chip or a semiconductor relay substrate in which an integrated circuit or wiring is built in. A sintered-silver-coated film is adhered on a surface layer part of the semiconductor substrate, interposed by a silicon oxide film. A heat-dissipating fin (heat sink), which may be copper or aluminum, is bonded on the sintered-silver-coated film, interposed by an adhesive layer.

Abstract: A module arrangement for power semiconductor devices, including one or more power semiconductor modules, wherein the one or more power semiconductor modules include a substrate with a first surface and a second surface being arranged opposite to the first surface, wherein the substrate is at least partially electrically insulating, wherein a conductive structure is arranged at the first surface of the substrate, wherein at least one power semiconductor device is arranged on the conductive structure and electrically connected thereto, wherein the one or more modules includes an inner volume for receiving the at least one power semiconductor device which volume is hermetically sealed from its surrounding by a module enclosure, wherein the module arrangement includes an arrangement enclosure at least partly defining a volume for receiving the one or more modules, and wherein the arrangement enclosure seals covers the volume.

Abstract: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.

Abstract: A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip.

Abstract: A method of and device for forming vias on an electronic board (such as a PCB board) comprises forming one or more holes on the electronic board, placing a nanomaterial inside the one or more holes, and forming one or more filled holes on the electronic board. The nanomaterial can be nanocopper, which can be either push/pull into the holes on the electronic board or a combination of push and pull. The push/pull can be performed by using a mechanical device or by a person. A capping layer can be on both side of the via. The vias formed by using the nanomaterials provides a high efficient vertical heat transferring path from one side of the electronic board to the other side of the electronic board.

Abstract: A microelectronic assembly including a dielectric region, a plurality of electrically conductive elements, an encapsulant, and a microelectronic element are provided. The encapsulant may have a coefficient of thermal expansion (CTE) no greater than twice a CTE associated with at least one of the dielectric region or the microelectronic element.

Abstract: A method for determining an area of a region for receiving a heat sink on a surface of a chip-supporting substrate is disclosed. The method can include determining, in response to a specified voltage drop associated with substrate wiring, a first set of wiring cross-sectional areas and corresponding lengths that satisfy the specified voltage drop. The method can also include determining, by selecting, in response to a specified thermal resistance associated with substrate wiring and insulating layers, from the first set, a second set of wiring cross-sectional areas and corresponding lengths that satisfy the specified thermal resistance. The method can also include selecting, from a set of placement areas corresponding to the second set of wiring cross-sectional areas and corresponding lengths, a heat sink placement area that is greater than a lower size for a placement area and less than an upper size for a placement area.

Abstract: A voltage regulator device for a rotary electrical machine, notably an alternator and/or alternator-starter of a motor vehicle. The regulator device (14) comprises one or more electronic components (28) able to contribute to controlling the electric machine, a heat sink (30) having parallel heat-dissipating vanes (32). The heat sink is in a heat-exchange relationship with the component or components, and a support (34) on which the heat sink is positioned. The support is able to be mounted on the electric machine in such a way that the vanes of the heat sink can orient an air flow towards a region of depression provided between the support and the machine. A bearing of an electric machine is equipped with such a device and to an electric machine equipped with such a bearing.

Abstract: A semiconductor package for mounting to a printed circuit board (PCB) includes a semiconductor die in a ceramic case, a conductive base coupled to the semiconductor die at a top surface of the conductive base, where the conductive base includes a first layer having a first coefficient of thermal expansion (CTE), and a second layer having at least one mounting tab and a second CTE. The conductive base is configured to reduce thermal stress in the ceramic case, where the first CTE is equal to or slightly different than a CTE of the ceramic case, the second CTE is greater than the first CTE, and a CTE of the PCB is greater than or equal to the second CTE. The conductive base is configured to electrically couple a power electrode of the semiconductor die to the PCB.

Abstract: An integrated circuit package may include an integrated circuit die with lower and upper surfaces. The integrated circuit die is mounted on a package substrate. An underfill material is deposited between the integrated circuit die and the package substrate. A molding compound may be injected to surround the integrated circuit die while leaving the upper surface of the integrated circuit die exposed. The integrated circuit package further includes a metal layer that contacts the exposed upper surface of the integrated circuit die. The metal layer may also cover the molding compound. If desired, an additional metal layer may be formed on the layer of metal as a heat spreader. Such a configuration may also be applicable for wire bond packages, in which the metal layers are formed on an overmold that is disposed over a wire-bonded integrated circuit die on a package substrate.

Abstract: A mounting carrier for semiconductor chips includes a second main surface provided for mounting of semiconductor chips, and a first main surface opposite to the second main surface. The mounting carrier also includes a mounting body, wherein the mounting body includes a first metallization on the side facing the first main surface and the first main surface includes a structure having a plurality of columnar structural elements.

Abstract: Provided is a radiant heat circuit board for mounting a plurality of heat generating devices. The radiant heat circuit board includes a metal plate including an integrated metal projection to which the plurality of heat generating devices are attached, an insulation layer exposing the integrated metal projection, the insulation layer being disposed on the metal plate, and a plurality of electrode pads disposed on the insulation layer, the plurality of electrode pads applying a voltage into each of the heat generating devices. Thus, a radiant projection may be disposed between the heat generating devices to improve heat radiation.

Abstract: A method of manufacturing a semiconductor device and a semiconductor device that is manufactured by the method. In the method of manufacturing a semiconductor device, a releasing sheet is disposed in close contact with a hole of an aluminum plate having the recessed hole, and a skeleton structure of a semiconductor device is put into the recessed hole. Then, liquid epoxy resin is poured into the recessed hole. After hardening, the epoxy resin body 10 including the skeleton structure is taken out from the recessed hole to complete manufacturing the semiconductor device. Using a simple molding jig including the aluminum plate, and covering the skeleton structure with the epoxy resin body, a highly reliable semiconductor device with a case-less construction can be manufactured.

Abstract: The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.

Abstract: A semiconductor device (10) includes a metallic base plate (22) provided with an upper surface (22a) and a lower surface (22b), a plurality of insulating substrates (24) provided on the upper surface (22a), and a plurality of semiconductor elements (26) and (28) mounted side by side on the respective insulating substrates (24). Annular grooves (50) and (52) for storing insulating grease are provided on the lower surface (22b) of the base plate (22). A surface (40a) of a cooling fin (40) is superimposed on the lower surface (22b) with insulating grease (42) interposed therebetween and insides of the annular grooves (50) and (52) are filled with the insulating grease (42).

Abstract: A method includes recording a wafer ID and a location ID of a device die in a database, and bonding the device die over a package substrate, wherein the device die and the package substrate are disposed in a package. A package ID is on the package. A mapping is established to link the wafer ID and the location ID of the device die to the package ID.

Abstract: A semiconductor device with plated pillars and leads is disclosed and may include a semiconductor die comprising a conductive pillar, a conductive lead electrically coupled to the conductive pillar, a metal plating layer covering the conductive lead and conductive pillar, and an encapsulant material encapsulating the semiconductor die and at least a portion of the plating layer. The pillar, lead, and plating layer may comprise copper, for example. The plating layer may fill a gap between the pillar and the lead. A portion of the metal plating layer may, for example, comprise an external lead. The metal plating layer may cover a side surface of the pillar and a top surface, side surface, and at least a portion of a bottom surface of the lead. The metal plating layer may cover side and bottom surfaces of the pillar and top, side, and at least a portion of bottom surfaces of the conductive lead.

Abstract: An integrated LED module at least comprises: a light-transmitting plate having a heat-conducting substrate and a transparent package; an LED array sealed in the light-transmitting plate; a drive circuit electrically connected to the LED array, and used for converting an external power supply into a 12V-75V forward voltage that drives each LED in the LED array; and a heat sink clinging to the light-transmitting plate. The integrated LED module solves the problem in the prior art that an LED lamp presented after assembly has a large size and is heavy as a part of the line of a drive power supply in the LED lamp is complicated, and further reduces material costs, saves processing and assembling time, and lowers production costs due to an integrally formed structure.

Abstract: A package on package semiconductor structure includes a first package positioned above a first surface of a substrate, a second package positioned above the first package, and a first thermal element positioned between the first package and the second package, wherein the first thermal element is separated from the second package by an air gap and the thermal element provides a heat path for heat generated by the first package.

Abstract: A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer.