For High Frequency (e.g., Microwave) Device Patents (Class 257/728)
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Patent number: 9673117Abstract: A semiconductor module includes a plurality of insulating circuit boards including semiconductor chips, each of the plurality of insulating circuit boards including a first outer edge among outer edges of the insulating circuit board facing an adjacent insulating circuit board of the plurality of insulating circuit boards, and a second outer edge among the outer edges excluding the first outer edge; a resin frame body having a crosspiece abutting against the first outer edges, and a frame element abutting against the second outer edges; a conductive component striding over the crosspiece to electrically connect the insulating circuit boards to each other; and an upper lid having a lid element covering an opening disposed at an upper part of the resin frame body and a partition protruding from a face of the lid element facing the insulating circuit boards to abut against a part of the crosspiece.Type: GrantFiled: January 7, 2016Date of Patent: June 6, 2017Assignee: FUJI ELECTRIC CO., LTD.Inventors: Rikihiro Maruyama, Takahito Harada
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Patent number: 9633951Abstract: A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.Type: GrantFiled: November 10, 2006Date of Patent: April 25, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Mark Pavier, Andrew N. Sawle, Martin Standing
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Patent number: 9583811Abstract: A microwave device includes a semiconductor package comprising a microwave semiconductor chip and a waveguide part associated with the semiconductor package. The waveguide part is configured to transfer a microwave waveguide signal. It includes one or more pieces. The microwave device further includes a transformer element configured to transform a microwave signal from the microwave semiconductor chip into the microwave waveguide signal or to transform the microwave waveguide signal into a microwave signal for the microwave semiconductor chip.Type: GrantFiled: August 7, 2014Date of Patent: February 28, 2017Assignee: Infineon Technologies AGInventors: Ernst Seler, Maciej Wojnowski, Walter Hartner, Josef Boeck
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Patent number: 9577308Abstract: An interconnecting structure for electrically connecting a first electronic device with a second electronic device is provided. The first electronic device has two first bond-pads, and the second electronic device has two second bond-pads electrically connected to the two first bond-pads respectively. The interconnecting structure includes a signal transmission structure electrically connected to the two first bond-pads and the two second bond-pads; and a ground device disposed between the first electronic device and the second electronic device so that the first electronic device and the second electronic device have a same ground potential.Type: GrantFiled: March 11, 2014Date of Patent: February 21, 2017Assignee: NATIONAL CHAIO TUNG UNIVERSITYInventors: Chun-Hsing Li, Chien-Nan Kuo, Chun-Lin Ko
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Patent number: 9544057Abstract: The present invention relates to an interconnect structure for coupling at least one electronic unit for outputting and/or receiving electric signals, and at least one optical unit for converting said electric signals into optical signals and/or vice versa, to a further electronic component. The interconnect structure comprises an electrically insulating substrate (102) and a plurality of signal lead pairs (104, 120) to be coupled between said electronic unit (108, 116) and a front end contact region (106) for electrically contacting said interconnect structure by said further electronic component.Type: GrantFiled: September 17, 2013Date of Patent: January 10, 2017Assignee: FINISAR CORPORATIONInventors: Andrei Kaikkonen, Lennart Lundquist, Lars-Goete Svensson, Robert Smith
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Patent number: 9520373Abstract: Provided is a semiconductor package including a semiconductor chip having one surface on which chip pads are formed, and a redistribution structure formed on the one surface of the semiconductor chip. The redistribution structure includes a redistribution layer connected to the chip pads and a redistribution insulating layer interposed between the semiconductor chip and the redistribution layer. The redistribution insulating layer includes a first insulating portion having a first dielectric constant and a second insulating portion having a second dielectric constant that is different from the first dielectric constant. The first insulating portion and the second insulating portion are connected to each other in a horizontal direction.Type: GrantFiled: December 22, 2015Date of Patent: December 13, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-hoon Kim, Keung-beum Kim
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Patent number: 9455157Abstract: A packaged IC has a package with a die paddle, a signal lead, and a ground lead. The packaged IC also has a die, secured to the package, with a ground pad and a signal pad. The signal pad is electrically connected to the signal lead, and the ground pad is electrically connected to both the die paddle and the ground lead.Type: GrantFiled: September 4, 2015Date of Patent: September 27, 2016Assignee: Anokiwave, Inc.Inventors: Vipul Jain, Noyan Kinayman, Amir Esmaili, Guarav Menon, Nitin Jain
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Patent number: 9412687Abstract: A wiring substrate includes a first wiring layer including a first wiring part having a first wiring interval and a second wiring part having a second wiring interval wider than the first wiring interval, a metal plane layer formed on a portion of a first insulation layer formed on the first wiring layer, the first wiring part being located below the portion, a second insulation layer formed on the first insulation layer and the metal plane layer and having a first via hole and a second via hole, a second wiring layer formed on the second insulation layer and connected to the first wiring layer via a first via conductor formed in the first via hole, and a third wiring layer formed on the second insulation layer and connected to the metal plane layer via a second via conductor formed in the second via hole.Type: GrantFiled: June 9, 2015Date of Patent: August 9, 2016Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Yuji Kunimoto, Jun Furuichi, Noriyoshi Shimizu, Naoyuki Koizumi
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Patent number: 9406582Abstract: A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness, in order to reduce or minimize wafer warpage. In some embodiments, the wafer, having a plurality of chips (e.g., silicon), is thinned (e.g., by chemical-mechanical polishing) before deposition of the copper layer, to reduce the thermal resistance of the chip. Some embodiments further deposit copper in a pattern of bumps, raised areas, or pads, e.g., in a checkerboard pattern, to thicken and add copper while reducing or minimizing wafer warpage and chip stress.Type: GrantFiled: July 24, 2008Date of Patent: August 2, 2016Assignee: Intel CorporationInventors: Fay Hua, Gregory M. Chrysler, James G. Maveety, Kramadhati V. Ravi
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Patent number: 9368457Abstract: A high-frequency package includes an MMIC including a signal source and a conductor pattern that is connected to the signal source, a substrate having a signal line and a GND formed thereon and the MMIC mounted thereon, a metal bump for signaling that is formed between the MMIC and the substrate, and connects the conductor pattern of the MMIC and the signal line of the substrate, and a plurality of metal bumps for shielding that are formed between the MMIC and the substrate so as to surround the signal source and the conductor pattern with the metal bump for signaling, where a space between a pair of adjacent metal bumps among the metal bump for signaling and the plurality of metal bumps for shielding is equal to or less than half of a wavelength of an electromagnetic wave generated from the signal source.Type: GrantFiled: February 28, 2013Date of Patent: June 14, 2016Assignee: Mitsubishi Electric CorporationInventor: Kosuke Yasooka
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Patent number: 9351395Abstract: A method of manufacturing a printed circuit board includes the steps of providing a first layer stack including a first electrically-conductive layer and a first electrically-insulating layer and providing a second layer stack including a second electrically-insulating layer. The first electrically-conductive layer is disposed on the first surface of the first electrically-insulating layer. The second electrically-insulating layer includes one or more electrically-conductive traces disposed on a first surface thereof. The method also includes mounting a device on the first surface of the second electrically-insulating layer such that the device is electrically-coupled to at least one of the one or more electrically-conductive traces, and providing the first layer stack with a cut-out area defining a void that extends from the second surface of the first electrically-insulating layer to the first surface of the first electrically-conductive layer.Type: GrantFiled: January 18, 2012Date of Patent: May 24, 2016Assignee: Covidien LPInventors: Wayne L. Moul, Robert J. Behnke, II, Scott E. M. Frushour, Jeffrey L. Jensen
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Patent number: 9349612Abstract: A lead frame includes a plurality of unit lead frames arranged in a matrix. Leads of adjacent ones of the unit lead frames are connected via a connecting bar, in which a longitudinal connecting bar and a transverse connecting bar are crossed at a crossing part. The lead frame further includes a dicing part including the connecting bar and a part of the leads, to be cut along a dicing line, a half-etching part formed along the dicing part, and being smaller in width than the dicing part, and a strength retention part formed in the half-etching part and extended from the crossing part of the connecting bar at least to an end lead located closest to the crossing part among the leads of the unit lead frame adjacent to the crossing part.Type: GrantFiled: January 2, 2014Date of Patent: May 24, 2016Assignee: MITSUI HIGH-TEC, INC.Inventor: Takahiro Ishibashi
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Patent number: 9293439Abstract: An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.Type: GrantFiled: December 11, 2014Date of Patent: March 22, 2016Assignee: GLOBALFOUNDRIES Inc.Inventors: Edmund Blackshear, Elaine Cyr, Benjamin Vito Fasano, Paul Francis Fortier, Marcus E. Interrante, Roger Lam, Shidong Li, Thomas Edward Lombardi, Hilton T. Toy, Thomas Weiss
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Patent number: 9252767Abstract: An integrated RF switch module including a package customized to include at least one trace. The trace includes one or more of at least one connection pad and at least one landing pad. At least one switching die is connected to the at least one connection pad. At least one device is connected to the at least one landing pad, the at least one device configured to enhance the performance of the switching die.Type: GrantFiled: June 28, 2011Date of Patent: February 2, 2016Assignee: HITTITE MICROWAVE CORPORATIONInventors: Kasim Ayyildiz, Michael Clark, Peter Katzin
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Patent number: 9177881Abstract: Certain embodiments provide a high-frequency semiconductor package including: a base which is made of metal and is a grounding portion; a multi-layer wiring resin substrate; a first internal conductor film; and a lid. The multi-layer wiring resin substrate is provided on a top surface of the base, and has a frame shape in which a first cavity from which the top surface of the base is exposed is formed. The first internal conductor film covers surfaces which form a top surface of the multi-layer wiring resin substrate and an inner wall surface of the first cavity, and is electrically connected with the base. The lid is attached onto the multi-layer wiring resin substrate, and seals and covers the first cavity.Type: GrantFiled: December 2, 2013Date of Patent: November 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiyuki Ikuma, Masatoshi Suzuki
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Patent number: 9142620Abstract: The present disclosure provides a power device and power device packaging. Generally, the power device of the present disclosure includes a die backside and a die frontside. A semi-insulating substrate with epitaxial layers disposed thereon is sandwiched between the die backside and the die frontside. Pads on the die frontside are coupled to the die backside with patterned backmetals that are disposed within vias that pass through the semi-insulating substrate and epitaxial layers from the die backside to the die frontside.Type: GrantFiled: June 5, 2013Date of Patent: September 22, 2015Assignee: RF Micro Devices, Inc.Inventors: Andrew P. Ritenour, Paul Partyka
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Patent number: 9142429Abstract: A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.Type: GrantFiled: June 23, 2014Date of Patent: September 22, 2015Assignee: RAYTHEON COMPANYInventors: Premjeet Chahal, Francis J. Morris
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Patent number: 9084342Abstract: A manufacturing method of a circuit board is provided. Providing a substrate, where a first laser resistant structure is disposed on a first dielectric layer and at the periphery of a pre-removing area, a second dielectric layer covers the first laser resistant structure, a circuit layer is disposed on the second dielectric layer, a second laser resistant structure is disposed on the second dielectric layer and at the periphery of the pre-removing area, a third dielectric layer covers the circuit layer and the second laser resistant structure. There are gaps between the second laser resistant structure and the circuit layer, and the vertical projection of the gaps on the first dielectric layer overlaps the first laser resistant structure. A laser machining process is performed to etch the third dielectric layer at the periphery of the pre-removing area. The portion of the third dielectric layer within the pre-removing area is removed.Type: GrantFiled: March 18, 2013Date of Patent: July 14, 2015Assignee: Unimicron Technology Corp.Inventor: Chen-Chuan Chang
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Patent number: 9070961Abstract: Shielding of high-frequency circuits is achieved using a simple and inexpensive configuration not using any lid. A high-frequency circuit mounting substrate (20) is disposed, on an underside surface layer of which are disposed high-frequency circuits (21 and 22) and is formed a first grounding conductor that has same electric potential as grounding conductors of the high-frequency circuits and that surrounds the high-frequency circuits. A mother control substrate (3) is disposed, on which the high-frequency circuit mounting substrate (20) is mounted in such a way that the high-frequency circuits are sandwiched therebetween and on which a second grounding conductor is formed in a region facing the high-frequency circuits. Plural first lands are formed on the first grounding conductor of the high-frequency circuit mounting substrate (20) to surround the high-frequency circuits.Type: GrantFiled: September 2, 2009Date of Patent: June 30, 2015Assignee: Mitsubishi Electric CorporationInventor: Takuya Suzuki
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Patent number: 9059083Abstract: A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.Type: GrantFiled: September 14, 2007Date of Patent: June 16, 2015Assignee: Infineon Technologies AGInventors: Henrik Ewe, Joachim Mahler, Manfred Mengel, Reimund Engl, Josef Hoeglauer, Jochen Dangelmaier
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Patent number: 9041169Abstract: A semiconductor packaging container allowing to use in millimeter band is provided at a low cost. The inner SIG pads and the inner GND pads, capable of a direct connection with a signal terminal of a semiconductor chip 10 are provided on the bottomed cylindrical dielectric case formed of the liquid crystal polymer. Further, the external SIG pads integrally formed with the inner SIG pads 201, 202 and the external GND pad 303 integrally formed with the inner GND pad are provided on the back of the bottom surface of the dielectric case as the external terminal. The inner GND pads and are to form the coplanar waveguide with the inner SIG pads and. Also, the inner GND pads and are to add capacitive reactance for canceling the inductance caused by the space at the semiconductor chip portion to the coplanar waveguide.Type: GrantFiled: May 27, 2014Date of Patent: May 26, 2015Assignee: YOKOWO CO., LTD.Inventors: Shoichi Koshikawa, Junichiro Nikaido, Shintaro Takase, Yoshio Aoki
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Patent number: 9035194Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.Type: GrantFiled: October 30, 2012Date of Patent: May 19, 2015Assignee: Intel CorporationInventors: M D Altaf Hossain, Jin Zhao, John T. Vu
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Patent number: 9000583Abstract: A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.Type: GrantFiled: September 30, 2013Date of Patent: April 7, 2015Assignee: Tessera, Inc.Inventors: Belgacem Haba, Wael Zohni, Richard Dewitt Crisp
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Patent number: 8987878Abstract: A substrate-less composite power semiconductor device may include a thin substrate and a top metal layer located on a top surface of the substrate. A total thickness of the substrate and the epitaxial layer may be less than 25 microns. Solder bumps are formed on top of the top metal layer and molding compound surrounds the solder bumps and leaves the solder bumps at least partly exposed.Type: GrantFiled: October 29, 2010Date of Patent: March 24, 2015Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Tao Feng, Zhiqiang Niu, Yuping Gong, Ruisheng Wu, Ping Huang, Lei Shi, Yueh-Se Ho
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Patent number: 8987061Abstract: Methods for antenna switch modules are disclosed. In certain implementations, a method of making an antenna switch module is provided. The method includes providing a package substrate implemented to receive one or more electrical components, attaching a silicon on insulator (SOI) die to the package substrate, and providing an integrated filter. The SOI die includes a capacitor and a switch coupled to a plurality of radio frequency (RF) signal paths. The integrated filter filters an RF signal received on a first RF signal path of the plurality of RF signal paths, and includes the capacitor of the SOI die and an inductor.Type: GrantFiled: June 19, 2014Date of Patent: March 24, 2015Assignee: Skyworks Soultions, Inc.Inventors: Jong-Hoon Lee, Chuming Shih
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Patent number: 8981881Abstract: A stacked module includes a first multilayer substrate including an opening having a stepwise wall face, and a first transmission line including a first grounding conductor layer, a second multilayer substrate supported on a stepped portion of the stepwise wall face and including a second transmission line including a second grounding conductor layer, a first chip mounted on a bottom of the opening and coupled to a third transmission line provided on the first multilayer substrate, and a second chip mounted on the front face of the second multilayer substrate and coupled to the second transmission line. A face to which the second grounding conductor layer or a fourth grounding conductor layer coupled thereto is exposed is joined to the stepped portion to which the first grounding conductor layer or a third grounding conductor layer coupled thereto is exposed, and the first and second grounding conductor layers are coupled.Type: GrantFiled: January 15, 2013Date of Patent: March 17, 2015Assignee: Fujitsu LimitedInventor: Satoshi Masuda
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Patent number: 8969132Abstract: Disclosed and claimed herein is a microwave assembly having a substrate comprising a microwave device; said device having a die, a first layer having a dielectric constant between about 1.00 and about 1.45 and a thickness between about 0.05 and about 2 mm along with one or more layers chosen from an absorbing layer, an EMI blocking layer, a layer comprising conductive material or a metal cover.Type: GrantFiled: September 20, 2011Date of Patent: March 3, 2015Assignee: Nuvotronics, LLCInventors: David William Sherrer, James MacDonald
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Patent number: 8964400Abstract: A circuitry arrangement includes several electronic parts mounted to a circuit board, at least one conductor section extending between the electronic parts within a first conductor layer, and a closed conductor loop comprising at least one loop section running in parallel to the at least one conductor section within a second conductor layer neighboring the first conductor layer. The closed conductor loop is configured to reduce a tendency towards oscillations of a current flowing through the conductor section in operation of the circuitry arrangement. The conductor loop is closed via at least one electronic component mounted to an outer surface of the circuit board.Type: GrantFiled: March 14, 2014Date of Patent: February 24, 2015Assignee: SMA Solar Technology AGInventor: Regine Mallwitz
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Patent number: 8963658Abstract: A structure having a coplanar waveguide transistor; and a microwave section, coupled to the transistor, having: a strip conductor coplanar with the electrodes of the coplanar waveguide transistor and a ground plane conductor disposed under the strip conductor.Type: GrantFiled: September 21, 2010Date of Patent: February 24, 2015Assignee: Raytheon CompanyInventors: James J. Chen, Nicholas J. Kolias, Francois Y. Colomb
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Patent number: 8952540Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.Type: GrantFiled: June 30, 2011Date of Patent: February 10, 2015Assignee: Intel CorporationInventors: Mihir K. Roy, Mathew J. Manusharow
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Patent number: 8952521Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.Type: GrantFiled: January 8, 2013Date of Patent: February 10, 2015Assignee: Infineon Technologies AGInventors: Maciej Wojnowski, Walter Hartner, Ottmar Geitner, Gottfried Beer, Klaus Pressel, Mehran Pour Mousavi
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Patent number: 8946894Abstract: Methods and apparatuses for forming a package for high-power semiconductor devices are disclosed herein. A package may include a plurality of distinct thermal spreader layers disposed between a die and a metal carrier. Other embodiments are described and claimed.Type: GrantFiled: February 18, 2013Date of Patent: February 3, 2015Assignee: TriQuint Semiconductor, Inc.Inventors: Tarak A. Railkar, Deep C. Dumka
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Patent number: 8928139Abstract: Embodiments described herein provide enhanced integrated circuit (IC) devices. In an embodiment, an IC device includes a substrate, an IC die coupled to a surface of the substrate, a first wirelessly enabled functional block located, on the IC die, the first wirelessly enabled functional block being configured to wirelessly communicate with a second wirelessly enabled functional block located on the substrate, and a ground ring configured to provide electromagnetic shielding for the first and second wirelessly enabled functional blocks.Type: GrantFiled: September 30, 2011Date of Patent: January 6, 2015Assignee: Broadcom CorporationInventors: Sam Ziqun Zhao, Michael Boers, Ahmadreza Rofougaran, Arya Behzad, Jesus Castaneda
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Patent number: 8912634Abstract: A mmWave electronics package constructed from common Printed Circuit Board (PCB) technology and a metal cover. Assembly of the package uses standard pick and place technology and heat is dissipated directly to a pad on the package. Input/output of mmWave signal(s) is achieved through a rectangular waveguide. Mounting of the electronic package to an electrical printed circuit board (PCB) is performed using conventional reflow soldering processes and includes a waveguide I/O connected to an mmWave antenna. The electronic package provides for transmission of low frequency, dc and ground signals from the semiconductor chip inside the package to the PCB it is mounted on. An impedance matching scheme matches the chip to high frequency board transition by altering the ground plane within the chip. A ground plane on the high frequency board encircles the high frequency signal bump to confine the electromagnetic fields to the bump region reducing radiation loss.Type: GrantFiled: March 29, 2012Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: Elad Danny, Kaminski Noam, Okamoto Keishi, Shumaker Evgeny, Toriyama Kazushige
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Patent number: 8912647Abstract: According to one embodiment, provided is a semiconductor device includes: a high frequency semiconductor chip; an input matching circuit disposed at the input side of the high frequency semiconductor chip; an output matching circuit disposed at the output side of the high frequency semiconductor chip; a high frequency input terminal connected to the input matching circuit; a high frequency output terminal connected to the output matching circuit, and a smoothing capacitor terminal connected to the high frequency semiconductor chip. The high frequency semiconductor chip, the input matching circuit and the output matching circuit are housed by one package.Type: GrantFiled: June 20, 2011Date of Patent: December 16, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Kazutaka Takagi
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Patent number: 8902123Abstract: To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first antenna is provided over a second substrate, and the first substrate and the second substrate are bonded to each other to manufacture a semiconductor device. The first substrate and the second substrate are bonded to each other by bonding with a bonding layer interposed therebetween, anodic bonding, or surface activated bonding.Type: GrantFiled: December 28, 2012Date of Patent: December 2, 2014Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koji Dairiki, Konami Izumi
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Patent number: 8890297Abstract: A light emitting device package according to embodiments comprises: a package body; a lead frame on the package body; a light emitting device supported by the package body and electrically connected with the lead frame; a filling material surrounding the light emitting device; and a phosphor layer comprising phosphors on the filling material.Type: GrantFiled: December 20, 2011Date of Patent: November 18, 2014Assignee: LG Innotek Co., Ltd.Inventors: Yu Ho Won, Geun Ho Kim
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Patent number: 8890303Abstract: A three-dimensional integrated circuit, including a first adhesive bonding layer, a first chip, a second chip, and an inter-stratum thermal pad, is provided. The first adhesive bonding layer has a first surface and a second surface opposite to each other. The first chip is disposed on the first surface of the first adhesive bonding layer. The first chip includes a hot zone. The second chip is disposed on the second surface of the first adhesive bonding layer. The inter-stratum thermal pad is embedded in the first adhesive bonding layer and faces to the hot zone.Type: GrantFiled: March 14, 2013Date of Patent: November 18, 2014Assignee: National Chiao Tung UniversityInventors: An-Nan Tan, Hung-Ming Chen
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Patent number: 8884428Abstract: Embodiments described herein provide enhanced integrated circuit (IC) devices. In an embodiment, an IC device includes a substrate, an IC die coupled to a surface of the substrate, a first wirelessly enabled functional block located, on the IC die, the first wirelessly enabled functional block being configured to wirelessly communicate with a second wirelessly enabled functional block located on the substrate, and a ground ring configured to provide electromagnetic shielding for the first and second wirelessly enabled functional blocks.Type: GrantFiled: September 30, 2011Date of Patent: November 11, 2014Assignee: Broadcom CorporationInventors: Sam Ziqun Zhao, Michael Boers, Ahmadreza Rofougaran, Arya Behzad, Jesus Castaneda
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Patent number: 8872328Abstract: An integrated power module includes a substantially planar insulated metal substrate having at least one cut-out region; at least one substantially planar ceramic substrate disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer on a first side and a second metal layer on a second side; at least one power semiconductor device coupled to the first side of the ceramic substrate; at least one control device coupled to a first surface of the insulated metal substrate; a power overlay electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages are provided in the cooling fluid reservoir.Type: GrantFiled: December 19, 2012Date of Patent: October 28, 2014Assignee: General Electric CompanyInventors: Eladio Clemente Delgado, John Stanley Glaser, Brian Lynn Rowden
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Patent number: 8872333Abstract: A millimeter wave integrated waveguide interface package device may comprise: (1) a package comprising a printed wiring board (PWB) and a monolithic microwave integrate circuit (MMIC), wherein the MMIC is in communication with the PWB; and (2) a waveguide interface integrated with the package. The package may be adapted to operate at high frequency and high power, where high frequency includes frequencies greater than about 5 GHz, and high power includes power greater than about 0.5 W.Type: GrantFiled: December 5, 2011Date of Patent: October 28, 2014Assignee: ViaSat, Inc.Inventors: Noel A Lopez, Michael R Lyons, Dave Laidig, Kenneth V Buer
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Patent number: 8866291Abstract: A microstrip MMIC chip flip-chip mounted to a printed circuit board with conductive vias passing through the chip to electrical connect a ground plane of the microstrip MMIC chip to a ground conductor of the printed circuit board.Type: GrantFiled: February 10, 2012Date of Patent: October 21, 2014Assignee: Raytheon CompanyInventor: Roberto W. Alm
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Patent number: 8866289Abstract: A sealing and bonding material structure for joining semiconductor wafers having monolithically integrated components. The sealing and bonding material are provided in strips forming closed loops. There are provided at least two concentric sealing strips on one wafer. The strips are laid out so as to surround the component(s) on the wafers to be sealed off when wafers are bonded together. The material in the strips is a material bonding the semiconductor wafers together and sealing off the monolithically integrated components when subjected to force and optionally heating. A monolithically integrated electrical and/or mechanical and/or fluidic and/or optical device including a first substrate and a second substrate, bonded together with the sealing and bonding structure, and a method of providing a sealing and bonding material structure on at least one of two wafers and applying a force and optionally heat to the wafers to join them are described.Type: GrantFiled: January 5, 2012Date of Patent: October 21, 2014Assignee: Silex Microsystems ABInventors: Thorbjorn Ebefors, Edward Kalvesten, Niklas Svedin, Anders Eriksson
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Patent number: 8866292Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A first chip is disposed in the substrate. The first chip includes a plurality of contact pads at the first major surface. A via bar is disposed in the substrate. An antenna structure is disposed within the via bar.Type: GrantFiled: January 8, 2013Date of Patent: October 21, 2014Assignee: Infineon Technologies AGInventors: Gottfried Beer, Maciej Wojnowski, Mehran Pour Mousavi
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Patent number: 8853547Abstract: A flexible printed circuit board, in particular for the spatial connection of electronic components, includes a carrier foil (1), several bonding surfaces (10) arranged on a solder side (4) of the carrier foil (1), and several soldering surfaces (2) arranged on a bonding side (12) of the carrier foil (1) opposite the solder side. The soldering surfaces (2) are connected to the bonding surfaces (10) via electrical strip conductors, and a stiffening plate (3) is inseparably connected to the carrier foil (1) on the solder side thereof.Type: GrantFiled: October 9, 2009Date of Patent: October 7, 2014Assignees: Conti Temic microelectronic GmbH, Carl Freudenberg KGInventors: Andreas Voegerl, Tilo Liebl, Gerhard Bauer, Marion Gebhardt, Alexander Wenk, Matthias Wieczorek, Juergen Henniger, Karl-Heinz Baumann
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Patent number: 8847383Abstract: An integrated circuit package strip employs a stiffener layer that houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units.Type: GrantFiled: February 1, 2012Date of Patent: September 30, 2014Assignee: ATI Technologies ULCInventors: Neil R. McLellan, Vincent K. Chan, Roden R. Topacio, III
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Patent number: 8824974Abstract: The present invention provides a semiconductor integrated circuit device and a radio frequency module realizing reduction in high-order harmonic distortion or IMD. For example, a so-called antenna switch having a plurality of transistors between an antenna terminal and a plurality of signal terminals is provided with a voltage supply circuit. The voltage supply circuit is a circuit for supplying voltage from a voltage supply terminal to at least two signal terminals in the plurality of signal terminals via resistive elements. With the configuration, antenna voltage dropped due to a leakage or the like can be boosted and, for example, transistors in an off state can be set to a deep off state.Type: GrantFiled: October 22, 2010Date of Patent: September 2, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Akishige Nakajima, Yasushi Shigeno, Takashi Ogawa, Shinnichirou Takatani, Shinya Osakabe, Tomoyuki Ishikawa
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Patent number: 8816497Abstract: An electronic component includes a III-N transistor and a III-N rectifying device both encased in a single package. A gate electrode of the III-N transistor is electrically connected to a first lead of the single package or to a conductive structural portion of the single package, a drain electrode of the III-N transistor is electrically connected to a second lead of the single package and to a first electrode of the III-N rectifying device, and a second electrode of the III-N rectifying device is electrically connected to a third lead of the single package.Type: GrantFiled: January 8, 2010Date of Patent: August 26, 2014Assignee: Transphorm Inc.Inventor: Yifeng Wu
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Patent number: 8811027Abstract: A DC-DC converter includes an insulating substrate with an inductor provided on the top surface thereof, a switching control IC provided therein, and a ground electrode pattern provided on the bottom surface thereof. The ground electrode pattern includes a first pattern and a second pattern separated from each other and a bridge pattern that connects the first and second patterns to each other. A capacitor and the switching control IC is connected to each of the first and second patterns. The bridge pattern faces the inductor and has a smaller width than that of the first and second patterns.Type: GrantFiled: August 14, 2012Date of Patent: August 19, 2014Assignee: Murata Manufacturing Co., Ltd.Inventor: Noboru Kato
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Patent number: 8810030Abstract: A MEMS device (20) with stress isolation includes elements (28, 30, 32) formed in a first structural layer (24) and elements (68, 70) formed in a second structural layer (26), with the layer (26) being spaced apart from the first structural layer (24). Fabrication methodology (80) entails forming (92, 94, 104) junctions (72, 74) between the layers (24, 26). The junctions (72, 74) connect corresponding elements (30, 32) of the first layer (24) with elements (68, 70) of the second layer (26). The fabrication methodology (80) further entails releasing the structural layers (24, 26) from an underlying substrate (22) so that all of the elements (30, 32, 68, 70) are suspended above the substrate (22) of the MEMS device (20), wherein attachment of the elements (30, 32, 68, 70) with the substrate (22) occurs only at a central area (46) of the substrate (22).Type: GrantFiled: February 3, 2012Date of Patent: August 19, 2014Assignee: Freescale Semiconductor, Inc.Inventor: Aaron A. Geisberger