For High Frequency (e.g., Microwave) Device Patents (Class 257/728)
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Patent number: 8803314Abstract: A method for forming an integrated circuit includes transforming at least a portion of a first substrate layer to form a conductive region within the first substrate layer. An integrated circuit device is provided proximate an outer surface of the first substrate layer. The integrated circuit device transmits or receives electrical signals through the conductive region. A second substrate layer is disposed proximate to the outer surface of the first substrate layer to enclose the integrated circuit device in a hermetic environment.Type: GrantFiled: December 14, 2012Date of Patent: August 12, 2014Assignee: Raytheon CompanyInventors: Premjeet Chahal, Francis J. Morris
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Patent number: 8803315Abstract: A semiconductor component is face-up mounted on a package substrate. An antenna substrate is flip-chip mounted on a front side of the semiconductor component. A device-side high-frequency signal terminal is disposed on the front side of the semiconductor component, and an antenna-side high-frequency signal terminal is disposed on a back side of the antenna substrate. The device-side high-frequency signal terminal and the antenna-side high-frequency signal terminal are electrically connected to each other. Thus, the antenna substrate for high-frequency signals can be separated from the package substrate for baseband signals.Type: GrantFiled: January 29, 2013Date of Patent: August 12, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Koichi Takizawa, Yoshihiko Goto, Kaoru Sudo, Hirotaka Fujii
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Patent number: 8803334Abstract: A semiconductor package including a substrate, a chip stack portion disposed on the substrate and including a plurality of first semiconductor chips, at least one second semiconductor chip disposed on the chip stack portion, and a signal transmitting medium to electrically connect the at least one second semiconductor chip and the substrate to each other, such that the chip stack portion is a parallelepiped structure including a first chip that is a semiconductor chip of the plurality of first semiconductor chips and includes a through silicon via (TSV), a second chip that is another semiconductor chip of the plurality of first semiconductor chips and electrically connected to the first chip through the TSV, and an internal sealing member to fill a space between the first chip and the second chip.Type: GrantFiled: November 9, 2012Date of Patent: August 12, 2014Assignee: Samsung Electronics Co., LtdInventors: Yun-seok Choi, Tae-je Cho
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Patent number: 8796697Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.Type: GrantFiled: March 14, 2013Date of Patent: August 5, 2014Assignee: Mitsubishi Electric CorporationInventors: Tetsuo Kunii, Seiichi Tsuji, Motoyoshi Koyanagi
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Patent number: 8786061Abstract: A semiconductor device includes a first semiconductor substrate and a second semiconductor substrate laminated with an insulating layer, a first transmission line formed on the first semiconductor substrate, the first transmission line including a signal line and a ground, a second transmission line formed on the second semiconductor substrate, the second transmission line including a signal line and a ground, a first via layer for the signal lines, the first via layer for the signal lines being formed of a conductor layer formed within a via hole, a first via layer for the grounds, the first via layer for the grounds being formed of a conductor layer formed within a via hole, and a second via layer for the grounds, the second via layer for the grounds being formed of a conductor layer formed within a via hole.Type: GrantFiled: April 4, 2012Date of Patent: July 22, 2014Assignee: Sony CorporationInventor: Ken Sawada
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Patent number: 8786079Abstract: Antenna switch modules and methods of making the same are provided. In certain implementations, an antenna switch module includes a package substrate, an integrated filter, and a silicon on insulator (SOI) die attached to the package substrate. The SOI die includes a capacitor configured to operate in the integrated filter and a multi throw switch for selecting amongst the RF signal paths. In some implementations, a surface mount inductor is attached to the package substrate adjacent the SOI die and is configured to operate in the integrated filter with the capacitor. In certain implementations, the inductor is formed from a conductive layer of the package substrate disposed beneath a layer of the package substrate used to attach the SOI die.Type: GrantFiled: August 8, 2012Date of Patent: July 22, 2014Assignee: Skyworks Solutions, Inc.Inventors: Jong-Hoon Lee, Chuming Shih
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Patent number: 8779599Abstract: A device includes a bottom chip and an active top die bonded to the bottom chip. A dummy die is attached to the bottom chip. The dummy die is electrically insulated from the bottom chip.Type: GrantFiled: November 16, 2011Date of Patent: July 15, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jing-Cheng Lin, Cheng-Lin Huang, Szu Wei Lu, Jui-Pin Hung, Shin-Puu Jeng, Chen-Hua Yu
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Patent number: 8779562Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a bottom substrate; attaching a first integrated circuit die to the bottom substrate; forming an interposer including: forming an intermediate substrate; forming a shield on the intermediate substrate; and applying a wire-in-film adhesive to the shield; and attaching the interposer to the first integrated circuit die with the wire-in-film adhesive.Type: GrantFiled: March 24, 2011Date of Patent: July 15, 2014Assignee: STATS ChipPAC Ltd.Inventors: SeongMin Lee, Sungmin Song, SeongHun Mun
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Patent number: 8772914Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.Type: GrantFiled: January 15, 2013Date of Patent: July 8, 2014Assignee: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Kenta Ogawa
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Patent number: 8766455Abstract: A semiconductor device includes a first semiconductor chip, a first connection structure disposed on a first side of the first semiconductor chip, a second semiconductor chip disposed on a second side of the first semiconductor chip, and a second connection structure disposed between the first and second semiconductor chips, wherein a number of the second connection structures is less than a number of the first connection structures.Type: GrantFiled: September 22, 2011Date of Patent: July 1, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: SeYoung Jeong, Sunpil Youn, Hogeon Song
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Patent number: 8753922Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.Type: GrantFiled: January 15, 2013Date of Patent: June 17, 2014Assignee: Renesas Electronics CorporationInventors: Yasutaka Nakashiba, Kenta Ogawa
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Patent number: 8749056Abstract: A module and a method for manufacturing a module are disclosed. An embodiment of a module includes a first semiconductor device, a frame arranged on the first semiconductor device, the frame including a cavity, and a second semiconductor device arranged on the frame wherein the second semiconductor device seals the cavity.Type: GrantFiled: May 26, 2011Date of Patent: June 10, 2014Assignee: Infineon Technologies AGInventors: Daniel Kehrer, Stefan Martens, Tze Yang Hin, Helmut Wietschorke, Horst Theuss, Beng Keh See, Ulrich Krumbein
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Patent number: 8749032Abstract: An integrated circuit is disclosed having through silicon vias spaced apart one from another and conductors, each coupled to one or more of the through silicon vias, the conductors in aggregate in use forming a segmented conductive plane maintained at a same potential and forming an electromagnetic shield.Type: GrantFiled: December 1, 2009Date of Patent: June 10, 2014Assignee: SiGe Semiconductor, Inc.Inventors: Mark Doherty, Michael McPartlin, Chun-Wen Paul Huang
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Patent number: 8736031Abstract: There is provided a semiconductor package, and more particularly, a semiconductor package including an antenna embedded in an inner portion thereof. The semiconductor package includes: a semiconductor chip; a main antenna disposed to be adjacent to the semiconductor chip and electrically connected thereto; a sealing part sealing both of the semiconductor chip and the main antenna; and an auxiliary antenna formed on an outer surface of the sealing part and coupled to the main antenna.Type: GrantFiled: September 23, 2011Date of Patent: May 27, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jung Aun Lee, Myeong Woo Han, Do Jae Yoo, Chul Gyun Park
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Patent number: 8729680Abstract: A semiconductor device includes a structure in which a semiconductor element (chip) is mounted in a cavity formed in a wiring board with an adhesive interposed between the chip and a bottom surface of the cavity, and electrode terminals of the chip are connected via wires to wiring portions formed on the board around the cavity. The chip is mounted in close contact with a side wall of the cavity, the side wall being near a region where a wiring for higher frequency compared with other wirings within the wiring portion is formed. A recessed portion is provided in a region of the bottom surface of the cavity, and a thermal via extending from the bottom surface of the recessed to the outside of the board is provided, the region being near a portion where the chip is in close contact.Type: GrantFiled: November 14, 2012Date of Patent: May 20, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Narue Kobayashi, Tomoharu Fujii, Yukiharu Takeuchi
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Structure for high-speed signal integrity in semiconductor package with single-metal-layer substrate
Patent number: 8723337Abstract: A semiconductor chip (101) with bond pads (110) on a substrate (103) with rows and columns of regularly pitched metal contact pads (131). A zone comprises a first pair (131a, 131b) and a parallel second pair (131c, 131d) of contact pads, and a single contact pad (131e) for ground potential; staggered pairs of stitch pads (133) connected to respective pairs of adjacent contact pads by parallel and equal-length traces (132a, 132b, etc.). Parallel and equal-length bonding wires (120a, 120b, etc.) connect bond pad pairs to stitch pad pairs, forming differential pairs of parallel and equal-length conductor lines. Two differential pairs in parallel and symmetrical position form a transmitter/receiver cell for conducting high-frequency signals.Type: GrantFiled: November 29, 2011Date of Patent: May 13, 2014Assignee: Texas Instruments IncorporatedInventors: Gregory E. Howard, Matthew D. Romig, Marie-Solange Anne Milleron, Souvik Mukherjee -
Patent number: 8722459Abstract: Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing.Type: GrantFiled: December 31, 2012Date of Patent: May 13, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Paul W. Sanders, Robert E. Jones, Michael F. Petras
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Patent number: 8710655Abstract: A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die.Type: GrantFiled: July 11, 2012Date of Patent: April 29, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun-Joong Kim, Jang Seok Choi, Chul-Hwan Choo
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Patent number: 8704384Abstract: A stacked die assembly for an IC includes a first interposer; a second interposer; a first integrated circuit die, a second integrated circuit die, and a plurality of components. The first integrated circuit die is interconnected to the first interposer and the second interposer, and the second integrated circuit die is interconnected to the second interposer. The plurality of components interconnect the first integrated circuit die to the first interposer and the second interposer. The plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area of the first interposer and the second interposer, and signals are routed between the first integrated circuit die and the second integrated circuit die via the first integrated circuit die avoiding the interconnect restricted area of the first interposer and the second interposer.Type: GrantFiled: February 17, 2012Date of Patent: April 22, 2014Assignee: Xilinx, Inc.Inventors: Ephrem C. Wu, Raghunandan Chaware
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Patent number: 8698289Abstract: The semiconductor device is high in both heat dissipating property and connection reliability in mounting. The semiconductor device includes a semiconductor chip, a resin sealing member for sealing the semiconductor chip, a first conductive member connected to a first electrode formed on a first main surface of the semiconductor chip, and a second conductive member connected to a second electrode formed on a second main surface opposite to the first main surface of the semiconductor chip, the first conductive member being exposed from a first main surface of the resin sealing member, and the second conductive member being exposed from a second main surface opposite to the first main surface of the resin sealing member and also from side faces of the resin sealing member.Type: GrantFiled: August 24, 2011Date of Patent: April 15, 2014Assignee: Renesas Electronics CorporationInventors: Yukihiro Satou, Takeshi Otani, Hiroyuki Takahashi, Toshiyuki Hata, Ichio Shimizu
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Patent number: 8686566Abstract: A coreless pin-grid array (PGA) substrate includes PGA pins that are integral to the PGA substrate without the use of solder. A process of making the coreless PGA substrate integrates the PGA pins by forming a build-up layer upon the PGA pins such that vias make direct contact to pin heads of the PGA pins.Type: GrantFiled: June 30, 2011Date of Patent: April 1, 2014Assignee: Intel CorporationInventors: Mihir K. Roy, Matthew J. Manusharow
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Patent number: 8653649Abstract: A device housing package includes a substrate having a device mounting region; a frame body having a through hole formed in part thereof, the frame body being disposed on the substrate so as to lie along a periphery of the device mounting region; and an input-output terminal disposed in the through hole, having a first dielectric layer; a signal line formed on the first dielectric layer; a first ground layer formed on a lower face of the first dielectric layer; a second dielectric layer formed on the signal line so as to overlap the frame body; a second ground layer formed on an upper face of the second dielectric layer; and a metal layer disposed within the second dielectric layer The metal layer is formed to extend from the second dielectric layer to the first dielectric layer, being separated from the signal line.Type: GrantFiled: September 24, 2010Date of Patent: February 18, 2014Assignee: Kyocera CorporationInventors: Mahiro Tsujino, Mamoru Kinoshita, Kiyoshige Miyawaki
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Patent number: 8643492Abstract: Encapsulated radio frequency identification (RFID) articles having enhanced break strength and/or temperature resistance and methods of making these articles. The RFID articles include an RFID tag embedded within a thermoplastic substrate to form the RFID article. In one embodiment, the RFID article includes an over-molded barrier material that enables the RFID article to have enhanced temperature resistance such that the articles are able top sustain repeated exposure to high temperatures and/or sterilization procedures, thereby enabling the RFID articles to be utilized in applications heretofore unavailable. In other embodiments, the RFID articles are made using an injection molding process that provides very thin encapsulated RFID tags that also exhibit an increased level of temperature resistance.Type: GrantFiled: August 30, 2012Date of Patent: February 4, 2014Assignee: Sabic Innovative Plastics IP B.V.Inventors: Sudhakar R. Marur, Theethira Kushalappa Poovanna, Venkatesha Narayanaswamy
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Patent number: 8643176Abstract: A semiconductor chip includes a power transistor circuit with a plurality of active transistor cells. A first load electrode and a control electrode are arranged on a first face of the semiconductor chip, wherein the first load electrode includes a first metal layer. A second load electrode is arranged on a second face of the semiconductor chip. A second metal layer is arranged over the first metal layer, wherein the second metal layer is electrically insulated from the power transistor circuit and the second metal layer is arranged over an area of the power transistor circuit that comprises at least one of the plurality of active transistor cells.Type: GrantFiled: July 27, 2011Date of Patent: February 4, 2014Assignee: Infineon Technologies AGInventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel
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Patent number: 8618655Abstract: A carrier-free semiconductor package includes a circuit structure having an insulating layer and a circuit layer embedded in the insulating layer and having a plurality of conductive traces and RF (radio frequency) traces, a chip disposed on a first surface of the insulating layer and electrically connected to the conductive traces, an encapsulant covering the chip and the circuit layer, a ground layer formed on a second surface of the insulating layer opposite to the first surface, and a plurality of solder balls disposed on the conductive traces or terminals on the conductive traces, wherein portions of the solder balls electrically connect the ground layer so as to allow the RF traces and the ground layer to form a microstrip line having an RF function, thus obtaining a single-layer carrier-free semiconductor package having low cost and simplified RF design.Type: GrantFiled: May 19, 2011Date of Patent: December 31, 2013Assignee: Siliconware Precision Industries Co., LtdInventors: Ching-Hua Chen, Heng-Cheng Chu, Hsin-Lung Chung, Chih-Hsien Chiu, Chia-Yang Chen
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Patent number: 8619003Abstract: To provide a semiconductor device in which wireless communication is performed between devices formed over different substrates and connection defects of wirings are reduced. A first device having a first antenna is provided over a first substrate, a second device having a second antenna which can communicate with the first antenna is provided over a second substrate, and the first substrate and the second substrate are bonded to each other to manufacture a semiconductor device. The first substrate and the second substrate are bonded to each other by bonding with a bonding layer interposed therebetween, anodic bonding, or surface activated bonding.Type: GrantFiled: March 24, 2008Date of Patent: December 31, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koji Dairiki, Konami Izumi
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Patent number: 8618656Abstract: A flexible semiconductor package apparatus having a responsive bendable conductive wire member is presented. The apparatus includes a flexible substrate, semiconductor chips, and conductive wires. The semiconductor chips are disposed on the flexible substrate and spaced apart from each other on the flexible substrate. Each semiconductor chip has bonding pads. The conductive wires are electrically connected to the bonding pads of the semiconductor chip. Each conductive wire has at least one elastic portion. One preferred configuration is that part of the conductive wire is wound to form a coil spring shape so that the coil spring shape of the conductive wire aid in preventing the conductive wire from being separated from the corresponding bonding pad of the semiconductor chip when the flexible substrate on which the semiconductor chips are mounted are bent, expanded or twisted.Type: GrantFiled: September 23, 2011Date of Patent: December 31, 2013Assignee: Hynix Semiconductor Inc.Inventors: Tac Keun Oh, Sung Min Kim
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Patent number: 8610255Abstract: A light emitting device package according to embodiments comprises: a package body; a lead frame on the package body; a light emitting device supported by the package body and electrically connected with the lead frame; a filling material surrounding the light emitting device; and a phosphor layer comprising phosphors on the filling material.Type: GrantFiled: July 4, 2008Date of Patent: December 17, 2013Assignee: LG Innotek Co., Ltd.Inventors: Yu Ho Won, Geun Ho Kim
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Patent number: 8604615Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip.Type: GrantFiled: July 1, 2011Date of Patent: December 10, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Chung-Sun Lee, Jung-Hwan Kim, Tae-Hong Min, Hyun-Jung Song, Sun-Pil Youn
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Patent number: 8606193Abstract: An RF transceiver integrated circuit has a novel segmented, low parasitic capacitance, internal loopback conductor usable for conducting IP2 self testing and/or calibration. In a first novel aspect, the transmit mixer of the transceiver is a current mode output mixer. The receive mixer is a passive mixer that has a low input impedance. In the loopback mode, the transmit mixer drives a two tone current signal to the passive mixer via the loopback conductor. In a second novel aspect, only one quadrature branch of the transmit mixer is used to generate both tones required for carrying out an IP2 test. In a third novel aspect, a first calibration test is performed using one quadrature branch of the transmit mixer at the same time that a second calibration test is performed using the other quadrature branch, thereby reducing loopback test time and power consumption.Type: GrantFiled: November 13, 2008Date of Patent: December 10, 2013Assignee: QUALCOMM IncorporatedInventors: Jin-Su Ko, Michael Kohlmann, Bahman Ahrari
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Patent number: 8598694Abstract: Various embodiments provide a chip-carrier including, a chip-carrier surface configured to carry a first chip from a first chip bottom side, wherein a first chip top side of the first chip is configured above the chip-carrier surface; and at least one cavity extending into the chip-carrier from the chip-carrier surface; wherein the at least one cavity is configured to carry a second chip from a second chip bottom side, wherein a second chip top side of the second chip is substantially level with the first chip top side. The second chip is electrically insulated from the chip-carrier by an electrical insulation material inside the cavity.Type: GrantFiled: November 22, 2011Date of Patent: December 3, 2013Assignee: Infineon Technologies AGInventors: Khalil Hosseini, Joachim Mahler, Anton Prueckl
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Patent number: 8598709Abstract: A method and a system for routing electrical connections are disclosed. A semiconductor device includes a first semiconductor chip and a routing plane having a plurality of routing lines. A first connecting line is electrically coupled to the first semiconductor chip and one of the plurality of routing lines and a second connecting line is electrically coupled to the one of the plurality of routing lines and to one of a second semiconductor chip or a first external contact element.Type: GrantFiled: August 31, 2010Date of Patent: December 3, 2013Assignee: Infineon Technologies AGInventors: Thorsten Meyer, Gottfried Beer, Christian Geissler, Thomas Ort, Klaus Pressel, Bernd Waidhas, Andreas Wolter
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Patent number: 8592960Abstract: A MMIC package is disclosed comprising: a leadframe based overmolded package, a die positioned within the overmolded package; and a partial waveguide interface, wherein the partial waveguide interface is integral with the overmolded package facilitating low cost and reliable assembly. Also disclosed is an overmolded package where the die sits on a metal portion exposed on the bottom of the package and the package is configured for attachment to a chassis of a transceiver such that heat from the die is easily dissipated to the chassis with a direct thermal path. The disclosure facilitates parallel assembly of MMIC packages and use of pick and place/surface mounting technology for attaching the MMIC packages to the chassis of transceivers. This facilitates reliable and low cost transceivers.Type: GrantFiled: August 30, 2011Date of Patent: November 26, 2013Assignee: ViaSat, Inc.Inventors: David R. Laidig, Kenneth V. Buer, Michael R. Lyons, Noel Lopez
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Patent number: 8592957Abstract: Provided is a semiconductor device including a wiring board having a first surface on which a board-side ground terminal and a board-side power supply terminal are provided; a semiconductor chip arranged so as to face the first surface of the wiring board, where the first surface faces an opposite surface of the semiconductor chip; a shield layer provided at the semiconductor chip so as to cover an outer surface of the semiconductor chip except for the opposite surface; a chip-side power supply terminal which is provided on the opposite surface and is electrically connected to the board-side power supply terminal; a chip-side ground terminal which is provided on the opposite surface and is electrically connected to the board-side ground terminal and the shield layer; and a first capacitively coupled part by which the shield layer and the chip-side power supply terminal are capacitively coupled with each other.Type: GrantFiled: June 9, 2010Date of Patent: November 26, 2013Assignee: NEC CorporationInventor: Yoshiaki Wakabayashi
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Patent number: 8587088Abstract: A die package having a vertical stack of dies and side-mounted circuitry and methods for making the same are disclosed, for use in an electronic device. The side-mounted circuitry is mounted to a vertical surface of the stack, as opposed to a top surface or adjacent of the stack to reduce the volume of the NVM package.Type: GrantFiled: February 17, 2011Date of Patent: November 19, 2013Assignee: Apple Inc.Inventor: Nicholas Seroff
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Patent number: 8569881Abstract: A semiconductor device includes a baseplate and a first and a second insulated gate bipolar transistor (IGBT) substrate coupled to the baseplate. The semiconductor device includes a first and a second diode substrate coupled to the baseplate and a first, a second, and a third control substrate coupled to the baseplate. Bond wires couple the first and second IGBT substrates to the first control substrate. Bond wires couple the first and second IGBT substrates to the second control substrate via the first and second diode substrates, and bond wires couple the first and second IGBT substrates to the third control substrate via the second diode substrate.Type: GrantFiled: September 8, 2010Date of Patent: October 29, 2013Assignee: Infineon Technologies AGInventors: Reinhold Spanke, Waleri Brekel, Ivonne Benzler
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Patent number: 8569884Abstract: A microelectronic package includes a subassembly including a first substrate and first and second microelectronic elements having contact-bearing faces facing towards oppositely-facing first and second surfaces of the first substrate and each having contacts electrically connected with the first substrate. The contact-bearing faces of the first and second microelectronic elements at least partially overlie one another. Leads electrically connect the subassembly with a second substrate, at least portions of the leads being aligned with an aperture in the second substrate. The leads can include wire bonds extending through an aperture in the first substrate and joined to contacts of the first microelectronic element aligned with the first substrate aperture. In one example, the subassembly can be electrically connected with the second substrate using electrically conductive spacer elements.Type: GrantFiled: August 15, 2011Date of Patent: October 29, 2013Assignee: Tessera, Inc.Inventors: Belgacem Haba, Wael Zohni, Richard Dewitt Crisp
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Patent number: 8558380Abstract: A semiconductor package includes a first semiconductor chip having first bumps which are projectedly formed thereon; a first copper foil attachment resin covered on the first semiconductor chip to embed the first semiconductor chip, and formed such that a first copper foil layer attached on an upper surface of the first copper foil attachment resin is electrically connected with the first bumps; a second copper foil attachment resin including a second copper foil layer which is electrically connected with the first copper foil layer, and disposed on the first copper foil attachment resin; and a second semiconductor chip embedded in the second copper foil attachment resin in such a way as to face the first semiconductor chip, and having second bumps formed thereon which are electrically connected with the second copper foil layer.Type: GrantFiled: February 3, 2012Date of Patent: October 15, 2013Assignee: SK Hynix Inc.Inventors: Si Han Kim, Woong Sun Lee
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Patent number: 8546939Abstract: A technology is provided so that RF modules used for cellular phones etc. can be reduced in size. Over a wiring board constituting an RF module, there are provided a first semiconductor chip in which an amplifier circuit is formed and a second semiconductor chip in which a control circuit for controlling the amplifier circuit is formed. A bonding pad over the second semiconductor chip is connected with a bonding pad over the first semiconductor chip directly by a wire without using a relay pad. In this regard, the bonding pad formed over the first semiconductor chip is not square but rectangular (oblong).Type: GrantFiled: December 29, 2006Date of Patent: October 1, 2013Assignee: Murata Manufacturing Co., Ltd.Inventors: Kenji Sasaki, Tomonori Tanoue, Sakae Kikuchi, Toshifumi Makino, Takeshi Sato, Tsutomu Kobori, Yasunari Umemoto, Takashi Kitahara
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Patent number: 8546927Abstract: An RFIC module includes an RFIC chip that is mounted on a mounting substrate and that is encapsulated with an encapsulation resin layer. The mounting substrate includes a flexible base and electrodes provided on the flexible base. External terminals are disposed near four corners of a mounting surface of the RFIC chip. One of a plurality of mounting lands located on the surface of the flexible base is a shared mounting land and defines an integrated mounting land that is shared by an RF terminal and an NC terminal of the RFIC chip. The shared mounting land is arranged to cover one side of the RFIC chip when viewed from above.Type: GrantFiled: September 1, 2011Date of Patent: October 1, 2013Assignee: Murata Manufacturing Co., Ltd.Inventors: Koji Shiroki, Makoto Osamura, Takeshi Kurihara, Masami Mizuyama
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Patent number: 8531037Abstract: Disclosed is a power supply line in which a voltage drop generated in a resistance component of a metal line which delivers a power voltage is minimized so that the level of the power supply voltage delivered to a semiconductor chip becomes constant in the entire area of the semiconductor chip. The semiconductor chip includes: at least two power supply pads to which a power voltage applied from an external unit of the semiconductor chip is supplied; power supply main metal lines connected to each of the power supply pads; power supply branch metal lines extended from each of the power supply main metal lines to deliver a power voltage to a circuit in the semiconductor chip; and at least an electrostatic discharge (ESD) improvement dummy pad, wherein the ESD improvement dummy pad is electrically connected to the corresponding power supply main metal line and the corresponding power supply branch metal line to minimize a voltage drop.Type: GrantFiled: October 27, 2008Date of Patent: September 10, 2013Assignee: Silicon Works Co., Ltd.Inventors: Yong-Icc Jung, Dae-Keun Han, Dae-Seong Kim, Joon-Ho Na
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Patent number: 8517275Abstract: A semiconductor device that is resistant to bending stress and has a structure in which an antenna circuit, an electric double layer capacitor for storing electricity, and the like are formed over a signal processing circuit that is provided over a substrate and has a charging circuit. The signal processing circuit having the charging circuit is provided over a substrate, and the antenna circuit and the electric double layer capacitor are provided over the signal processing circuit. The antenna circuit is electrically connected to the signal processing circuit, and the electric double layer capacitor is electrically connected to the charging circuit. With such a structure, a wiring for connecting the charging circuit and the electric double layer capacitor can be made short. Accordingly, a semiconductor device that is resistant to bending stress can be provided.Type: GrantFiled: December 20, 2007Date of Patent: August 27, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Kaoru Tsuchiya
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Patent number: 8519537Abstract: A 3D semiconductor package using an interposer is provided. In an embodiment, an interposer is provided having a first die electrically coupled to a first side of the interposer and a second die electrically coupled to a second side of the interposer. The interposer is electrically coupled to an underlying substrate, such as a packaging substrate, a high-density interconnect, a printed circuit board, or the like. The substrate has a cavity such that the second die is positioned within the cavity. The use of a cavity may allow smaller conductive bumps to be used, thereby allowing a higher number of conductive bumps to be used. A heat sink may be placed within the cavity to aid in the dissipation of the heat from the second die.Type: GrantFiled: June 10, 2010Date of Patent: August 27, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shin-Puu Jeng, Kim Hong Chen, Shang-Yun Hou, Chao-Wen Shih, Cheng-Chieh Hsieh, Chen-Hua Yu
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Patent number: 8508045Abstract: An integrated circuit (IC) package has a package member having a first surface and a second surface opposite the first surface. A first plurality of contact members is physically and electrically fixed to the second surface. An interposer substrate having a second plurality of contact members on one surface thereof which make physical and electrical contact with respective ones of the first plurality of contact members. The interposer substrate is configured to have at least one circuit member mounted to a second surface thereof opposite the one surface thereof.Type: GrantFiled: June 30, 2011Date of Patent: August 13, 2013Assignee: Broadcom CorporationInventors: Rezaur Rahman Khan, Sam Ziqun Zhao
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Patent number: 8508023Abstract: A semiconductor device has a substrate having a plurality of metal traces. A die is electrically attached to a first surface of the substrate. A first plurality of segmented metal traces is formed around a perimeter of the first surface of the substrate, wherein an end section of the first plurality of segmented metal traces is exposed. A mold compound is used for encapsulating the semiconductor device. A first metal plating is formed on a top terminal end section of the first plurality of segmented metal traces. The first metal plating is spread to at least one of the mold compound or the exposed end sections of the first plurality of segmented metal traces. A conductive coating is applied to the mold compound, the exposed end sections of the first plurality of segmented metal traces and to the first metal plating.Type: GrantFiled: June 17, 2010Date of Patent: August 13, 2013Assignee: Amkor Technology, Inc.Inventors: Michael G. Kelly, John Cambas, Francis Tan, Pam Montero
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Patent number: 8508048Abstract: A semiconductor device which includes a substrate, a semiconductor chip which is mounted on the substrate, a package in which an upper surface of the substrate and the semiconductor chip are sealed using an insulating material, and a molding material which is exposed to the upper surface of the package. In addition, the device includes a lead of which one end is connected to the mold material and the other end is electrically connected to the substrate, which is integrally formed of the same material as from a connection portion with the mold material to a connection portion with the substrate, and of which the connection portion with the mold material is exposed to the upper surface of the package.Type: GrantFiled: November 17, 2011Date of Patent: August 13, 2013Assignee: Sony CorporationInventor: Hiroshi Honjo
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Patent number: 8508412Abstract: A semiconductor device, includes a chip, a first external terminal, a second external terminal, and a partial antenna wiring that is coupled to the first external terminal, and that constitutes a matching circuit, wherein the chip includes first and second electrode pads that are coupled to the partial antenna wiring, a third electrode pad that is different from each of the first and second electrode pads, and that is coupled to the second external terminal, and an electrostatic discharge (ESD) protection circuit that is coupled to the third electrode pad.Type: GrantFiled: May 11, 2011Date of Patent: August 13, 2013Assignee: Renesas Electronics CorporationInventor: Hatsuhide Igarashi
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Patent number: 8502377Abstract: A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap disposed along with the bumping trace in the conductive pattern to separate the bumping trace from a bulk portion of the conductive pattern. The bumping trace may have a lathy shape from a plan view and a width substantially between 10 ?m and 40 ?m and a length substantially between 70 ?m and 130 ?m, for example.Type: GrantFiled: May 19, 2011Date of Patent: August 6, 2013Assignee: Mediatek Inc.Inventors: Tzu-Hung Lin, Ching-Liou Huang, Thomas Matthew Gregorich
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Patent number: 8487430Abstract: Examples of high-speed ball grid array packages and a process of forming a package are provided. A package may include contact pads disposed on a bottom surface, conductive balls, and a signal via structure. The package may also include a first ground via structure arranged along one or more first semi-circular contours around the signal via structure and extending vertically and a second ground via structure arranged along one or more second semi-circular contours around the signal via structure and extending vertically. The package may include a ground interface plane disposed in separation from the signal contact pad by a distance. The distance may be determined based on at least a size of the signal contact pad, a dielectric constant of a transition layer between the ground interface plane and the signal contact pad, and a distance between the signal via structure and the second ground via structure.Type: GrantFiled: January 21, 2010Date of Patent: July 16, 2013Assignee: Semtech CorporationInventor: Darren Jay Walworth
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Patent number: 8476757Abstract: A monolithic microwave integrated circuit (MMIC) flip chip interconnect is formed by coating an active side of the chip with a dielectric coating, such as benzocyclobutene (BCB), that inhibits deposition of metal plating materials. A portion of the dielectric coating is removed to expose bond pads on the active side of the chip, stud bumps are bonded to the bond pads, and the active side is then plated with first and second consecutive metal plating materials, such as nickel and gold, respectively, that do not adhere to the dielectric coating. The chip is then oriented such that the plated stud bumps on the active side of the chip face bond pads on a substrate, and the stud bumps on the chip are bonded to the bond pads on the substrate.Type: GrantFiled: October 2, 2009Date of Patent: July 2, 2013Assignee: Northrop Grumman Systems CorporationInventors: Peter A. Stenger, Mark E. Schneider, Thomas A. Andersen