Abstract: A package structure, a die and method of forming the same are provided. The package structure includes a die, an encapsulant, a RDL structure, and a conductive terminal. The die has a connector. The connector includes a seed layer and a conductive on the seed layer. The seed layer extends beyond a sidewall of the conductive pillar. The encapsulant is aside the die and encapsulates sidewalls of the die. The RDL structure is electrically connected to the die. The conductive terminal is electrically connected to the die through the RDL structure.

Abstract: A semiconductor device package includes a substrate, a semiconductor chip, a first ring structure and a second ring structure. The substrate includes a surface. The semiconductor chip is over the surface of the substrate. The first ring structure is over the surface of the substrate. The second ring structure is over the surface of the substrate, wherein the first ring structure is between the semiconductor chip and the second ring structure.

Abstract: A semiconductor package includes a connection member having a first surface and a second surface opposing each other and including a first redistribution layer on the second surface and at least one second redistribution layer on a level different from a level of the first redistribution layer; a semiconductor chip on the first surface of the connection member; a passivation layer on the second surface of the connection member, and including openings; UBM layers connected to the first redistribution layer through the openings; and electrical connection structures on UBM layers. An interface between the passivation layer and the UBM layers has a first unevenness surface, an interface between the passivation layer and the first redistribution layer has a second unevenness surface, connected to the first unevenness surface, and the second unevenness surface has a surface roughness greater than a surface roughness of the second redistribution layer.

Abstract: The present disclosure is directed to a semiconductor die on a tapeless leadframe and covered in encapsulant. The semiconductor package includes leads formed from the leadframe and electrically coupled to the semiconductor die, the leads being accessible through electrical contacts embedded in the encapsulant. Openings between the leads and the leadframe are formed from etching recesses from opposing sides of the leadframe. The resulting openings have non-uniform sidewalls. The leadframe is further electrically or thermally coupled to electrical contacts embedded in the encapsulant. The embedded electrical contacts forming a land grid array.

Abstract: A microelectronic package may include stacked microelectronic dice, wherein a first microelectronic die is attached to a microelectronic substrate, and a second microelectronic die is stacked over at least a portion of the first microelectronic die, wherein the microelectronic substrate includes a plurality of pillars extending therefrom, wherein the second microelectronic die includes a plurality of pillars extending therefrom in a mirror-image configuration to the plurality of microelectronic substrate pillars, and wherein the second microelectronic die pillars are attached to microelectronic substrate pillars with an attachment material.

Abstract: A process for manufacturing a semiconductor flip chip package and a corresponding flip chip package. The process comprises associating conducting bump pads to a face corresponding to an active side of one or more electronic dice, flipping the one or more electronic dice so that said face corresponding to an active side of one or more electronic dies is facing a leadframe carrying contacting pads in correspondence of said conducting bump pads, bonding said contacting pads to said conducting bump pads and encasing said one or more electronic dice in a casing by a molding operation. The process includes providing a leadframe having contacting pads presenting a recessed surface in correspondence of the position of said conducting bump pads.

Abstract: Integrated circuit (IC) structures with extended conductive pathways, as well as related structures, devices, and methods, are disclosed herein. For example, in some embodiments, an IC structure may include a die having a device side and an opposing back side; a mold compound disposed at the back side; and a conductive pathway extending into the die from the back side and extending into the mold compound from the back side.

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes attaching a first side of an integrated circuit die to a carrier. An encapsulant is formed over and around the integrated circuit die. The encapsulant is patterned to form a first opening laterally spaced apart from the integrated circuit die and a second opening over the integrated circuit die. The first opening extends through the encapsulant. The second opening exposes a second side of the integrated circuit die. The first side of the integrated circuit die is opposite the second side of the integrated circuit die. A conductive material is simultaneously deposited in the first opening and the second opening.

Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

Abstract: A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various aspects of this disclosure provide high-yield methods for manufacturing a package-on-package type semiconductor package, or a portion thereof.

Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.

Abstract: In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

Abstract: In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die.

Abstract: The object of the present invention is to provide a technic for accurately measuring a connection state between a flexible board and a circuit board. A measurement apparatus includes a flexible board connected to a plurality of electrode terminals in a state of being superimposed on the plurality of electrode terminals provided on a circuit board, and a laser displacement meter configured to measure a height distribution of a surface of a connection portion of the plurality of electrode terminals of the circuit board. The plurality of electrode terminals are linearly arranged at a predetermined pitch, and the laser displacement meter is configured to continuously measure a height position of the surface of the connection portion while scanning from one side to an other side in an arrangement direction of the plurality of linearly arranged electrode terminals.

Abstract: An embodiment is a method including bonding a first die to a first side of an interposer using first electrical connectors, bonding a second die to first side of the interposer using second electrical connectors, attaching a first dummy die to the first side of the interposer adjacent the second die, encapsulating the first die, the second die, and the first dummy die with an encapsulant, and singulating the interposer and the first dummy die to form a package structure.

Abstract: Provided is a three-dimensional integrated circuit (3DIC) structure including a die stack structure, a metal circuit structure, and a protective structure. The die stack structure includes a first die and a second die face-to-face bonded together. The second die includes a plurality of through-substrate vias (TSVs). The metal circuit structure is disposed over a back side of the second die. The protective structure is sandwiched between and in contact with a bottom surface of the metal circuit structure and a top surface of one of the plurality of TSVs of the second die.

Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.

Abstract: A multi-wafer stacking structure is disclosed. In which a first interconnection layer is electrically connected to a second metal layer and a first metal layer via a first opening, a second interconnection layer is electrically connected to the first interconnection layer via a second opening, a third interconnection layer is electrically connected to a third metal layer via a third opening, and the second interconnection layer is electrically connected to the third interconnection layer. It is unnecessary to reserve a bonding lead space between wafers, a silicon substrate is eliminated, and the multi-wafer stacking thickness is reduced while multi-wafer interconnection is realized, so that the overall device thickness is reduced after multi-wafer stacked package. Moreover, there is no need of leads, so as to eliminate design processing of a silicon substrate and a plurality of shared bonding pads on the silicon substrate.

Abstract: A semiconductor device and method of manufacturing is provided, whereby a support structure is utilized to provide additional support for a conductive element in order to eliminate or reduce the formation of a defective surface such that the conductive element may be formed to have a thinner structure without suffering deleterious structures.

Abstract: The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device that enable prevention of generation of tape scraps from the dicing tape during dicing, and an electronic apparatus. When a semiconductor substrate on which a protective film for protecting a circuit surface is formed is divided, dicing is performed so as to form a portion in which the section width of the semiconductor substrate differs from the section width of the protective film. The present technology can be applied to a wafer level CSP manufacturing process and the like, for example.

Abstract: An embodiment package includes a first package. The first package includes a first integrated circuit die, an encapsulant around the first integrated circuit die, and redistribution layers over the encapsulant and the first integrated circuit die. The package also includes a second package bonded to the first package by a plurality of functional connectors. The functional connectors and the redistribution layers electrically connect a second integrated circuit die of the second package to the first integrated circuit die. The package also includes a plurality of dummy connectors disposed between the first package and the second package. One end of each of the plurality of dummy connectors facing the first package is physically separated from the first package.

Abstract: A method includes forming a plurality of vias in a dielectric layer and over a package substrate and forming a plurality of top pads over the dielectric layer, each of the plurality of top pads being connected to a respective via of the plurality of vias, wherein the plurality of top pads includes a first group, a second group, a third group and a fourth group, wherein the first group is separated from the fourth group by a first pad line, wherein the first group is separated from the second group by a second pad line, the first pad line comprising a plurality of first elongated pads, the second pad line comprising a plurality of second elongated pads, the second pad line being orthogonal to the first pad line.

Abstract: The semiconductor structure includes a semiconductor device, a first metallization layer on the semiconductor device, a second metallization layer on the first metallization layer, and a third dielectric layer between the first metallization layer and the second metallization layer. The first metallization layer includes a first dielectric layer and a first metal layer disposed in the first dielectric layer, wherein the first metal layer has a first thickness, and the first metal layer comprises copper. The third dielectric layer has a second thickness, and a ratio of the second thickness of the third dielectric layer to the first thickness of the first metal layer is ranged from about 3 to about 20.

Abstract: An assembly is provided including one or more semiconductor dice attached on a substrate, the semiconductor die provided with electrically-conductive stud bumps opposite the substrate. The stud bumps embedded in a molding compound molded thereon are exposed to grinding thus leveling the molding compound to expose the distal ends of the stud bumps at a surface of the molding compound. Recessed electrically-conductive lines extending over said surface of the molding compound with electrically-conductive lands over the distal ends of the stud bumps. A further molding compound is provided to cover the recessed electrically-conductive lines and surrounding the electrically-conductive lands.

Abstract: A pre-conductive array disposed on a target circuit substrate comprises a plurality of conductive electrode groups disposed on the target circuit substrate, and at least a conductive particle dispose on each of conductive electrodes of a part or all of the conductive electrode groups. The at least a conductive particle and the corresponding conductive electrode form a pre-conductive structure, and the pre-conductive structures form the pre-conductive array.

Abstract: A semiconductor package includes a connection member having first and second surfaces opposing each other and including a redistribution layer, an integrated circuit chip disposed on the first surface of the connection member, and including a plurality of units, at least one capacitor on the first surface of the connection member and in proximity to the integrated circuit chip, and an encapsulant on the first surface of the connection member and encapsulating the integrated circuit chip and the at least one capacitor, wherein the plurality of units include core power units selected from the group consisting of a central processing unit, a graphics processing unit, and an artificial intelligence unit, at least one of the core power units is disposed adjacent to one edge of the integrated circuit chip, and the at least one capacitor is disposed adjacent to the one edge of the integrated circuit chip.

Abstract: A method of manufacturing a semiconductor device in which a prescribed target lamination number of semiconductor chips are laminated on a substrate, the method includes: a first lamination step of laminating while temporarily bonding one or more semiconductor chips on the substrate to thereby form a first chip laminate body; a first permanent bonding step of pressurizing while heating from the upper side of the first chip laminate body to thereby collectively and permanently bond the one or more semiconductor chips; a second lamination step of sequentially laminating while temporarily bonding two or more semiconductor chips on the permanently bonded semiconductor chips to thereby form a second chip laminate body; and a second permanent bonding step of pressurizing while heating from the upper side of the second chip laminate body to thereby collectively permanently bond the two or more semiconductor chips.

Abstract: In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening.

Abstract: A semiconductor device of an embodiment includes a substrate, first, second, third, and fourth semiconductor elements, a first wiring layer, and first and second bonding wires. The third semiconductor element is on the substrate between the first resin element and the second resin element. The first wiring layer is on the first semiconductor element, is connected to the first semiconductor element, and is connected to the substrate by the first bonding wire. The fourth semiconductor element is on the first wiring layer and is connected to the first wiring layer by a second bonding wire. The first bonding wire is at a side of the first wiring layer other than a side farthest from the second wiring layer.

Abstract: Disclosed embodiments include a signal trace in an integrated-circuit device package substrate. Portions of the signal traces, suspend a landing pad in a recess, and a portion of the suspended signal trace is form-factor modulated that is different in cross-section area than other portions of the suspended signal trace.

Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.

Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protection layer encapsulating the semiconductor die. The chip package also includes a conductive structure in the protection layer and separated from the semiconductor die by the protection layer. The chip package further includes an interconnection structure over the conductive structure and the protection layer. The interconnection structure has a protruding portion between the conductive structure and the semiconductor die, and the protruding portion extends into the protection layer.

Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

Abstract: The present disclosure provides a semiconductor package, including a substrate, an active region in the substrate, an interconnecting layer over the active region, a conductive pad over the interconnecting layer, surrounded by a dielectric layer. At least two discrete regions of the conductive pad are free from coverage of the dielectric layer. A method of manufacturing the semiconductor package is also disclosed.

Abstract: The present disclosure, in some embodiments, relates to a bump structure. The bump structure includes a conductive layer and a solder layer. The solder layer is disposed vertically below and laterally between portions of the conductive layer along a cross-section. The conductive layer is continuous between the portions.

Abstract: A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure.

Abstract: A stacked semiconductor device is provided, which includes a first die, a second die and a heat dissipating layer. The first die has a pre-determined size. The second die is bonded to the first die using a dielectric material, wherein the second die is smaller than the first die. The heat dissipating layer is surrounding the second die, wherein the heat dissipating layer has an outer dimension that is equal to the size of the first die.

Abstract: Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.

Abstract: A carrier substrate includes a circuit structure layer, a first solder resist layer, a second solder resist layer and conductive towers. The circuit structure layer includes a core structure layer, a first circuit layer and a second circuit layer. The first solder resist layer has first openings exposing a portion of the first circuit layer. The second solder resist layer has second openings exposing a portion of the second circuit layer. The conductive towers are disposed at the first openings, higher than a surface of the first solder resist layer and connected with the first openings exposed by the first circuit layer, wherein a diameter of each of the conductive towers gradually increases by a direction from away-from the first openings towards close-to the first openings. A diameter of the second conductive towers is greater than that of the first conductive towers.

Abstract: A 3D stack includes a first chip having first interconnection pads of rectangular section, the first interconnection pads having a first pitch in a first direction and a second pitch in a second direction perpendicular to the first direction; and a second chip having second interconnection pads, the second interconnection pads having a third pitch in the first direction and a fourth pitch in the second direction, at least one part of the second interconnection pads being in contact with the first interconnection pads to electrically couple the first and second chips. The first interconnection pads have a first dimension in the first direction equal to m times the third pitch and a second dimension in the second direction equal to n times the fourth pitch. The first interconnection pads are separated two by two in the first direction by a first distance equal to q times the third pitch.

Abstract: An electronic device is provided. The electronic device includes a substrate, at least one contact pad disposed on the substrate, and a redistribution layer including a strip-shaped portion. The redistribution layer is electrically connected to the contact pad. The strip-shaped portion includes at least two strip-shaped steps, and each of the strip-shaped steps includes a plurality of peaks and valleys.

Abstract: A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

Abstract: A semiconductor packaging device includes a first patterned insulation layer, a patterned conductive layer, a semiconductor device and an encapsulant. The first patterned insulation layer has a first surface, a second surface opposite the first surface, and an island portion having the first surface. The first patterned insulation layer defines a tapered groove surrounding the island portion. The patterned conductive layer is disposed on the first surface of the island portion. The semiconductor device electrically connects to the patterned conductive layer. The encapsulant encapsulates the semiconductor device, the first patterned insulation layer and the patterned conductive layer.

Abstract: A method for hybrid wafer-to-wafer bonding, comprising: providing two silicon wafers with Cu pattern structures, a conventional Cu BEOL process is adopted on the silicon wafers to obtain the planarized surface with copper and dielectric; removing part of the Cu on the planarized surface of the Cu pattern structures by adopting an etching process to form a certain amount of Cu recesses; depositing a layer of bonding metal on the surface of the Cu by adopting a selective deposition process; performing surface activation on the bonding metal and the dielectric by adopting a surface activation process; aligning and pressing the two silicon wafers together to obtain the dielectric bonding; and obtaining the metal bonding through the annealing process.

Abstract: A semiconductor package structure includes at least one semiconductor die, at least one conductive pillar, an encapsulant and a circuit structure. The semiconductor die has an active surface. The conductive pillar is disposed adjacent to the active surface of the semiconductor die. The encapsulant covers the semiconductor die and the conductive pillar. The encapsulant defines at least one groove adjacent to and surrounding the conductive pillar. The circuit structure is electrically connected to the conductive pillar.

Abstract: A microelectronic structure includes a microelectronic substrate having a first surface and a cavity extending into the substrate from the microelectronic substrate first surface, a first microelectronic device and a second microelectronic device attached to the microelectronic substrate first surface, and a microelectronic bridge disposed within the microelectronic substrate cavity and attached to the first microelectronic device and to the second microelectronic device. In one embodiment, the microelectronic structure may include a reconstituted wafer formed from the first microelectronic device and the second microelectronic device. In another embodiment, a flux material may extend between the first microelectronic device and the microelectronic bridge and between the second microelectronic device and the microelectronic bridge.

Abstract: A method for manufacturing a semiconductor device includes: supplying a resist to a first surface of a semiconductor element having a plurality of electrode pads to cover the electrode pad surfaces; opening the resist on the electrode pad surfaces to expose the electrode pad surfaces from the resist; curing the resist by applying light or heat to the resist; forming bump electrodes on the electrode pad surfaces by filling a plating solution into the openings of the resist; and peeling the resist from the first surface of the semiconductor element.

Abstract: A method of manufacturing a package structure includes the following processes. An adhesive layer is formed on a carrier. A die is attached to the carrier through the adhesive layer. A protection layer is formed to at least cover a sidewall and a portion of a top surface of the adhesive layer on an edge of the carrier. An encapsulant is formed over the carrier to laterally encapsulate the die. A redistribution layer (RDL) structure is formed on the die and the encapsulant. A connector is formed to electrically connect to the die through the RDL structure. The carrier is released.

Abstract: Methods of forming supports for 3D structures on semiconductor structures comprise forming the supports from photodefinable materials by deposition, selective exposure and curing. Semiconductor dice including 3D structures having associated supports, and semiconductor devices are also disclosed.