Abstract: A multilayer flexible wiring board, suited for mounting semiconductor elements. The flexible wiring board is fabricated in the following manner. A flexible wiring board piece having a metal wiring, in which a metal coating is exposed on at least a part of surface of the metal wiring, is adhered to another flexible wiring board piece having a metal projection on which a metal coating is formed. One of or both of the metal coatings on the metal wiring and the metal projection is composed of a soft metal coating a surface of which has a Vickers' hardness of 80 kgf/mm2 or lower. The metal coating of the metal wiring contacts with the metal coating of said metal projection and ultrasonic wave is applied thereto to connect the metal wiring with the metal projection.

Abstract: Disclosed is a layer to electrically connect targets during a circuit edit of an integrated circuit and systems and methods for forming the layer. The layer contains a conductive material, such as gold or another metal, which has been physically deposited by sputtering, thermal evaporation, and other physical deposition technique.

Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.

Abstract: A tungsten nucleation film is formed on a surface of a semiconductor substrate by alternatively providing to that surface, reducing gases and tungsten-containing gases. Each cycle of the method provides for one or more monolayers of the tungsten film. The film is conformal and has improved step coverage, even for a high aspect ratio contact hole.

Abstract: A microelectronic semiconductor interconnect structure barrier and method of deposition provide improved conductive barrier material properties for high-performance device interconnects. The barrier includes a refractory metal such as cobalt, cobalt-based alloys, ruthenium or ruthenium-based alloys for promoting adhesion of copper. The barrier materials can be deposited by chemical-vapor deposition to achieve good step coverage and a relatively conformal thin film with a good nucleation surface for subsequent metallization such as copper metallization. In one embodiment, the barrier suppresses diffusion of copper into other layers of the device, including the inter-metal dielectric, pre-metal dielectric, and transistor structures.

Abstract: A semiconductor device includes a middle inter-level insulating film disposed on or above a semiconductor substrate, a conductive layer disposed on the middle inter-level insulating film, and an upper inter-level insulating film disposed on the middle inter-level insulating film and the conductive layer. The upper inter-level insulating film includes first, second, and third wiring grooves distant from each other. The second and third wiring grooves use the conductive layer as their bottoms. The side surfaces of the first, second, and third wiring grooves are covered with in-groove barrier layers. First, second, and third wiring layers are buried in the first, second, and third wiring grooves. The first, second, and third wiring layers are derived from the same wiring film, and have a thickness larger than that of the conductive layer. The second and third wiring layers are electrically connected to the conductive layer.

Abstract: The invention includes a method of fabricating a circuit in a manner to place certain structures within a predefined distance of one another. Electrical connections are formed between certain structures of silicon, by annealing a conductive material to cause silicon out-diffusing to form local interconnects. The silicon out-diffusion can be facilitated without a masking step thereby simplifying as well as speeding up the fabrication process. The invention also includes a local interconnect thus formed.

Abstract: A method of manufacturing integrated circuits using a thin metal oxide film as a seed layer for building multilevel interconnects structures in integrated circuits. Thin layer metal oxide films are deposited on a wafer, and standard optical lithography is used to expose the metal oxide film in a pattern corresponding to a metal line pattern. The metal oxide film is converted to a layer of metal, and a metal film may then be deposited on the converted oxide film by either selective CVD or electroless plating. Via holes are then fabricated in a similar process using via hole lithography. The process is continued until the desired multilevel structure is fabricated.

Abstract: To provide excellent reliability and high yield of a semiconductor device that has a multi-wiring structure by using a fluorine-containing silicon oxide film as an interlayer insulating film. A fluorine-containing silicon oxide film is formed so as to cover a lower layer metal wiring. A TEOS film is formed on the fluorine-containing silicon oxide film. After planarizing the TEOS film with the CMP method, an SiH4-based silicon oxide film that is suitable for capturing fluorine is formed on the TEOS film. Metal wirings are formed on the SiH4-based silicon oxide film. A predetermined heat treatment is performed to capture fluorine inside the SiH4-based silicon oxide film. The SiH4-based silicon oxide film is patterned to the same pattern as the metal wirings. After diffusing fluorine into the atmosphere from the exposed area of the TEOS film, a silicon nitride film is formed on the metal wirings.

Abstract: The present invention relates to a semiconductor structure including metal nitride and metal silicide, where a metal silicide layer is formed upon an active area that is part of a junction in order to facilitate further miniaturization that is demanded and dictated by the need for smaller devices. A single PECVD process makes three distinct depositions. First, a metal silicide forms by the reaction: MHal+Si+H2MSix+HHal, where M represents a metal and Hal represents a preferred halogen or the like. Second, a metal nitride forms upon areas not containing Si by the reaction: MHal+N2+H2MN+HHal. Third, a metal nitride forms upon areas of evolving metal silicide due to a diffusion barrier effect that makes formation of the metal silicide self limiting. Ultimately, a metal nitride layer will be uniformly disposed in a substantially uniform composition covering all underlying structures upon a semiconductor substrate.

Abstract: The use of an intermetal dielectric (IMD) layer and an organic etch-stop layer are disclosed in forming a dual damascene in order to reduce the RC delay and the overall dielectric constant of the damascene interconnect. The disclosed IMD layer is an FSG and the etch-stop layer is an organic spin-on-glass (SOG). A dual damascene structure utilizing the IMD layer and the organic etch-stop layer is also disclosed.

Abstract: An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film effectively prevents oxygen diffusion, and is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from oxidizing the same variety of M transition metals, the resulting conductive barrier also suppresses the diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. The Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile MFMIS (metal/ferro/metal/insulator/silicon) memory devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, and piezoelectric transducers.

Abstract: A novel, high performance, high reliability interconnection structure for an integrated circuit. The interconnection structure of the present invention is formed on a first insulating layer which in turn is formed on a silicon substrate or well. A first multilayer interconnection comprising a first aluminum layer, a first refractory metal layer, and a second aluminum layer is formed on the first insulating layer. A second insulating layer is formed over the first multilayer interconnection. A conductive via is formed through the second insulating layer and recessed into the first multilayer interconnection wherein a portion of the via extends above the second insulating layer. A second interconnection is formed on the second insulating layer and on and around the portion of the via extending above the second insulating layer.

Abstract: A semiconductor device having a contact layer and a diffusion barrier layer is fabricated by preparing a semiconductor substrate, forming a layer of titanium/aluminum alloy on the surface of the substrate, and then heating the resultant structure in a nitrogen ambient to form a contact layer of titanium silicide interposed between the substrate and a diffusion barrier layer consisting of titanium/aluminum/nitride.

Abstract: Integrated circuit interconnect alloys having copper, silver or gold as the major constituent element. The resulting reduction in melting temperature allows for improved coverage of high aspect ratio features with reduced deposition pressure. The alloys are used to fabricate interconnects in integrated circuits, such as memory devices. The interconnects can be high aspect ratio features formed using a dual damascene process. The integrated circuits having the interconnects are applicable to semiconductor dies, devices, modules and systems.

Abstract: A thermoelectric device that realizes miniaturization and densification, an optical module incorporating the thermoelectric device, and their production method. N-type thermoelectric elements 51 and p-type thermoelectric elements 52 are arranged orthogonally and alternately, on the XY-plane, in a matrix consisting of at least four elements in total in a row and at least four elements in total in a column. All the thermoelectric elements 51 and 52 have a size of at most 250 &mgr;m in the X and Y directions. At most four thermoelectric elements nearest to an n-type thermoelectric element 51 are of p type, and at most four thermoelectric elements nearest to a p-type thermoelectric element 52 are of n type. The thermoelectric elements 51 and 52 are bonded through metallic bonding materials to electrodes 53 having the shape of a rectangle or a rounded rectangle formed on an insulating substrate 54.

Abstract: An integrated circuit device, and a method of manufacturing the same, comprises an epitaxial nickel silicide on (100) Si, or a stable nickel silicide on amorphous Si, fabricated with a cobalt interlayer. In one embodiment the method comprises depositing a cobalt (Co) interface layer between the Ni and Si layers prior to the silicidation reaction. The cobalt interlayer regulates the flux of the Ni atoms through the cobalt/nickel/silicon alloy layer formed from the reaction of the cobalt interlayer with the nickel and the silicon so that the Ni atoms reach the Si interface at a similar rate, i.e., without any orientation preference, so as to form a uniform layer of nickel silicide. The nickel silicide may be annealed to form a uniform crystalline nickel disilicide. Accordingly, a single crystal nickel silicide on (100) Si or on amorphous Si is achieved wherein the nickel silicide has improved stability and may be utilized in ultra-shallow junction devices.

Abstract: A high aspect ratio contact structure using a metal silicide adhesion layer that is interposed between titanium and titanium nitride (TiN) to promote adhesion of TiN to Ti. The metal silicide adhesion layer created from silicon doped CVD Ti can be deposited over the unreacted Ti after the silicidation reaction or deposited directly on the silicon substrate in place of CVD Ti. The contact structure further includes contact fill that is comprised of TiCl4 based TiN, which affords improved step coverage in the contact structure.

Abstract: The present invention provides methods of forming local interconnect structures for integrated circuits. A representative embodiment includes depositing a silicon source layer over a substrate having at least one topographical structure thereon. The silicon source layer preferably comprising silicon rich silicon nitride, silicon oxynitride or other silicon source having sufficient free silicon to form a silicide but not so much free silicon as to result in formation of stringers (i.e., does not comprise polysilicon). The silicon source layer is preferably deposited over an active area in the substrate and at least a portion of the topographical structure. A silicide forming material, e.g., a refractory metal, is deposited directly on selected regions of the silicon source layer and over the topographical structure. A silicide layer is made from the silicide forming material and the silicon source layer preferably by annealing the structure.

Abstract: In a semiconductor device, a CoSi2 film is interposed between a pluglike contact and a barrier metal film as a silicide film. Consequently, excess reaction can be suppressed on a Ti/polysilicon interface between the pluglike contact or a pluglike local wire and the barrier metal film for stably lowering contact resistance.

Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented, after silicidation and removal of any unreacted nickel, by treating the exposed surfaces of the silicon nitride sidewall spacers with a HDP plasma to oxidize nickel silicide thereon forming a surface layer comprising silicoin oxide and silicon oxynitride. Embodiments include treating the silicon nitride sidewall spacers with a HDP plasma to form a surface silicon oxide/silicon oxynitride region having a thickness of about 40 Å to about 50 Å.

Abstract: Low resistivity, C54-phase TiSi2 is formed in narrow lines on heavily doped polysilicon by depositing a bi-layer silicon film. A thin, undoped amorphous layer is deposited on top of a heavily doped layer. The thickness of the undoped amorphous Si is about 2.4 times the thickness of the subsequently deposited Ti film. Upon thermal annealing above 750° C., the undoped amorphous Si is consumed by the reaction of Ti+Si to form TiSi2, forming a low-resistivity, C54-phase TiSi2 film on top of heavily doped polysilicon. The annealing temperature required to form C54 phase TiSi2 is reduced by consuming undoped amorphous Si in the reaction of Ti and Si, as compared with heavily doped polysilicon. Narrow lines (<0.3 &mgr;m) of low-resistivity, C54-phase TiSi2 films on heavily doped polysilicon are thus achieved.

Abstract: A leadframe for use with integrated circuit chips, comprising a leadframe base made of aluminum or aluminum alloy having a surface layer of zinc; a first layer of nickel on said zinc layer, said first nickel layer deposited to be compatible with aluminum and zinc; a layer of an alloy of nickel and a noble metal on said first nickel layer; a second layer of nickel on said alloy layer, said second nickel layer deposited to be suitable for lead bending and solder attachment; and an outermost layer of noble metal, whereby said leadframe is suitable for solder attachment to other parts, for wire bonding, and for corrosion protection.

Abstract: An apparatus including a circuit of n circuit levels formed over a substrate from a first level to a nth level, wherein n is greater than one, and each of the n circuit levels has a material parameter change that is at least in part caused by a thermal processing operation that is applied to more than one of the n circuit levels simultaneously. An apparatus including a circuit of a plurality of circuit levels, each of the plurality of circuit levels having substantially similar material parameters.

Abstract: This invention provides a semiconductor device comprising gate insulating films 13, 21 formed on the main surface of a silicon substrate 11; gate electrodes 14, 22 consisting of polycrystalline silicon; and a high-density doped layer 17, wherein a part of the side of the gate electrode 22 is electrically connected with the high-density doped layer via a metal silicide layer 23.

Abstract: A CVD source material which can be stably tramsported to a reactor in order to form a platinum metal, Cu, or an oxide of them as an electrode. An organometallic compound including a platinum metal (Ru, Pt, Ir, Pd, Os, Rh, Re) or Cu, is dissolved into tetrahydrofuran or a solvent containing tetrahydrofuran to obtain the CVD source material. In this material, the amount of moisture is preferably not more than 200 ppm. A film is formed by CVD employing this source material, the material is supplied stably, and the properties of the electrode film are improved. The capacitance property of the film is improved. Wiring of an electrical device may be formed by employing source material.

Abstract: A contact interface having a substantially continuous profile along a bottom and lower sides of the active surface of the semiconductor substrate formed within a contact opening. The contact interface is formed by depositing a layer of conductive material, such as titanium, using both a high bias deposition and a low bias deposition. The high bias and low bias deposition may be effected as a two-step deposition or may be accomplished by changing the bias from a high level to a low level during deposition, or vice versa. The conductive material is converted to a silicide by an annealing process to form the contact interface.

Abstract: Wiring for a semiconductor device which is suitable for high density device packing, and a method for forming the same, are disclosed. The wiring includes: impurity regions formed in a substrate on both sides of an insulated gate electrode; a first conduction layer formed on the impurity regions; and a second conduction layer formed in contact with the first conduction layer on one side of the gate electrode. The method includes the steps of: forming impurity regions in a substrate on both sides of an insulated gate electrode; forming a first conduction layer on the impurity regions; and forming a second conduction layer in contact on one side of the gate electrode with the first conduction layer.

Abstract: In one aspect, the present invention discloses a transistor device (see e.g., FIG. 3) that includes first and second source/drain regions 124a and 126 disposed in a semiconductor body 122 and separated by a channel region 128a. A dielectric layer 134a overlies the channel region 128a and a gate electrode 130a/132a overlies the dielectric layer 134a. In the preferred embodiment, the gate electrode includes a polysilicon layer 130a that extends a first lateral distance over the dielectric layer and a silicide layer 132a that extends a second lateral distance over the first polysilicon layer. In this example, the first lateral distance is greater than the second lateral distance.

Abstract: An electrode substrate comprises a backing substrate carrying thereon a metal electrode layer and/or a recording layer, the layer or layers having a smooth surface area with a surface roughness of less than 1 nm by more than 1 &mgr;m2. The smooth surface of the metal electrode layer and/or the recording layer is formed by firstly forming the layer on another substrate having a corresponding smooth surface and then peeling the another substrate off the layer after the layer is bonded to the surface of the backing substrate, whereby the smooth surface profile of the another substrate is transferred to the surface of the layer formed on the backing substrate.

Abstract: The present invention provides a semiconductor device which can prevent the oxidization of the surfaces of pad electrodes to enhance the connecting strength between the pad electrodes and external terminals. The semiconductor device according to the present invention comprises pad electrodes for use in connecting external electrodes and a multilayer wiring structure connected to the pad electrodes, wherein one surface of an insulating layer covering the pad electrodes and having openings over the pad electrodes for exposing the surfaces of the pad electrodes is in contact with a metal layer. formed from one selected from precious metals and alloys containing the precious metals as main components.

Abstract: A method is provided for forming a contact in an integrated circuit by chemical vapor deposition (CVD). In one embodiment, a titanium precursor and a silicon precursor are contacted in the presence of hydrogen, to form titanium silicide. In another embodiment, a titanium precursor contacts silicon to form to form titanium silicide.

Abstract: A new method and structure for an improved contact using doped silicon is provided. The structures are integrated into several higher level embodiments. The improved contact has low contact resistivity. Improved junctions are thus provided between an IGFET device and subsequent metallization layers. The improvements are obtained through the use of a silicon-germanium (Si—Ge) alloy. The alloy can be formed from depositing germanium onto the substrate and subsequently annealing the contact or by selectively depositing the preformed alloy into a contact opening. The above advantages are incorporated with relatively few process steps.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures include a bottom conductive layer, a top conductive layer and a dielectric layer interposed between the bottom conductive layer and the top conductive layer. The container structures further include a diffusion barrier layer interposed between the dielectric layer and the bottom conductive layer. The diffusion barrier layer acts to inhibit atomic diffusion to at least a portion of the bottom conductive layer, particularly atomic diffusion of oxygen during formation or annealing of the dielectric layer. The container structures are especially adapted for use as container capacitors. The container capacitors are further adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: An integrated circuit and manufacturing method therefor is provided for an integrated circuit on a semiconductor substrate grated circuit having a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening, and a first conductor core fills the opening over the barrier layer. A second dielectric layer is formed on the first dielectric layer and has a second channel and via opening provided therein. A shunt layer is in the via opening above the conductor core. A barrier layer lines the second channel and via opening over the shunt layer and the second dielectric layer. A conductor core fills the second channel and via opening over the barrier layer and the first conductor core to form the second channel and via.

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

Abstract: A first cathode flange (14) provided with branch-like protrusions (14d) extending towards substantially its outer periphery and a gate flange (15) provided with branch-like protrusions (15c) extending towards substantially its outer periphery are connected to a cathode electrode (7a) and a gate electrode (7b), respectively, formed on one surface of a gate drive substrate (7). With this structure, a gate commutated turn-off semiconductor device which eliminates the necessity of a gate spacer and a cathode spacer and allows reduction in time and cost required for manufacture can be achieved.

Abstract: An interconnect structure and barrier layer for electrical interconnections is described incorporating a layer of TaN in the hexagonal phase between a first material such as Cu and a second material such as Al, W, and PbSn. A multilayer of TaN in the hexagonal phase and Ta in the alpha phase is also described as a barrier layer. The invention overcomes the problem of Cu diffusion into materials desired to be isolated during temperature anneal at 500° C.

Abstract: Integrated circuit contact structures are fabricated by forming a first layer comprising niobium (Nb) on a silicon substrate and forming a second layer comprising a near noble metal on the first layer, opposite the silicon substrate. The near noble metal, also referred to as a Group VIII metal, is preferably cobalt (Co). The near noble metal has higher diffusion coefficient than the niobium and the silicon substrate. Annealing is then performed to diffuse at least some of the near noble metal through the first layer and react the diffused near noble metal with the silicon substrate to form a third layer comprising a near noble metal silicide, and to form a fourth layer comprising niobium-near noble metal alloy on the third layer. It has been found that the use of niobium can reduce substrate consumption compared to conventional cobalt titanium double-metal silicide fabrication processes.

Abstract: Structures within semiconductor devices having a titanium alloy layer are provided. The titanium alloy layer is formed through chemical vapor deposition by combining a first precursor with a reducing agent to form a seed layer, and by combining a second precursor with the seed layer to form the titanium alloy layer. Structures are described having a titanium alloy layer on sidewalls and an exposed base layer of a contact hole. Structures are further described having a titanium alloy layer on sidewalls of a contact hole and a titanium silicide layer on an exposed base layer of the contact hole. The structures are useful as device contacts to active areas of a semiconductor device, and as interlevel vias within semiconductor integrated circuits.

Abstract: A method for forming an aluminum contact through an insulating layer includes the formation of an opening. A barrier layer is formed, if necessary, over the insulating layer and in the opening. A thin refractory metal layer is then formed over the barrier layer, and aluminum deposited over the refractory metal layer. Proper selection of the refractory metal layer and aluminum deposition conditions allows the aluminum to flow into the contact and completely fill it. Preferably, the aluminum is deposited over the refractory metal layer without breaking vacuum.

Abstract: An integrated circuit, comprising: a semiconductor substrate, a plurality of last metal conductors disposed above said substrate, a bottom metallic layer disposed on said last metal conductors, a top metallic layer, and an alpha absorber disposed between said bottom and top metallic layers, said alpha absorber consisting essentially of a high-purity metal which is an alpha-particle absorber. The metal is, for example, of Ta, W, Re, Os or Ir.

Abstract: A method of forming a connection is comprised of the steps of depositing a lower conductor. A dielectric layer is deposited on the lower conductor, with the dielectric layer having a lower surface adjacent to the lower conductor, and having an upper surface. An opening extending between the upper surface and the lower surface of the dielectric layer is formed. A conductive plug is deposited within the opening, with the plug having an upper surface proximate the upper surface of the dielectric layer. The upper surface has an edge where the upper surface of the plug is adjacent to the dielectric layer. A recess is formed proximate to the edge of the upper surface of the plug, the recess extending into both the plug and the dielectric layer. Finally, an upper conductor is deposited on the upper surface of the dielectric layer and the upper surface of the plug. A connection thus formed is also disclosed.

Abstract: A semiconductor device includes a semiconductor substrate having a device element, an interlayer dielectric layer (silicon oxide layer, BPSG layer) formed on the semiconductor substrate, a through hole defined in the interlayer dielectric layer, a barrier layer formed on surfaces of the interlayer dielectric layer and the through hole, and a wiring layer formed on the barrier layer. The barrier layer includes a first metal oxide layer formed from an oxide of a metal that forms the barrier layer (e.g., a first titanium oxide layer), a metal nitride layer formed from a nitride of the metal that forms the barrier layer (e.g., a titanium nitride layer), and a second metal oxide layer formed from an oxide of the metal that forms the barrier layer (e.g., a second titanium oxide layer). The semiconductor device thus manufactured has a barrier layer of an excellent barrier capability.

Abstract: In one aspect, the invention provides a method of forming an integrated circuitry memory device. In one preferred implementation, a conductive layer is formed over both memory array areas and peripheral circuitry areas. A refractory metal layer is formed over the conductive layer to provide conductive structure in both areas. According to a preferred aspect of this implementation, the conductive layer which is formed over the memory array provides an electrical contact for a capacitor container to be formed. According to another preferred aspect of this implementation, the conductive layer formed over the peripheral circuitry area constitutes a conductive line which includes at least some of the silicide. In another preferred implementation, the invention provides a method of forming a capacitor container over a substrate. According to a preferred aspect of this implementation, a conductive layer is elevationally interposed between an upper insulating layer and a lower conductive layer over the substrate.

Abstract: A method of constructing a conductive via spacer within a dielectric layer located between a first metal layer and a second metal layer includes the steps of depositing a conductive spacer layer within the opening and over the first metal layer. A portion of the conductive spacer layer is removed to leave a conductive spacer within the opening. The second metal layer is deposited over the spacer to complete the connection between the first and second metal layers. The spacer preferably comprises a material selected from the group comprising refractory metal silicides and nitrides. The spacer is preferably tapered and the via may include a glue layer to improve the adherence of the spacer to the dielectric layer.

Abstract: A conductive contact having an atomically flat interface. The contact includes, in order, a silicon substrate, a highly disordered silicide layer, and a titanium oxynitride layer. The silicide layer is formed of titanium, silicon, and one of the elements tungsten, tantalum, and molybdenum. The interface between the silicon substrate and the silicide layer is atomically flat. The flat interface prevents diffusion of conductive materials into the underlying silicon substrate. The contact is useful especially for very small devices and shallow junctions, such as are required for ULSI shallow junctions.

Abstract: A method of forming a refractory metal nitride layer for integrated circuit fabrication is disclosed. In one embodiment, the refractory metal nitride layer is formed by chemisorbing monolayers of a hydrazine-based compound and one or more refractory metal compounds onto a substrate. In an alternate embodiment, the refractory metal nitride layer has a composite structure, which is composed of two or more refractory metals. The composite refractory metal nitride layer is formed by sequentially chemisorbing monolayers of a hydrazine-based compound and two or more refractory metal compounds on a substrate.

Abstract: A new n-type semiconducting diamond is disclosed, which is doped with n-type dopant atoms. Such diamond is advantageously formed by chemical vapor deposition from a source gas mixture comprising a carbon source compound for the diamond, and a volatile hot wire filament for the n-type impurity species, so that the n-type impurity atoms are doped in the diamond during its formation. A corresponding chemical vapor deposition method of forming the n-type semiconducting diamond is disclosed. The n-type semiconducting diamond of the invention may be usefully employed in the formation of diamond-based transistor devices comprising pn diamond junctions, and in other microelectronic device applications.

Abstract: A method for forming a platen useful for forming nanoscale wires for device applications comprises: (a) providing a substrate having a major surface; (b) forming a plurality of alternating layers of two dissimilar materials on the substrate to form a stack having a major surface parallel to that of the substrate; (c) cleaving the stack normal to its major surface to expose the plurality of alternating layers; and (d) etching the exposed plurality of alternating layers to a chosen depth using an etchant that etches one material at a different rate than the other material to thereby provide the surface with extensive strips of indentations and form the platen useful for molding masters for nano-imprinting technology. The pattern of the platen is then imprinted into a substrate comprising a softer material to form a negative of the pattern, which is then used in further processing to form nanowires.