Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a base substrate having a bottom pad; an integrated circuit device mounted on the base substrate; an interposer having a package interconnect mounted on the base substrate, the package interconnect includes an underside base portion having an irregular surface characteristic of a coining process; and an encapsulation between the interposer and the base substrate.

Abstract: An encapsulating sheet is formed from an encapsulating resin composition which contains an encapsulating resin and silicone microparticles, and the mixing ratio of the silicone microparticles with respect to the encapsulating resin composition is 20 to 50 mass %.

Abstract: An encapsulating sheet is formed from an encapsulating resin composition which contains an encapsulating resin and silicone microparticles, and the mixing ratio of the silicone microparticles with respect to the encapsulating resin composition is 20 to 50 mass %.

Abstract: Provided are a thin circuit device with show-through of thin metal wires prevented and a method of manufacturing the circuit device. A circuit device mainly includes: a substrate including a first substrate and second substrates; pads formed respectively on upper surfaces of the second substrates; a semiconductor element fixed on an upper surface of the first substrate; thin metal wires each connecting the semiconductor elements and a corresponding one of the pads; and a sealing resin with which the semiconductor element and the thin metal wires are covered, and which thereby seals the circuit device with the semiconductor element and the thin metal wires disposed therein. Furthermore, filler particles located in the uppermost portion of the sealing resin are covered with a resin material constituting the sealing resin.

Abstract: Set of compositions for preparing system-in-package type semiconductor device. The composition set consists of underfill composition for preparing underfill part and encapsulation resin composition for preparing resin encapsulation part. 1) A cured product of the underfill composition has a glass transition temperature, Tg, ?100° C. and is the same with or differs from a Tg of a cured product of the encapsulation resin composition by ?20° C. 2) Total linear expansion coefficient of the cured product of the underfill composition at a temperature not higher than (Tg?30)° C. and a linear expansion coefficient of the cured product of the encapsulation resin composition at a temperature not higher than (Tg?30)° C. is ?42 ppm/° C. 3) A ratio of the linear expansion coefficient of the cured product of the encapsulation resin composition to the linear expansion coefficient of the cured product of the underfill composition ranges from 0.3 to 1.0.

Abstract: A method for fabricating a packaging structure having an embedded semiconductor element includes: providing a substrate having opposite first and second surfaces and at least an opening penetrating the first and second surfaces; forming a first metallic frame around the periphery of the opening on the first surface; forming at least an opening inside the first metallic frame by laser ablation; disposing a semiconductor chip in the opening; forming a first dielectric layer on the first and second surfaces and the chip; forming a first wiring layer on the first dielectric layer of the first surface; and forming a first built-up structure on the first dielectric layer and the first wiring layer of the first surface. A shape of the opening is precisely controlled through the first metallic frame around the periphery of the predefined opening region, thereby allowing the chip to be precisely embedded in the substrate.

Abstract: A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding.

Abstract: An epoxy resin composition for encapsulating a semiconductor device includes a curing agent, a curing accelerator, inorganic fillers, and an epoxy resin, the epoxy resin including a first resin represented by Formula 1: wherein R1 and R2 are each independently hydrogen or a C1 to C4 linear or branched alkyl group, and n is a value from 1 to 9 on average.

Abstract: A thermosetting encapsulation adhesive sheet which is used for encapsulating a chip type device (1) having connection electrodes (bumps) (3) and mounted on a wiring circuit board (2). The thermosetting encapsulation adhesive sheet is composed of an epoxy resin composition having a viscosity of 5×104 to 5×106 Pa·s as measured at a temperature of 80 to 120° C. before thermosetting thereof. The thermosetting encapsulation adhesive sheet makes it possible to conveniently encapsulate a hollow device with an improved yield.

Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit, having a device through via and a device interconnect, over a substrate with the device through via traversing the integrated circuit and the device interconnect attached to the device through via; attaching a conductive support over the substrate with the conductive support adjacent to the integrated circuit; providing a pre-formed interposer, having an interposer through via and a pre-attached interconnect, with the pre-attached interconnect attached to the interposer through via; mounting the pre-formed interposer over the integrated circuit and the conductive support with the pre-attached interconnect over the device through via; and forming an encapsulation over the substrate covering the integrated circuit, the conductive support, and partially covering the pre-formed interposer.

Abstract: A semiconductor device and a method for making a semiconductor device are disclosed. In an embodiment a semiconductor device includes a semiconductor chip and a fiber reinforced encapsulation layer at least partly covering the semiconductor chip.

Abstract: A method of manufacturing a MEMS device comprises forming a MEMS device element (12). A sidewall (20) is formed around the MEMS device element, and a sacrificial layer (14) is formed over the device element and within the sidewall. A package cover layer (16) is provided over the sacrificial layer, and the sacrificial layer is removed. This method provides additional sidewalls to the cap provided over the MEMS device. These additional sidewalls can then be deposited by a different process and be formed of a different material to the top part of the package cover layer. The sidewalls can prevent reflow of the sacrificial layer and improve the sealing properties of the sidewalls.

Abstract: Thermosetting resin compositions with low coefficient of thermal expansion are provided herein.

Abstract: A method of manufacturing a device includes forming a covering layer having affinity for a filler to be injected into a space between a first base and a second base, on at least one of the opposing surfaces of the first base and the second base, and then injecting the filler into the space between the first base and the second base.

Abstract: An integrated circuit is provided. The integrated circuit includes: a chip and encapsulation material covering at least three sides of the chip, the encapsulation material being formed from adhesive material. The integrated circuit includes a carrier adhered to the chip by means of the encapsulation material.

Abstract: An electronic component includes a unit including an electronic device; and an opposite member opposing the electronic device, wherein the unit and the opposite member are bonded together with an adhering member disposed between the unit and the opposite member and having light-cured resin and inorganic particles dispersed in the light-cured resin; and wherein in a particle-diameter distribution of the inorganic particles by volume, a particle diameter having a cumulative value of distribution of 50 is 0.5 ?m or more, and a particle diameter having a cumulative value of distribution of 90% is 5.0 ?m or less.

Abstract: Electrical components such as integrated circuits may be mounted on a printed circuit board. To prevent the electrical components from being subjected to electromagnetic interference, radio-frequency shielding structures may be formed over the components. The radio-frequency shielding structures may be formed from a layer of metallic paint. Components may be covered by a layer of dielectric. Channels may be formed in the dielectric between blocks of circuitry. The metallic paint may be used to coat the surfaces of the dielectric and to fill the channels. Openings may be formed in the surface of the metallic paint to separate radio-frequency shields from each other. Conductive traces on the surface of the printed circuit board may be used in connecting the metallic paint layer to internal printed circuit board traces.

Abstract: According to the present invention, an epoxy resin composition for semiconductor encapsulant including (A) an epoxy resin, (B) a curing agent, (C) an inorganic filler, and (D) a compound in which a copolymer of a 1-alkene having 5 to 80 carbon atoms and maleic anhydride is esterified with an alcohol having 5 to 25 carbon atoms in the presence of a compound represented by General Formula (1), wherein R1 in General Formula (1) is selected from the group consisting of an alkyl group having 1 to 5 carbon atoms, a halogenated alkyl group having 1 to 5 carbon atoms, and an aromatic group having 6 to 10 carbon atoms is provided.

Abstract: An embodiment is directed to a polysiloxane having a moiety represented by the following Chemical Formula 1: *—Si-AR—Si—*??[Chemical Formula 1] wherein, in the Chemical Formula 1, AR is or includes a substituted or unsubstituted C6 to C30 arylene group.

Abstract: A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill.

Abstract: A semiconductor device includes a carrier and a first chip attached to the carrier. The semiconductor device includes a sintered insulation material over at least a portion of the carrier and the first chip.

Abstract: A semiconductor encapsulation material which exhibits a low viscosity and further improved moldability in encapsulation even when highly loaded with an inorganic filler; an amorphous siliceous powder suitable for the preparation of a resin composition useful as the encapsulation material; and a process for the production of the amorphous siliceous powder. An amorphous siliceous powder having a content of Si and Al of 99.5 mass % or above in terms of oxides, wherein the Al content in the particle size region of 15 ?m to less than 70 ?m is 100 to 30000 ppm in terms of oxides; the Al content in the particle size region of 3 ?m to less than 15 ?m is 100 to 7000 ppm in terms of oxides; and the Al content in the whole particle size region is 100 to 25000 ppm in terms of oxides. It is preferable that the (A)/(B) ratio of the Al content (A) in the particle size region of 15 ?m to less than 70 ?m to the Al content (B) in the particle size region of 3 ?m to less than 15 ?m be 1.0 to 20.

Abstract: A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. The flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer.

Abstract: A sheet of material includes a layer of the insulative thermoplastic material such as PET (poly(ethylene terephthalate)). The sheet is placed down over the wirebonds and a semiconductor die of a substrate assembly so that the sheet contacts the wirebonds and/or the semiconductor die. In one example, the sheet is a preform and the bottom of the sheet includes a layer of tacky adhesive that adheres the sheet to the substrate assembly. The sheet is then heated such that the PET softens and becomes conformal to the wirebonds and the semiconductor die of the upper surface of the substrate assembly. The resulting encapsulated substrate assembly is then encapsulated (for example, by overmolding in an injection molding process) to form a packaged semiconductor device. The conformal PET sheet is embedded within the packaged semiconductor device in such a way that it separates the wirebonds and semiconductor die from another encapsulant.

Abstract: A semiconductor device includes a semiconductor chip, an electrode pad formed on the semiconductor chip, an underlying barrier metal formed on the electrode pad, a solder bump formed on the underlying barrier metal, and an underfill material surrounding the underlying barrier metal and the solder bump. A junction interface of the solder bump with the underlying barrier metal corresponds to an upper surface of the underlying barrier metal, and a portion of the underfill material bonded to a side surface of the solder bump and an end surface of the underlying barrier metal forms a right angle or an obtuse angle.

Abstract: A method for producing a semiconductor chip laminate, which comprises applying an adhesive to a substrate or other semiconductor chip; laminating the semiconductor chip on the substrate or other semiconductor chip via the adhesive; uniformly wetting and spreading the adhesive on an entire region for bonding the semiconductor chip on the substrate or other semiconductor chip; and curing the adhesive. In the application step, an area for applying adhesive is 40% to 90% of the region for bonding the semiconductor chip located on the substrate or other semiconductor chip, immediately after laminating, an area with the adhesive thereon is 60% to less than 100% of the region for bonding the semiconductor chip on the substrate or other semiconductor chip, and in wetting and spreading the adhesive, a viscosity of adhesive between the substrate or other semiconductor chips and the semiconductor chip at 0.5 rpm is 1 Pas to 30 Pas.

Abstract: A manufacturing method of a semiconductor device includes: sealing a semiconductor chip with a sealing resin containing a filler; exposing a part of the filler; etching at least a part of the exposed filler; and forming a metal film at least at a part of a surface of the sealing resin including inner surfaces of holes formed at the surface of the sealing resin by the etching.

Abstract: A method of fabricating a chip package is provided. The chip package includes a laminate, a chip and conductive elements interposed between the chip and the laminate by which signals are transmitted among the chip and the laminate. The method includes dispensing a first underfill in a space defined between opposing faces of the chip and the laminate and dispensing a second underfill at least at a portion of an edge of the chip, the second underfill including a high aspect ratio material.

Abstract: An insulating member of the invention can include an epoxy resin, a first inorganic filler diffused in the epoxy resin and having an average particle diameter of 1 to 99 nm, and a second inorganic filler diffused in the epoxy resin and having an average particle diameter of 0.1 to 100 ?m. The first and second inorganic fillers can be independent of each other, and can be selected from a group including Al2O3, SiO2, BN, AlN, and Si3N4, and the blending ratios of the first and second inorganic fillers in the insulating member can be 0.1 to 7% by weight and 80 to 95% by weight respectively. A metal base substrate can be formed by forming a metal foil and a metal base on either surface of the insulating member.

Abstract: The invention relates to a module package which comprises a module substrate 1, a chip 2, 3 applied using the flip chip process, and an encapsulation layer 8, and to a method for producing same. The chip 2, 3 has component structures on the top side 13, 14 thereof. Said top said 13, 14 faces the module carrier 1, wherein a gap 4, 5 is formed between the top side 13, 14 of the chip and the module carrier 1. A filler is added to the encapsulation layer 8. The encapsulation layer 8 partly fills underneath the chip 2, 3, wherein at most the part of the chip 2, 3, on which no component structures are present, is underfilled, and at a minimum the material of the encapsulation layer 8 completely encloses the sides of the chip 2, 3.

Abstract: In one embodiment, a flip chip LED is formed with a high density of gold posts extending from a bottom surface of its n-layer and p-layer. The gold posts are bonded to submount electrodes. An underfill material is then molded to fill the voids between the bottom of the LED and the submount. The underfill comprises a silicone molding compound base and about 70-80%, by weight, alumina (or other suitable material). Alumina has a thermal conductance that is about 25 times better than that of the typical silicone underfill, which is mostly silica. The alumina is a white powder. The underfill may also contain about 5-10%, by weight, TiO2 to increase the reflectivity. LED light is reflected upward by the reflective underfill, and the underfill efficiently conducts heat to the submount. The underfill also randomizes the light scattering, improving light extraction. The distributed gold posts and underfill support the LED layers during a growth substrate lift-off process.

Abstract: A system for and a method of curing a material is provided. A material, such as an underfill material, is rotated during a curing process. The curing system may include a chamber, a holder to support one or more workpieces, and a rotating mechanism. The rotating mechanism rotates the workpieces during the curing process. The chamber may include one or more heat sources and fans, and may further include a controller. The curing process may include varying the rotation speed, continuously rotating, periodically rotating, or the like.

Abstract: Underfill flow guide structures and methods of using the same are provided with a module. The method includes mounting bumps on a substrate. The method also includes forming underfill flow guide structures on the substrate by patterning wires with an overlay of hard substance. The underfill flow guide structures are integrated with the substrate and formed between adjacent bumps. The underfill flow guide structures are further formed to uniformly guide underfill along the substrate during capillary underfill processing.

Abstract: In order to easily inject underfill resin and perform molding with reliability, groove sections are formed on a surface of a circuit board such that the ends of the groove sections extend to semiconductor elements. Low-viscosity underfill resin applied dropwise is guided by the groove sections and flows between the circuit board and the semiconductor elements. The underfill resin hardly expands to regions outside the semiconductor elements.

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: Disclosed herein is a light emitting device, which includes a first substrate, a protective layer, a second substrate, a buffer member and a sealant. The first substrate has an illuminating member thereon. The protective layer covers the illuminating member and has a first coefficient of thermal expansion. The second substrate is disposed over the protective layer. The buffer member is disposed between the first and second substrates and surrounds the protective layer, wherein the buffer member has a second coefficient of thermal expansion which is less than the first coefficient. The sealant surrounds the buffer member and seals off the space between the first and second substrates, wherein the sealant has a third coefficient of thermal expansion which is less than the second coefficient.

Abstract: A manufacturing method of a semiconductor device includes: sealing a semiconductor chip with a sealing resin containing a filler; exposing a part of the filler; etching at least a part of the exposed filler; and forming a metal film at least at a part of a surface of the sealing resin including inner surfaces of holes formed at the surface of the sealing resin by the etching.

Abstract: An electroconductive bonding material contains a thermosetting resin, a low-melting-point metal powder which is melted at a temperature equal to or lower than the thermosetting temperature of the thermosetting resin, a high-melting-point metal powder which is not melted at a temperature equal to or lower than the thermosetting temperature of the thermosetting resin and which reacts with the low-melting-point metal powder to form a reaction product having a high melting point of 300° C. or higher during heat-hardening of the thermosetting resin, and a reducing substance which removes an oxide formed on the surface of the high-melting-point metal powder. The total content of the low-melting-point metal powder and the high-melting-point metal powder is 75% to 88% by weight, and the particle size ratio D1/D2 of the average particle size D1 of the low-melting-point metal powder to the average particle size D2 of the high-melting-point metal powder is 0.5 to 6.0.

Abstract: A sealing material is provided which has sealing characteristics with low stress and high reliability upon mounting electronic parts on a board, and good repairablity after the sealing. The sealing material contains a heat-curable resin component and is characterized by ?E/?T in a range of from 0.5 MPa/° C. to 30 MPa/° C. wherein ?E/?T represents a ratio of change (?E) in storage elastic modulus (E) relative to a temperature change (?T) when the storage elastic modulus (E) is determined as the temperature is raised within a temperature range including a glass transition point (Tg) of the cured sealing material.

Abstract: The extent of a bow of a semiconductor device is suppressed in a case where the fillet width of an underfill resin is asymmetrical. The center position 12 of a chip 1 is caused to deviate from the center position 13 of a wiring substrate 2 in a direction (the direction of the arrow B) reverse to the deviation direction (the direction of the arrow A) of the center position 11 of an underfill resin 4 from the center position 12 of the chip 1. The center position 14 of a resin for encapsulation 6 is caused to deviate from the center position 13 of the wiring substrate 2 in the same direction (the direction of the arrow A) as the deviation direction (the direction of the arrow A) of the center position 11 of the underfill resin 4 from the center position 12 of the chip 1.

Abstract: The present invention discloses a flip-chip semiconductor package and a chip carrier thereof. The chip carrier includes a groove formed around a chip-mounting area. The groove may be formed along a periphery of the chip-mounting area or at corners thereof. The groove is filled with a filler of low Young's modulus so as to absorb and eliminate thermal stress, thereby preventing delamination between an underfill and a flip chip mounted on the chip-mounting area.

Abstract: A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller footprint than that of the die. A method is disclosed which includes operatively coupling an interposer to a die comprising an integrated circuit, the interposer having a smaller footprint than that of the die, and filling a space between the interposer and the die with an underfill material.

Abstract: A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer.

Abstract: This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals.

Abstract: Underfill flow guide structures and methods of using the same are provided with a module. In particular the underfill flow guide structures are integrated with a substrate and are configured to prevent air entrapment from occurring during capillary underfill processes.

Abstract: An integrated circuit package comprises a molding compound covering a semiconductor die. A healing substance is on the surface of the semiconductor die at an interface of the molding compound and the semiconductor die. The healing compound comprises a catalyst and a plurality of microcapsules containing a sealing compound. If the molding compound becomes delaminated from the semiconductor die the microcapsules rupture and spill the sealing compound. When the sealing compound is spilled and contacts the catalyst the sealing compound and catalyst polymerize and fasten the molding compound to the semiconductor die.

Abstract: A stacked integrated circuit package system is provided including providing a first device and a second device with the first device, the second device, or a combination thereof having an integrated circuit die; forming a conductive spacer structure over the first device with the conductive spacer structure having a spacer filler around a conductive element; mounting the second device over the conductive spacer structure and the first device; and encapsulating the first device, the second device, and the conductive spacer structure.

Abstract: An electronic package for containing at least a top packaging module vertically stacked on a bottom packaging module. Each of the packaging modules includes a semiconductor chip packaged and connected by via connectors and connectors disposed on a laminated board fabricated with a standard printed-circuit board process wherein the top and bottom packaging module further configured as a surface mountable modules for conveniently stacking and mounting to prearranged electrical contacts without using a leadframe. At least one of the top and bottom packaging modules is a multi-chip module (MCM) containing at least two semiconductor chips. At least one of the top and bottom packaging modules includes a ball grid array (BGA) for surface mounting onto the prearranged electrical contacts. At least one of the top and bottom packaging modules includes a plurality of solder bumps on one of the semiconductor chips for surface mounting onto the prearranged electrical contacts.

Abstract: A wiring structure having a wiring-terminal-connection adhesive that includes a curing agent capable of generating a free radical upon heating, a radically polymerizable substance and silicone particles.