Abstract: A semiconductor device includes: first and second semiconductor elements, each of which has first and second electrodes; a first lead mounting the first semiconductor element; a second lead mounting the second semiconductor element; a sealing resin covering the first and second semiconductor elements; a third lead disposed apart from the first and second leads in a y direction, exposed from the sealing resin, and electrically connected to the first electrode of the first semiconductor element; a fifth lead disposed apart from the first and second leads on the opposite side to the third lead, exposed from the sealing resin, and electrically connected to the second electrode of the first semiconductor element; and a sixth lead disposed apart from the first and second leads on the same side as the fifth lead, exposed from the sealing resin, and electrically connected to the second electrode of the second semiconductor element.

Abstract: In a circuit module, lead frames include top surfaces facing a main surface of a substrate and bottom surfaces exposed from an insulating seal. The lead frames include pad portions including portions of the top surfaces and connected to metal posts, and lead portions including the bottom surfaces. The pad portions completely overlap the metal posts.

Abstract: A semiconductor package includes a substrate, a package structure, and a lid structure. The package structure is disposed on the substrate. The lid structure is disposed over substrate, wherein the lid structure includes a main body covering and surrounding the package structure and a plurality of rib portions protruded from the main body and extended toward the package structure.

Abstract: Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example, a semiconductor apparatus includes first and second semiconductor dies, each having a surface with an integrated circuit thereon coupled to contact pads of an uppermost metallization layer of a common semiconductor package substrate by a plurality of conductive contacts, the first and second semiconductor dies separated by a spacing. A barrier structure is disposed between the first semiconductor die and the common semiconductor package substrate and at least partially underneath the first semiconductor die. An underfill material layer is in contact with the second semiconductor die and with the barrier structure, but not in contact with the first semiconductor die.

Abstract: Lead frames for semiconductor device packages may include lead fingers proximate to a die-attach pad. A convex corner of the lead frame proximate to a geometric center of the lead frame may be rounded to include a radius of curvature of at least two times a greatest thickness of the die-attach pad. The thickness of the die-attach pad may be measured in a direction perpendicular to a major surface of the die-attach pad. A shortest distance between the die-attach pad and each one of the lead fingers having a surface area larger than an average surface area of the lead fingers may be at least two times the greatest thickness of the die-attach pad.

Abstract: A resin composition includes (A) a polyolefin epoxy resin, (B) an epoxy resin having a condensed polycyclic aromatic hydrocarbon, (C) a nitrogen-containing novolak resin, and (D) an inorganic filler, in which an epoxy equivalent of the (A) component is 200 g/eq. or more, a nitrogen content in the (C) component is 13% by mass or more and/or the (C) component has a cresol novolak structure, and a content of the (D) component is 60% by mass or more on the basis of 100% by mass of non-volatile components in the resin composition.

Abstract: A semiconductor package structure includes a die paddle, a plurality of leads, an electronic component and a package body. Each of the plurality of leads is separated from the die paddle and has an inner side surface facing the die paddle. The electronic component is disposed on the die paddle. The package body covers the die paddle, the plurality of leads and the electronic component. The package body is in direct contact with a bottom surface of the die paddle and the inner side surface of the plurality of leads.

Abstract: In one example, an electronic device comprises a base substrate comprising a base substrate conductive structure, a first electronic component over a first side of the base substrate, an encapsulant over the first side of the base substrate, wherein the encapsulant contacts a lateral side of the electronic component, an interposer substrate over a first side of the encapsulant and comprising an interposer substrate conductive structure, and a vertical interconnect in the encapsulant and coupled with the base substrate conductive structure and the interposer substrate conductive structure. A first one of the base substrate or the interposer substrate comprises a redistribution layer (RDL) substrate, and a second one of the base substrate or the interposer substrate comprises a laminate substrate. Other examples and related methods are also disclosed herein.

Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.

Abstract: A semiconductor package includes: a first package substrate; a first semiconductor device mounted on the first package substrate; a second package substrate arranged on an upper part of the first semiconductor device; and a heat-dissipating material layer arranged between the first semiconductor device and the second package substrate and having a thermal conductivity of approximately 0.5 W/m·K to approximately 20 W/m·K, wherein the heat-dissipating material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second package substrate.

Abstract: A pressure sensor for an evaporated fuel leak detector includes a sensor unit, a case, and a sealing resin. The sensor unit has a pressure receiving portion, a plurality of conduction terminals, and a mold resin portion. The case has a fluid flow path and a housing recess. Each remaining inner wall surface of the housing recess except for an inner wall surface on the conduction terminal side is provided with an inclined surface and a vertical surface, in a cross section along an axial direction perpendicular to a pressure receiving surface of the sensor unit. The inclined surface is inclined inward as toward a pressure receiving side. The vertical surface extends from the end of the inclined surface on the pressure receiving side to define a filling gap in which the sealing resin is filled between the side surface of the mold resin portion and the vertical surface.

Abstract: An electronic device module includes a substrate, at least one first component and at least one second component disposed on one surface of the substrate, a second sealing portion having the at least one second component embedded therein, and disposed on the substrate, and a first sealing portion disposed outside of the second sealing portion, at least a portion of the first sealing portion being disposed between the at least one first component and the substrate.

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes stacking a plurality of integrated circuit dies on a wafer to form a die stack. A bonding process is performed on the die stack. The bonding process mechanically and electrically connects adjacent integrated circuit dies of the die stack to each other. A dam structure is formed over the wafer. The dam structure surrounds the die stack. A first encapsulant is formed over the wafer and between the die stack and the dam structure. The first encapsulant fills gaps between the adjacent integrated circuit dies of the die stack. A second encapsulant is formed over the wafer. The second encapsulant surrounds the die stack, the first encapsulant and the dam structure.

Abstract: A package is disclosed. In one example, the package comprises a carrier, an electronic component mounted on the carrier, and an encapsulant encapsulating at least part of the electronic component and only part of the carrier so that another exposed part of the carrier is exposed with regard to the encapsulant. The exposed part of the carrier comprises an electric connection structure and a corrosion protection structure. One of the electric connection structure and the corrosion protection structure is selectively formed on only a sub-portion of the other one of the electric connection structure and the corrosion protection structure outside of the encapsulant.

Abstract: A microelectronic device, in a multirow gull-wing chip scale package, has a die connected to intermediate pads by wire bonds. The intermediate pads are free of photolithographically-defined structures. An encapsulation material at least partially surrounds the die and the wire bonds, and contacts the intermediate pads. Inner gull-wing leads and outer gull-wing leads, located outside of the encapsulation material, are attached to the intermediate pads. The gull-wing leads have external attachment surfaces opposite from the intermediate pads. The external attachment surfaces of the outer gull-wing leads are located outside of the external attachment surfaces of the inner gull-wing leads. The microelectronic device is formed by mounting the die on a carrier, forming the intermediate pads without using a photolithographic process, and forming the wire bonds. The encapsulation material is formed, and the carrier is subsequently removed, exposing the intermediate pads.

Abstract: A foundation layer having a stiffener and methods of forming a stiffener are described. One or more dies are formed over the foundation layer. Each die has a front side surface that is electrically coupled to the foundation layer and a back side surface that is opposite from the front side surface. A stiffening layer (or a stiffener) is formed on the back side surface of at least one of the dies. The stiffening layer may be directly coupled to the back side surface of the one or more dies without an adhesive layer. The stiffening layer may include one or more materials, including at least one of a metal, a metal alloy, and a ceramic. The stiffening layer may be formed to reduce warpage based on the foundation layer and the dies. The one or more materials of the stiffening layer can be formed using a cold spray.

Abstract: A semiconductor device includes: a substrate; a semiconductor element that disposed on the upper surface of the substrate; a sealing portion that seals the substrate and the semiconductor element; a first lead frame that has one end in contact with a upper surface of the first conductive layer at an end extending in the side direction of the upper surface of the substrate in the sealing portion, and has the other end exposed from the sealing portion; a first conductive bonding material that bonds between the upper surface of the first conductive layer and the lower surface side of the one end portion of the first lead frame at the end portion of the substrate, and has electrical conductivity.

Abstract: An image capturing device including a cover plate, an image capturing module, a frame body, a first adhesive layer, and a second adhesive layer is provided. The frame body and the image capturing module are located on the same side of the cover plate. The frame body is joined to the cover plate through the first adhesive layer. The image capturing module is joined to the frame body through the second adhesive layer. An orthographic projection of the second adhesive layer on the cover plate falls within an orthographic projection of the frame body on the cover plate.

Abstract: An optical device package comprises a carrier having a first surface and a second surface recessed with respect to the first surface and a lid disposed on the second surface of the carrier.

Abstract: A semiconductor package includes a semiconductor die including a sensing component, an encapsulant extending along sidewalls of the semiconductor die, a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant and disposed aside the semiconductor die, a patterned dielectric layer disposed on the encapsulant and exposing the sensing component of the semiconductor die, a conductive pattern disposed on the patterned dielectric layer and extending to be in contact with the TIV and the semiconductor die, and a first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV through an alignment opening of the first patterned dielectric layer. The semiconductor die is in a hollow region of the encapsulant, and a top width of the hollow region is greater than a width of the semiconductor die.

Abstract: An image sensor packaging method, an image sensor packaging structure and a lens module are disclosed by the present invention provides. With the image sensor packaging method, a plurality of image sensor chips are embedded in a molding layer, thus allowing a greatly reduced thickness and improved slimness of the resulting packaging structure. Moreover, in this packaging method, instead of bonding wires, solder pads are externally connected by thin film metal layer formed on non-photosensitive surface area located on the same side as light-sensing surfaces. This allows a reduced impact on the light-sensing surfaces as well as a shorter distance from each solder pad to a corresponding one of the light-sensing surfaces along the direction parallel to the light-sensing surfaces, when compared to the use of bonding wires.

Abstract: A liquid crystal antenna and a manufacturing method thereof are disclosed. The liquid crystal antenna includes: an antenna array including a first substrate and a second substrate arranged opposite to each other and configured to change a phase of an electromagnetic wave signal fed into the liquid crystal antenna to transmit or receive a beam in a preset direction; and an inertial navigation element configured to determine a motion parameter of the liquid crystal antenna in a navigation coordinate system, the inertial navigation element is disposed on a side of the second substrate facing the first substrate; and the antenna array adjusts the preset direction according to the motion parameter acquired by the inertial navigation element.

Abstract: An electronic device module includes a substrate, at least one first component and at least one second component disposed on one surface of the substrate, a second sealing portion having the at least one second component embedded therein, and disposed on the substrate, and a first sealing portion disposed outside of the second sealing portion, at least a portion of the first sealing portion being disposed between the at least one first component and the substrate.

Abstract: Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes a plurality of integrated circuits, a first encapsulant, a first redistribution structure, a plurality of conductive pillars, a second redistribution structure, a second encapsulant and a third redistribution structure. The first encapsulant encapsulates the integrated circuits. The first redistribution structure is disposed over the first encapsulant and electrically connected to the integrated circuits. The conductive pillars are disposed over the first redistribution structure. The conductive pillars are disposed between and electrically connected to the first and second redistribution structures. The second encapsulant encapsulates the conductive pillars and is disposed between the first redistribution structure and second redistribution structure.

Abstract: A method includes forming a device structure, the method including forming a first redistribution structure over and electrically connected to a semiconductor device, forming a molding material surrounding the first redistribution structure and the semiconductor device, forming a second redistribution structure over the molding material and the first redistribution structure, the second redistribution structure electrically connected to the first redistribution structure, attaching an interconnect structure to the second redistribution structure, the interconnect structure including a core substrate, the interconnect structure electrically connected to the second redistribution structure, forming an underfill material on sidewalls of the interconnect structure and between the second redistribution structure and the interconnect structure.

Abstract: The present disclosure relates to a semiconductor device package including a substrate, a semiconductor device and an underfill. The substrate has a first surface and a second surface angled with respect to the first surface. The semiconductor device is mounted on the first surface of the substrate and has a first surface facing the first surface of the substrate and a second surface angled with respect to the first surface of the substrate. The underfill is disposed between the first surface of the semiconductor device and the first surface of the substrate. The second surface of the substrate is located in the substrate and external to a vertical projection of the semiconductor device on the first surface of the substrate.

Abstract: The present invention relates to a three-dimensional integrated package device for a high-voltage silicon carbide power module, comprising a source substrate, first chip submodules, a first driving terminal, a first driving substrate, a ceramic housing, a metal substrate, a water inlet, a water outlet, second chip submodules, a second driving terminal, a second driving substrate and a drain substrate from top to bottom; and each first chip submodule is composed of a driving connection substrate, a power source metal block, a first driving gate metal post, second driving gate metal posts, a silicon carbide bare chip, an insulation structure and the like. A three-dimensional integrated half-bridge structure is adopted to greatly reduce corresponding parasitic parameters.

Abstract: One embodiment is directed towards an encapsulated device. The encapsulated device includes a device, and a first encapsulation covering the device. The first encapsulation has one or more exterior surfaces. One or more recesses in one or more of the exterior surfaces is configured to receive a second encapsulation.

Abstract: A device includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle, an outer lead portion opposite to the inner lead portion and a bridge portion between the inner lead portion and the outer lead portion. The inner lead portion has an upper bond section connected to the bridge portion and a lower support section below the upper bond section. A sum of a thickness of the upper bond section and a thickness of the lower support section is greater than a thickness of the bridge portion.

Abstract: A semiconductor package is provided which addresses problems of mold cap heel cracking. The package may made by using a cavity die and a gate insertion tool. The gate insertion tool, which fits into the cavity die, has an elongated body and includes a nozzle head with an edge which is contoured in relation to a mold cap formed on a substrate. The edge defines a curved border, for the mold cap, from a plane above the substrate to a plane lying on the substrate. The nozzle head includes a slot, for admitting a cull runner tip, centered on an axis of the elongated body.

Abstract: A method for producing a power semiconductor module arrangement includes forming a pre-layer by depositing inorganic filler on a first surface within a housing, the inorganic filler being impermeable to corrosive gases. The method further includes filling casting material into the housing to fill spaces present in the inorganic filler of the pre-layer with the casting material, and hardening the casting material to form a first layer.

Abstract: A memory device includes a first semiconductor chip including a memory cell array disposed on a first substrate, and a first bonding metal on a first uppermost metal layer of the first semiconductor chip, and a second semiconductor chip including circuit devices disposed on a second substrate and a second bonding metal on a second uppermost metal layer of the second semiconductor chip, the circuit devices providing a peripheral circuit operating the memory cell array. The first and second semiconductor chips are electrically connected to each other by the first bonding metal and the second bonding metal in a bonding area. A routing wire electrically connected to the peripheral circuit is disposed in one or both of the first and second uppermost metal layers and is disposed in a non-bonding area in which the first and second semiconductor chips are not electrically connected to each other.

Abstract: A semiconductor device may include a first conductive plate, a plurality of semiconductor chips disposed on the first conductive plate, and a first external connection terminal connected to the first conductive plate. The plurality of semiconductor chips may include first, second, and third semiconductor chips. The second semiconductor chip may be located between the first semiconductor chip and the third semiconductor chip. A portion of the first conductive plate where the first external connection terminal is connected may be closest to the second semiconductor chip among the first, second, and third semiconductor chips. The first conductive plate may be provided with an aperture located between the portion of the first conductive plate where the first external connection terminal is connected and a portion of the first conductive plate where the second semiconductor chip is connected.

Abstract: A semiconductor device includes a substrate, a first semiconductor chip on the substrate, a first adhesive material on the first semiconductor chip, a spacer chip on the first adhesive material, a second adhesive material on the spacer chip, a second semiconductor chip on the second adhesive material, and a resin material that covers the first and second semiconductor chips and the spacer chip. The spacer chip has a first region with which the resin material comes in contact is roughened and a second region that is different from the first region.

Abstract: In some examples, a system comprises a die having multiple electrical connectors extending from a surface of the die and a lead coupled to the multiple electrical connectors. The lead comprises a first conductive member; a first non-solder metal plating stacked on the first conductive member; an electroplated layer stacked on the first non-solder metal plating; a second non-solder metal plating stacked on the electroplated layer; and a second conductive member stacked on the second non-solder metal plating, the second conductive member being thinner than the first conductive member. The system also comprises a molding to at least partially encapsulate the die and the lead.

Abstract: Embodiments of systems and methods for an FIB-aware anti-probing physical design flow are described in the present disclosure. Such embodiments incorporate new and improved security-critical steps in a physical design flow, in which the design is constrained to provide coverage on asset nets through an internal shield.

Abstract: A component mounting board includes first and second substrates, a connection substrate, an interposer, and an electronic component. The first substrate has first and second surfaces opposing each other, a first side surface between the first and second surfaces, and a first signal pattern. The second substrate is disposed on the first substrate, has third and fourth surfaces opposing each other and a second side surface between the third and fourth surfaces, and includes a second signal pattern. The connection substrate is bent to connect the first and second side surfaces, and the interposer is disposed between the first and third surfaces and electrically connects the first and second signal patterns. The electronic component is mounted on at least one of the first to fourth surfaces.

Abstract: A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, and a molding member that surrounds the at least one semiconductor chip. The molding member includes fillers. Each of the fillers includes a core and a coating layer that surrounds the core. The core includes a non-electromagnetic material and the coating layer includes an electromagnetic material. The molding member includes regions respectively have different distributions of the fillers.

Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.

Abstract: An antenna module includes a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) package disposed on a first surface of the connection member; and an antenna package including a plurality of antenna members and a plurality of feed vias, and disposed on a second surface of the connection member, wherein the IC package includes: an IC having an active surface electrically connected to at least one wiring layer and an inactive surface opposing the active surface, and generating the RF signal; a heat sink member disposed on the inactive surface of the IC; and an encapsulant encapsulating at least portions of the IC and the heat sink member.

Abstract: A microelectronic device and/or microelectronic device package having a warpage control structure. The warpage control structure may be positioned over an encapsulating material, wherein the encapsulating material is positioned between the warpage control structure and a die positioned over a substrate. The warpage control structure may have a first thickness over a first portion of the encapsulating material and a second thickness over a second portion of the encapsulating material. Methods of forming the microelectronic device are also disclosed herein.

Abstract: A stiffener on a semiconductor package substrate includes a plurality of parts that are electrically coupled to the semiconductor package substrate on a die side. Both stiffener parts are electrically contacted through a passive device that is soldered between the two stiffener parts and by an electrically conductive adhesive that bonds a given stiffener part to the semiconductor package substrate. The passive device is embedded between two stiffener parts to create a smaller X-Y footprint as well as a lower Z-direction profile.

Abstract: Conventionally, when an adherend is nickel or the like, it has been difficult to realize an electroconductive adhesive that lowers connection resistance in various kinds of thermocurable curing resins. However, it is possible to provide an electroconductive adhesive, in the case where the adherend is nickel or the like, which reduces connection resistance in various kinds of thermocurable curing resins while simultaneously maintaining storage stability to have good handleability. The present description provides a thermocurable electroconductive adhesive including the following components (A) to (D): Component (A): a curable resin, Component (B): a thermal curing agent that cures Component (A), Component (C): an organometallic complex, and Component (D): electroconductive particles.

Abstract: A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.

Abstract: A system and method for detecting particles in a fluidic medium using a microfluidic sensor is described. The system utilises microfluidic channels though which the fluidic medium is passed. On one section of the microfluidic channel, an array of non-flexible electrodes are coupled with uniform spacing therebetween. On the opposing section of the channel, a flexible electrode is coupled and all electrodes are connected to an electrical analyser which is used to generate an electrical field inside the microfluidic channel with the flexible electrode acting as ground. The flexible electrode is actuated by different means to narrow the width of the microfluidic in the section of interest and to capture the particle between the section, where sectional scans of the particles are obtained and electrical properties of the particle are measured, thereby detecting the particles in the fluidic medium.

Abstract: It is an object of the present invention to provide a method for manufacturing a resin-sealed power semiconductor device that facilitates the separation of a suspension lead from a mold resin and a lead frame. A method for manufacturing a resin-sealed power semiconductor device according to the present invention includes the following steps: (a) sealing a semiconductor element and a lead frame, to prepare a sealed body in which a terminal lead and a suspension lead that are included in the lead frame project outward from a side of the mold resin; (b) punching a portion of the suspension lead, the portion projecting from the mold resin, with a first punch in a first direction, to separate the suspension lead from the mold resin; and (c) punching the projecting portion of the suspension lead with a second punch in a second direction.

Abstract: A display device includes a substrate including an upper surface, a lower surface, and side surfaces; a display element layer on the upper surface overlapping the display area; an encapsulation layer on the upper surface, the encapsulation layer including a main part that overlaps the display element layer and a protruding part that protrudes along a first direction from the main part and overlaps the bezel area; an input sensor on the main part; a first circuit board facing the main part, overlapping the bezel area, and on the upper surface; and a second circuit board on the protruding part, wherein each of the first circuit board and the second circuit board is adjacent to a first side surface among the side surfaces, and in the first direction, the protruding part is more adjacent to the first side surface than the main part.

Abstract: A method of forming a package structure includes the following processes. A die is attached to a polymer layer. An encapsulant is formed over the polymer layer to encapsulate sidewalls of the die. A RDL structure is formed on the encapsulant and the die. A conductive terminal is electrically connected to the die through the RDL structure. A light transmitting film is formed on the polymer layer. An alignment process is performed, and the alignment process uses an optical equipment to see through the light transmitting film to capture the alignment information included in the polymer layer. A singulating process is performed to singulate the package structure according to the alignment information.

Abstract: A die stack structure may include a base die having base contact pads insulated by a base protection patterns and a flat side surface, a die stack bonded to the base die and having a plurality of component dies on the base die such that each of the component dies includes component contact pads insulated by a corresponding component protection pattern, and a residual mold unevenly arranged on a side surface of the die stack such that the component dies are attached to each other by the residual mold.

Abstract: A hermetic capsule including a semiconductor/metal base with sensitive semiconductor/polymer electrical and optical components formed thereon and a semiconductor/metal lid. The semiconductor/metal lid sealed to the semiconductor/metal base by metallization so as to form a chamber including all of the sensitive semiconductor/polymer electrical and optical components and hermetically sealing the chamber and all sensitive components from the ambient. External access to the sensitive semiconductor/polymer electrical and optical components is provided through a metallization.