Abstract: A method of fabricating a semiconductor device includes forming a first film on a processed film, patterning the first film into a pattern with smaller width and a space with larger width, forming a second film along upper and side surfaces of first film and an upper surface of second film, etching the second film thereby to expose upper surfaces of first film and processed film while part of second film remains along the side surface of first film, etching the first film under the condition that the first film has higher etch selectivity than the second film, etching an upper part of second film under the condition that the second film has a higher etch selectivity than the processed film, after the first film has been etched, and etching the processed film with the second film serving as mask after the upper part of second film has been etched.

Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Abstract: A plurality of gate lines are formed on a substrate. After depositing a gate insulating layer, a semiconductor layer and a doped amorphous silicon layer are sequentially formed thereon. A lower insulating layer made of silicon nitride and an upper insulating layer made of a photosensitive organic material are deposited thereon after forming data lines and drain electrodes. The upper insulating layer is patterned to form an unevenness pattern on its surface and contact holes on the drain electrodes. The lower insulating layer is patterned together with the gate insulating layer using a photoresist pattern having apertures located in the contact holes to form other contact holes respectively exposing the drain electrodes, portions of the gate lines, and portions of the data lines.

Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.

Abstract: A method for fabricating a capacitor in a semiconductor device includes forming an insulation layer over a substrate, forming a storage node contact plug passing through the insulation layer and coupled to the substrate, recessing the storage node contact plug to a certain depth to obtain a sloped profile, forming a barrier metal over the surface profile of the recessed storage node contact plug, forming a sacrificial layer over the substrate structure, etching the sacrificial layer to form an opening exposing the barrier metal, forming a bottom electrode over the surface profile of the opening, and removing the etched sacrificial layer.

Abstract: A method of fabricating a semiconductor device, the method comprises forming a mask layer over a compound semiconductor substrate; and patterning a photoresist over the mask layer. The method comprises etching a portion of the mask layer beneath the photoresist; forming a hardmask over the substrate and not over the mask layer; removing the mask layer; etching to form and opening down to the substrate; and forming a gate in the opening.

Abstract: A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (19) that is isolated from an underlying first single crystal semiconductor layer (17) by a buried insulator layer (18); patterning and etching the second single crystal semiconductor layer (19) to form a single crystal mandrel (42) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers (52) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel (42) while substantially retaining the oxide spacers (52); and selectively etching the first single crystal semiconductor layer (17) using the oxide spacers (52) to form one or more FinFET channel regions (92).

Abstract: When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage, the dielectric cap layer of the gate electrode structures may be efficiently removed on the basis of a carbon spacer element, which may thus preserve the integrity of the silicon nitride spacer structure. Thereafter, the sacrificial carbon spacer may be removed substantially without affecting other device areas, such as isolation structures, active regions and the like, which may contribute to superior process conditions during the further processing of the semiconductor device.

Abstract: Methods used during the manufacture of a semiconductor device, such as one that includes forming a plurality of vertically oriented first support features. Each feature comprises first and second sidewalls and the first support features are formed to have a first pitch. A plurality of first mask spacers are formed, wherein one first mask spacer is formed on each first support feature sidewall, and each first mask spacer comprises an exposed, vertically oriented sidewall. A plurality of vertically oriented second support features are formed, wherein one second support feature is formed on the exposed, vertically oriented sidewall of each first mask spacer, and each second support feature is separated from an adjacent second support feature by a gap. A plurality of second mask features are formed, wherein one second mask feature is formed within each gap.

Abstract: A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures.

Abstract: Methods are provided for forming contacts for a semiconductor device. The methods may include depositing various materials, such as polysilicon, nitride, oxide, and/or carbon materials, over the semiconductor device. The methods may also include forming a contact hole and filling the contact hole to form the contact for the semiconductor device.

Abstract: Methods of producing an electromechanical circuit element are described. A lower structure having lower support structures and a lower electrically conductive element is provided. A nanotube ribbon (or other electromechanically responsive element) is formed on an upper surface of the lower structure so as to contact the lower support structures. An upper structure is provided over the nanotube ribbon. The upper structure includes upper support structures and an upper electrically conductive element. In some arrangements, the upper and lower electrically conductive elements are in vertical alignment, but in some arrangements they are not.

Abstract: A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.

Abstract: A method of manufacturing a memory device includes an nMOS region and a pMOS region in a substrate. A first gate is defined within the nMOS region, and a second gate is defined in the pMOS region. Disposable spacers are simultaneously defined about the first and second gates. The nMOS and pMOS regions are selectively masked, one at a time, and LDD and Halo implants performed using the same masks as the source/drain implants for each region, by etching back spacers between source/drain implant and LDD/Halo implants. All transistor doping steps, including enhancement, gate and well doping, can be performed using a single mask for each of the nMOS and pMOS regions. Channel length can also be tailored by trimming spacers in one of the regions prior to source/drain doping.

Abstract: A method for fabricating a semiconductor mask is described. A semiconductor stack having a sacrificial mask comprised of a series of lines is first provided. A spacer mask having spacer lines adjacent to the sidewalls of the series of lines of the sacrificial mask is then formed. The spacer mask also has interposed lines between the spacer lines. Finally, the sacrificial mask is removed to provide only the spacer mask. The spacer mask having interposed lines triples the frequency of the series of lines of the sacrificial mask.

Abstract: A magnetic memory device including a Magnetic Tunnel Junction (MTJ) device comprises a substrate and Front End of Line (FEOL) circuitry. A Via level (VA) InterLayer Dielectric (ILD) layer, a bottom conductor layer, and an MTJ device formed over the top surface of the VA ILD layer are formed over a portion of the substrate. An alignment region including alignment marks extends through the bottom conductor layer and extends down into the device below the top surface of the VA ILD layers is juxtaposed with the MJT device.

Abstract: An embodiment of a system and method produces a random half pitched interconnect layout. A first normal-pitch mask and a second normal-pitch mask are created from a metallization layout having random metal shapes. The lines and spaces of the first mask are printed at normal pitch and then the lines are shrunk to half pitch on mask material. First spacers are used to generate a half pitch dimension along the outside of the lines of the first mask. The mask material outside of the first spacer pattern is partially removed. The spacers are removed and the process is repeated with the second mask. The mask material remains at the locations of first set of spacers and/or the second set of spacers to create a half pitch interconnect mask with constant spaces. In an embodiment, the half pitch interconnect mask is used to create a metallization interconnect layer with area of constant spacing and area of metallization.

Abstract: In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anisotropically etched spacers. The spacers are utilized to pattern lines in material underlying the spacers. Some embodiments include constructions having one or more openings which contain steep sidewalls joining to one another at shallow sidewall regions. The constructions may also contain lines along and directly against the steep sidewalls, and spaced from one another by gaps along the shallow sidewall regions.

Abstract: A method of manufacturing a semiconductor device according to the invention is an effective technique for ensuring a sufficient process margin and enabling the formation of a fine pattern in a peripheral circuit region. The method includes forming an anti-reflective layer with a varying thickness in a peripheral circuit region and a cell region, and then over-etching the anti-reflective layer in the peripheral circuit region. The method is capable of improving the data processing speed of a semiconductor device and therefore increases the device efficiency.

Abstract: Methods of fabricating a semiconductor device is provided. The methods include forming an interlayer insulating layer on a semiconductor substrate having a first region and a second region. First contact plugs may be formed on a portion of the second region to fill a plurality of first contact holes. A plurality of first contact mask layers and a plurality of first dummy mask layers may be formed on the interlayer insulating layer. The first contact mask layers may be formed in the first region. The first dummy mask layers may be formed in the second region. A plurality of second contact mask layers may be formed between two adjacent first contact mask layers. A plurality of second dummy mask layers may be formed between two adjacent first dummy mask layers. The interlayer insulating layer may be etched using the first contact mask layers and the second contact mask layers as etch stop layers to form a plurality of second contact holes through the interlayer insulating layer formed in the first region.

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract: A method of fabricating an integrated circuit, including the steps of forming a first mask layer in the form of a hard mask layer including a plurality of first openings and a second mask layer with at least one second opening which at least partially overlaps with one of the first openings, wherein the at least one second opening is generated lithographically; and at least two neighboring first openings are distanced from each other with a center to center pitch smaller than the resolution limit of the lithography used for generating the second opening.

Abstract: A method for forming a fine pattern of a semiconductor device include forming a stack structure including a 1st layer hard mask film to a nth layer hard mask film (n is an integer ranging from 2 or more) over an underlying layer formed over a semiconductor substrate. The nth layer hard mask film, the top layer, is selectively etched to obtain a first hard mask pattern of the nth layer. A second hard mask pattern of the nth layer is formed between the first hard mask patterns of the nth layer. A (n?1)th layer hard mask film is etched using the first and the second hard mask pattern of the nth layer as etching masks. The (c) step to the (d) step repeat to form the first and the second hard mask patterns of the 1st layer over the underlying layer. And, the underlying layer is etched using the first and second hard mask patterns of the 1st layer as etching masks.

Abstract: An EL element capable of: preventing the state in which number of excessive layers are laminated on each light emitting part formed in a pattern at the time of forming the light emitting parts using the photolithography method; executing the peeling treatment easily and quickly in the excessive layer peeling process; and preventing generation of color mixture or pixel narrowing derived from the elution of the patterned light emitting part into the light emitting layer coating solution to be coated later, at the end part thereof, at the time of coating a light emitting layer coating solution. In order to achieve the above mentioned object, the present invention provides a method for manufacturing an electroluminescent element using a photolithography method.

Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.

Abstract: A method of etching a substrate is provided. The method of etching a substrate includes transferring a pattern into the substrate using a double patterned amorphous carbon layer on the substrate as a hardmask. Optionally, a non-carbon based layer is deposited on the amorphous carbon layer as a capping layer before the pattern is transferred into the substrate.

Abstract: According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, the method including: forming a first film on a target film; forming resist patterns on the first film; processing the first film with the resist patterns to form first patterns including: periodic patterns; and aperiodic patterns; removing the resist patterns; forming a second film over the target film; processing the second film to form second side wall patterns on side walls of the first patterns; removing the periodic patterns; and processing the target film with the aperiodic patterns and the second side wall patterns, thereby forming a target patterns including: periodic target patterns; aperiodic target patterns; and dummy patterns arranged between the periodic target patterns and the aperiodic patterns and arranged periodically with the periodic target patterns.

Abstract: A patterning method for a semiconductor substrate is disclosed. A substrate is provided and a stack structure is laid thereon. The stack layer includes at least a target layer and a pad layer sequentially formed on the substrate. Follow by a lithography process, wherein photoresists are laid on the stack layer to form a plurality of photoresist elements. Thus, a plurality of pattern is formed on the target layer, and a portion of target layer's surface is exposed. Lastly, ion implanting is provided and defines a doped area as hard mask for the etching process.

Abstract: Methods of isolating spaces formed between features in an array during a pitch reduction process and semiconductor device structures having the same. In one embodiment, ends of the features are wider than middle regions of the features. During the pitch reduction process, spacer sidewalls formed between adjacent ends of the features come into substantial contact with one another, isolating the spaces between the features. In another embodiment, the features have a single width and an additional feature is located near ends of the features. Spacer sidewalls formed between adjacent features and the additional feature come into substantial contact with one another, isolating the spaces between the features.

Abstract: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

Abstract: A method used during the manufacture of a semiconductor device comprises the formation of a first patterned layer having individual features of a first density. Through the formation and etching of various layers, for example conformal layers and a spun-on layer, a second patterned layer results which comprises individual features of a second density, which is about three times the first density. An in-process semiconductor apparatus formed using the method, and a system comprising the semiconductor apparatus formed according to the method, is also described.

Abstract: An integrated circuit package may include a plurality of interconnects, and an integrated package substrate coupled to the plurality of interconnects and comprising an integrated circuit package substrate core. A first surface of the integrated circuit package substrate core may define a depression.

Abstract: To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.

Abstract: A method for forming a fine pattern of a semiconductor device overcomes resolution limits of exposure equipment. The method includes forming a first photoresist pattern over an underlying layer formed over a semiconductor substrate. An amorphous carbon film and a second photoresist film are sequentially deposited over the first photoresist pattern. The second photoresist film and the amorphous carbon film are planarized to expose the first photoresist pattern. A thick portion and a thin portion of the amorphous carbon film is formed. The first photoresist pattern and the second photoresist film are removed. Etching is performed on the thin portion of the amorphous carbon film and the underlying layer using the thick portion of the amorphous carbon film as an etch mask. The thick portion of the amorphous carbon film is removed to expose a fine pattern of the underlying layer.

Abstract: A method of forming a photoresist-comprising pattern on a substrate includes forming a patterned first photoresist having spaced first masking shields in at least one cross section over a substrate. The first masking shields are exposed to a fluorine-containing plasma effective to form a hydrogen and fluorine-containing organic polymer coating about outermost surfaces of the first masking shields. A second photoresist is deposited over and in direct physical touching contact with the hydrogen and fluorine-containing organic polymer coating. The second photoresist which is in direct physical touching contact with the hydrogen and fluorine-containing organic polymer coating is exposed to a pattern of actinic energy and thereafter spaced second masking shields are formed in the one cross section which comprise the second photoresist and correspond to the actinic energy pattern. The first and second masking shields together form at least a part of a photoresist-comprising pattern on the substrate.

Abstract: A method of manufacturing a semiconductor device, the semiconductor device comprising: a semiconductor substrate; a pixel portion including an in-layer lens; and a peripheral circuit portion including a metal wiring portion, the pixel portion and the peripheral circuit portion being on the semiconductor substrate, the method comprising: forming an insulating film in the pixel portion and the peripheral circuit portion, so as to cover the metal wiring portion; providing, on the insulating film, a lens material layer for forming the in-layer lens; forming a resist layer for etching the lens material layer; curing the resist layer; and forming a first region and a second region in the resist layer, wherein a portion of the resist layer in the first region is thicker than that of the resist layer in the second region, the first region being in the peripheral circuit portion and the second region being in the pixel portion.

Abstract: Broadly speaking, methods and an apparatus are provided for removing an inorganic material from a substrate. More specifically, the methods provide for removing the inorganic material from the substrate through exposure to a high density plasma generated using an inductively coupled etching apparatus. The high density plasma is set and controlled to isotropically contact particular regions of the inorganic material to allow for trimming and control of a critical dimension associated with the inorganic material.

Abstract: A method of forming a mask pattern and, more particularly, a method of forming a mask pattern wherein micro patterns having resolutions lower than those of exposure equipment by overcoming the resolutions of the exposure equipment, wherein, a silicon layer is formed over a substrate and is patterned. The patterned silicon layer is oxidized to form the entire surface of the silicon layer to a specific thickness by using an oxide layer. The oxide layer is removed to expose a top surface of the silicon layer. A mask pattern is formed with the remaining oxide layer by removing the silicon layer.

Abstract: Provided is a method of forming a nanostructure having a nano-sized diameter and a high aspect ratio through a simple and economical process. To form the nanostructure, a polymer thin film is formed on a substrate and a mold is brought to contact the polymer thin film. Then, a polymer patterning is formed to contact the background surface of an engraved part of the mold, and then the polymer pattern is extended out by removing the mold out of the polymer thin film. The nanostructure forming method of the present research can reproduce diverse cilia optimized in the natural world. Also, it can be used to develop new materials with an ultra-hydrophobic property or a high adhesiveness. Further, it can be applied to a nanopattern forming process for miniaturizing electronic devices and to various ultra-precise industrial technologies together with carbon nanotube, which stands in the highlight recently.

Abstract: To provide a manufacturing method of a semiconductor device with a reduced chip area by reducing the size of a pattern for forming an integrated circuit. For example, the size of an IC chip that is provided as an application of IC cards or IC tags can be reduced. The manufacturing method includes the steps of forming a gate electrode; forming an insulating layer over the gate electrode; and forming an opening in the insulating layer. One or both of the step of forming the gate electrode and the step of forming the opening in the insulating layer is/are conducted by a lithography process using a phase-shift mask or a hologram mask. Accordingly, micropatterns can be formed even over a substrate with low planarity such as a glass substrate.

Abstract: A self-align patterning method for forming patterns includes forming a first layer on a substrate, forming a plurality of first hard mask patterns on the first layer, forming a sacrificial layer on top surfaces and sidewalls of the first hard mask patterns, thereby forming a gap between respective facing portions of the sacrificial layer on the sidewalls of the first hard mask patterns, forming a second hard mask pattern in the gap, etching the sacrificial layer using the second hard mask pattern as a mask to expose the first hard mask patterns, exposing the first layer using the exposed first hard mask patterns and the second hard mask pattern, and etching the exposed first layer using the first and second hard mask patterns.

Abstract: Single spacer processes for multiplying pitch by a factor greater than two are provided. In one embodiment, n, where n?2, tiers of stacked mandrels are formed over a substrate, each of the n tiers comprising a plurality of mandrels substantially parallel to one another. Mandrels at tier n are over and parallel to mandrels at tier n?1, and the distance between adjoining mandrels at tier n is greater than the distance between adjoining mandrels at tier n?1. Spacers are simultaneously formed on sidewalls of the mandrels. Exposed portions of the mandrels are etched away and a pattern of lines defined by the spacers is transferred to the substrate.

Abstract: A method of forming fine patterns of a semiconductor device includes double etching by changing a quantity of producing polymer by-products to etch a film with different thicknesses in regions having different pattern densities. In a first etching, reactive ion etching (RIE) is performed upon a buffer layer and a hardmask layer both in a low-density pattern region and a high-density pattern region under a first etching ambient until an etch film is exposed in the low-density pattern region using mask patterns as an etch mask. In second etching for forming the hardmask patterns, using the mask patterns as an etch mask, the hardmask layer is etched until the etch film is exposed in the high-density pattern region while accumulating polymer by-products on the etch film in the low-density pattern region under a second etching ambient having polymer by-products produced greater than in the first etching ambient.

Abstract: A method of forming a metal contact and passivation of a semiconductor feature, and devices made using the method. The method comprises the steps of forming a dielectric mask on a semiconductor substrate utilising photolithography processes; etching the semiconductor substrate such that one or more features are formed underneath respective portions of the dielectric mask; depositing a passivation layer on the substrate with the dielectric mask in place above the features; subjecting the substrate to an etchant such that the dielectric mask is etched at a higher rate than the passivation layer, whereby portions of the passivation layer deposited on the dielectric mask are lifted off from the substrate; and depositing a metal layer on the substrate including over the remaining passivation layer and exposed portions of the features.

Abstract: A metal layer etch process deposits, patterns and anisotropically etches a polysilicon layer (24) down to an underlying metal layer (22) to form an etched polysilicon structure (54) with polymer layers (50, 52) formed on its sidewall surfaces. The polymer layer (50, 52) are removed to expose an additional surface area (60, 62) of the metal layer (22), and dielectric layers (80, 82) are formed on the sidewall surfaces of the etched polysilicon structure (54). Next, the metal layer (22) is plasma etched to form an etched metal layer (95) with substantially vertical sidewall surfaces (97, 99) by simultaneously charging the dielectric layers (80, 82) to change plasma ion trajectories near the dielectric layers (80, 82) so that plasma ions (92, 94) impact the sidewall surfaces (97, 99) in a more perpendicular angle to enhance etching of the sidewall surfaces (97, 99) of the etched metal layer (95).

Abstract: A method for forming a pattern of a semiconductor device comprises forming a spacer with an oxide film in a SPT process, and removing the spacer formed to have a horn shape before etching an underlying layer, so that the horn shape is transcribed in a lower portion, thereby facilitating control of critical dimension in etching the underlying layer so as to improve a characteristic of the device. A method for forming a pattern of a semiconductor device of the present invention comprises: forming an underlying layer and a hard mask layer over a semiconductor substrate; forming a sacrificial pattern over the hard mask layer; forming a spacer at both sides of the sacrificial pattern; removing the sacrificial pattern to remain the spacer; etching the hard mask layer with the spacer as a mask to form a hard mask pattern; removing the spacer; and etching the underlying layer with the hard mask pattern as a mask.

Abstract: In one embodiment, a tiered gate device is provided including a source, a drain, and a gate foot therebetween. A gate head is attached to the gate foot. A source extension extends from on the source toward the gate foot along the substrate. In some embodiments a drain extension extends from on the drain toward the gate foot along the substrate.

Abstract: A method for fabricating a semiconductor device having fine contact holes is exemplarily disclosed. The method includes forming an isolation layer defining active regions on a semiconductor substrate. An interlayer dielectric layer is formed on the semiconductor substrate having the isolation layer. First molding patterns are formed on the interlayer dielectric layer. Second molding patterns positioned between the first molding patterns and spaced apart therefrom are also formed. A mask pattern surrounding sidewalls of the first and second molding patterns is formed. Openings are formed by removing the first and second molding patterns. Contact holes are formed by etching the interlayer dielectric layer using the mask pattern as an etching mask.

Abstract: A method for manufacturing a memory device including a resistance change layer as a storage node according to example embodiment(s) of the present invention and a memory device made by the method(s) are provided. Pursuant to example embodiments of the present invention, the method may include stacking (sequentially or otherwise) a conductive material layer, a diode layer and a data storage layer on a bottom layer, forming a first material layer on the data storage layer, forming a first hole exposing the data storage layer in the first material layer, forming a first spacer with a second material layer on the sidewall of the first hole, filling the first hole with a third material layer and covering the first spacer; removing the first material layer, forming a second spacer with a fourth material layer on the sidewall of the first spacer; removing the third material layer, and forming a second hole exposing the bottom layer in a first stack structure using the first and second spacers as a mask.

Abstract: A method for forming a fine pattern of a semiconductor device comprises: forming a first hard mask film and an etch barrier film over a semiconductor substrate; forming a sacrificial pattern over the etch barrier film; forming a spacer on sidewalls of the sacrificial pattern; removing the sacrificial pattern; etching the etch barrier film and the hard mask film with the spacer as an etch mask to form an etch barrier pattern and a hard mask pattern; and removing the spacer and the etch barrier pattern, thereby improving yield and reliability of the device.