Abstract: An apparatus comprising a memory array comprising wordlines, digit lines, and memory cells, with each memory cell coupled to an associated wordline and an associated digit line. Each memory cell comprises a monocrystalline silicon material adjacent to an access device, a monocrystalline metal silicide material directly contacting the monocrystalline semiconductor material, a metal material directly contacting the monocrystalline metal silicide material, and a storage device adjacent to the metal material. Electronic devices, electronic systems, and methods of forming an electronic device are also disclosed.

Abstract: Embodiments are directed to methods and resulting structures for a vertical field effect transistor (VFET) having a super long channel. A pair of semiconductor fins is formed on a substrate. A semiconductor pillar is formed between the semiconductor fins on the substrate. A region that extends under all of the semiconductor fins and under part of the semiconductor pillar is doped. A conductive gate is formed over a channel region of the semiconductor fins and the semiconductor pillar. A surface of the semiconductor pillar serves as an extended channel region when the gate is active.

Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.

Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.

Abstract: A silicon carbide epitaxial substrate has a silicon carbide single-crystal substrate and a silicon carbide layer. An average value of carrier concentration in the silicon carbide layer is not less than 1×1015 cm?3 and not more than 5×10 cm?3. In-plane uniformity of the carrier concentration is not more than 2%. The second main surface has: a groove 80 extending in one direction along the second main surface, a width of the groove in the one direction being twice or more as large as a width thereof in a direction perpendicular to the one direction, and a maximum depth of the groove from the second main surface being not more than 10 nm; and a carrot defect. A value obtained by dividing a number of the carrot defects by a number of the grooves is not more than 1/500.

Abstract: Embodiments provide a method for manufacturing a bipolar junction transistor. The method comprises a step of providing a layer stack, the layer stack comprising a semiconductor substrate having a trench isolation, a base contact layer stack, wherein the base contact layer stack comprises a recess forming an emitter window, lateral spacers arranged on sidewalls of the emitter window, the lateral spacers isolating a base contact layer of the base contact layer stack; and a base layer arranged in the emitter window on the semiconductor substrate, wherein the base layer at least partially protrudes under the lateral spacers. The method further comprises a step of providing an isolation layer on the base layer.

Abstract: A carbon nanotube producing method, which is capable of realizing a low resistant depth-wise wiring. An acetylene gas is first supplied as a carbon-containing gas and subsequently, an ethylene gas is supplied as the carbon-containing gas such that carbon nanotubes are produced.

Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.

Abstract: A vertical transistor includes two portions of a gate conductor that extend within a layer of insulator. An opening extending through the later of insulator includes source, channel and drain regions form by epitaxy operations. A thickness of the portions of the gate conductor decreases in the vicinity of the channel region.

Abstract: Some embodiments include an integrated assembly having a first semiconductor structure containing heavily-doped silicon, a germanium-containing interface material over the first semiconductor structure, and a second semiconductor structure over the germanium-containing interface material. The second semiconductor structure has a heavily-doped lower region adjacent the germanium-containing interface material and has a lightly-doped upper region above the heavily-doped lower region. The lightly-doped upper region and heavily-doped lower region are majority doped to a same dopant type, and join to one another along a boundary region. Some embodiments include an integrated assembly having germanium oxide between a first silicon-containing structure and a second silicon-containing structure. Some embodiments include methods of forming assemblies.

Abstract: A semiconductor device includes a substrate; an n-type transistor including a first junction region positioned on the substrate, a first channel region positioned on the first junction region, a second junction region positioned on the first channel region, and a first gate stack at least partially surrounding the first channel region; and a p-type transistor including a third junction region positioned on the substrate, a second channel region positioned on the third junction region, a fourth junction region positioned on the second channel region, and a second gate stack at least partially surrounding the second channel region, in which the first channel region and the second channel region are epitaxial channel layers.

Abstract: A VCSEL array having a plurality of VCSELs, each having more than two modes, and the optical emission from each of the VCSELs overlaps in a far field of the VCSELs. A VCSEL array having a plurality of VCSELs, each having an aperture size of at least about 6 ?m, and the optical emission from each of the VCSELs overlaps in a far field of the VCSELs. A VCSEL array having a plurality of VCSELs, wherein the spectral width of each VCSEL is at least about 0.5 nm, and the optical emission from each of the VCSELs overlaps in a far field of the VCSELs.

Abstract: A method for forming a semiconductor device is disclosed. The method includes providing a semiconductor substrate. The method also includes epitaxially growing on the semiconductor substrate a first part of a III-V semiconductor nanostructure. The method further includes covering the first part of the III-V semiconductor nanostructure with a layer of a first material. Additionally, the method includes removing a top portion of the layer of the first material. Still further, the method includes epitaxially growing on the first part of the III-V semiconductor nanostructure a second part of the III-V semiconductor nanostructure. The method additionally includes covering the second part of the III-V semiconductor nanostructure with a layer of a second material. The second material is different from the first material. Even further, the method includes removing a top portion of the layer of the second material.

Abstract: A pixel cell has a photodiode, a readout circuit, a vertical transfer transistor and a reflective structure. The photodiode is disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit is disposed within a second substrate of a second semiconductor chip. The vertical transfer transistor is coupled between the photodiode and the readout circuitry to transfer the image charge from the photodiode to the readout circuitry. The reflective structure is positioned between the readout circuit and the photodiode to reflect incident light, that passes through the photodiode without being absorbed, back towards the photodiode for a second chance at being absorbed.

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a first distance from a first portion of the first type region. The semiconductor device includes a gate region surrounding the channel region. A first portion of the gate region is separated a second distance from the first portion of the first type region. The second distance is greater than the first distance.

Abstract: A pixel cell has a photodiode, a readout circuit, and a vertical transfer transistor. The photodiode is disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit is disposed within a second substrate of a second semiconductor chip. The vertical transfer transistor is coupled between the photodiode and the readout circuitry to transfer the image charge from the photodiode to the readout circuitry.

Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.

Abstract: In a method, a gate structure is formed over a substrate, and source/drain (S/D) features are formed in the substrate and interposed by the gate structure. At least one of the S/D features is formed by forming a first semiconductor material including physically discontinuous portions, forming a second semiconductor material over the first semiconductor material, and forming a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from a composition of the first semiconductor material. The third semiconductor material has a composition different from the composition of the second semiconductor material.

Abstract: A photodiode includes a semiconductor substrate, a crystalline layer on the semiconductor substrate, an insulating pattern layer on the crystalline layer to define a plurality of holes exposing a top surface of the crystalline layer, a seed layer in the plurality of holes and directly on the crystalline layer, and a light absorption layer on the seed layer and the insulating pattern layer.

Abstract: An integrated circuit includes a gate structure over a substrate. A silicon-containing material structure is in each of recesses that are adjacent to the gate structure. The silicon-containing material structure has a first region and a second region, the second region is closer to the gate structure than the first region, and the first region is thicker than the second region.

Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.

Abstract: The maximum value of peak intensities of cathode luminescence of a wavelength corresponding to a band gap of gallium nitride and in a measured visual field of 0.1 mm×0.1 mm is 140 percent or higher of an average value of the peak intensities of the cathode luminescence, provided that the peak intensities of the cathode luminescence are measured on a surface of the gallium nitride substrate.

Abstract: A change in electrical characteristics of a semiconductor device including an interlayer insulating film over a transistor including an oxide semiconductor as a semiconductor film is suppressed. The structure includes a first insulating film which includes a void portion in a step region formed by a source electrode and a drain electrode over the semiconductor film and contains silicon oxide as a component, and a second insulating film containing silicon nitride, which is provided in contact with the first insulating film to cover the void portion in the first insulating film. The structure can prevent the void portion generated in the first insulating film from expanding outward.

Abstract: The invention is a thermoelectric device fabricated by growing a single crystal AlInN semiconductor material on a substrate, and a method of fabricating same. In a preferred embodiment, the semiconductor material is AlInN grown on and lattice-matched to a GaN template on a sapphire substrate, and the growth is performed using metalorganic vapor phase epitaxy (MOVPE).

Abstract: Methods for fabricating semiconductor devices are provided. Gate structures are formed on a top surface of a substrate to form semiconductor devices. Trenches are formed in the substrate on both sides of each gate structure of each semiconductor device. The trenches on the both sides of each gate structure are filled with stress layers, the stress layers in the substrate protruding over the top surface of the substrate. The stress layers are ion-doped and annealed on the both sides of each gate structure, and are pulse-etched to form a source region and a drain region of each gate structure. The pulse-etching is controlled such that the source regions and the drain regions of the plurality of semiconductor devices have a top surface coplanar with the top surface of the substrate.

Abstract: A method for forming a semiconductor device comprises patterning and etching a fin in a semiconductor substrate, forming a gate stack over the fin, epitaxially growing a first semiconductor material on exposed portions of the fin, epitaxially growing a second semiconductor material on exposed portions of the first semiconductor material, and performing an etching process that removes exposed portions of the first semiconductor material and exposed portions of the second semiconductor material, the etching process is operative to remove portions of the first semiconductor material at a faster rate than the second semiconductor material such that a first cavity is formed adjacent to the fin.

Abstract: The present disclosure provides a method for manufacturing ordered nanowires array of NiO doped with Pt in situ, comprising: growing a Ni layer on a high-temperature resistant and insulated substrate; applying a photoresist on the Ni layer, pattering a pattern region of the ordered nanowires array by applying electron beam etching on the photoresist, growing Ni on the pattern region of the ordered nanowires array, peeling off the photoresist by acetone and etching the surface of the Ni layer by ion beam etching so as to etch off the Ni layer grown on the surface of the substrate and to leave the Ni on the pattern region of the ordered nanowires array to form the ordered Ni nanowires array; dipping the ordered Ni nanowires array into a solution of H2PtCl6 so as to displace Pt on the Ni nanowires array by a displacement reaction; and oxidizing the Ni nanowires array attached with Pt in an oxidation oven to obtain the ordered nanowires array of NiO doped with Pt.

Abstract: A method for forming a semiconductor device comprises patterning and etching a fin in a semiconductor substrate, forming a gate stack over the fin, epitaxially growing a first semiconductor material on exposed portions of the fin, epitaxially growing a second semiconductor material on exposed portions of the first semiconductor material, and performing an etching process that removes exposed portions of the first semiconductor material and exposed portions of the second semiconductor material, the etching process is operative to remove portions of the first semiconductor material at a faster rate than the second semiconductor material such that a first cavity is formed adjacent to the fin.

Abstract: Embodiments of the invention provide a fabricating method a thin film transistor, a thin film transistor and a display panel, so as to improve carrier mobility in the polycrystalline silicon.

Abstract: A method of forming transistors with close proximity stressors to channel regions of the transistors is provided. The method includes forming a first transistor, in a first region of a substrate, having a gate stack on top of the first region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the first region including a source and drain region of the first transistor; forming a second transistor, in a second region of the substrate, having a gate stack on top of the second region of the substrate and a set of spacers adjacent to sidewalls of the gate stack, the second region including a source and drain region of the second transistor; covering the first transistor with a photo-resist mask without covering the second transistor; creating recesses in the source and drain regions of the second transistor; and forming stressors in the recesses.

Abstract: A photo detector comprising a first doped impurity region (adapted to receive a first voltage) disposed in or on a substrate; a body region, juxtaposed the first doped impurity region; a gate (adapted to receive a second voltage) spaced from a first portion of the body region; a light absorbing region, juxtaposed a second portion of the body region, includes a material which, in response to light incident thereon, generates carrier pairs including a first and second type carriers; a contact region (adapted to receive a third voltage) juxtaposed the light absorbing region; wherein, in response to incident light, the gate attracts first type carriers of the carrier pairs to the first portion of the body region which causes second carriers from the first doped impurity region to flow to the contact region, and the contact region attracts second type carriers.

Abstract: A patterned substrate is provided having at least two mesa surface portions, and a recessed surface located beneath and positioned between the at least two mesa surface portions. A Group III nitride material is grown atop the mesa surface portions of the patterned substrate and atop the recessed surface. Growth of the Group III nitride material is continued merging the Group III nitride material that is grown atop the mesa surface portions. When the Group III nitride material located atop the mesa surface portions merge, the Group III nitride material growth on the recessed surface ceases. The merged Group III nitride material forms a first Group III nitride material structure, and the Group III nitride material formed in the recessed surface forms a second material structure. The first and second material structures are disjoined from each other and are separated by an air gap.

Abstract: In a method for making a GaN article, an epitaxial nitride layer is deposited on a single-crystal substrate. A 3D nucleation GaN layer is grown on the epitaxial nitride layer by HVPE under a substantially 3D growth mode. A GaN transitional layer is grown on the 3D nucleation layer by HVPE under a condition that changes the growth mode from the substantially 3D growth mode to a substantially 2D growth mode. A bulk GaN layer is grown on the transitional layer by HVPE under the substantially 2D growth mode. A polycrystalline GaN layer is grown on the bulk GaN layer to form a GaN/substrate bi-layer. The GaN/substrate bi-layer may be cooled from the growth temperature to an ambient temperature, wherein GaN material cracks laterally and separates from the substrate, forming a free-standing article.

Abstract: Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern.

Abstract: A multilayered structure is provided. The multilayered structure may include a silicon substrate and a film of gadolinium oxide disposed on the silicon substrate. The top surface of the silicon substrate may have silicon orientated in the 100 direction (Si(100)) and the gadolinium oxide disposed thereon may have an orientation in the 100 direction (Gd2O3(100)).

Abstract: A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin. An Inter-Layer Dielectric (ILD) is formed to cover end portions of the semiconductor fin. The dummy gate is then removed to form a first recess, wherein the middle portion is exposed to the first recess. The middle portion of the semiconductor fin is removed to form a second recess. An epitaxy is performed to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions. A gate dielectric and a gate electrode are formed in the first recess. The gate dielectric and the gate electrode are over the semiconductor material.

Abstract: A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material.

Abstract: Solid state lighting devices and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and a plurality of hemispherical grained silicon (“HSG”) structures on the substrate surface of the substrate material. The solid state lighting device also includes a semiconductor material on the substrate material, at least a portion of which is between the plurality of HSG structures.

Abstract: Disclosed are a method for fabricating a quantum dot. The method includes the steps of (a) preparing a compound semiconductor layer including a quantum well structure formed by sequentially stacking a first barrier layer, a well layer and a second barrier layer; (b) forming a dielectric thin film pattern including a first dielectric thin film having a thermal expansion coefficient higher than a thermal expansion coefficient of the second barrier layer and a second dielectric thin film having a thermal expansion coefficient lower than the thermal expansion coefficient of the second barrier layer on the second barrier layer; and (c) heat-treating the compound semiconductor layer formed thereon with the dielectric thin film pattern to cause an intermixing between elements of the well layer and elements of the barrier layers at a region of the compound semiconductor layer under the second dielectric thin film.

Abstract: The invention includes methods of forming layers comprising epitaxial silicon. In one implementation, an opening is formed within a first material received over a monocrystalline material. Opposing sidewalls of the opening are lined with a second material, with monocrystalline material being exposed at a base of the second material-lined opening. A silicon-comprising layer is epitaxially grown from the exposed monocrystalline material within the second material-lined opening. At least a portion of the second material lining is in situ removed. Other aspects and implementations are contemplated.

Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.

Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain\-inducing semiconductor material, superior uniformity may be achieved by using an implantation process so as to selectively modify the etch behavior of exposed portions of the active region. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility, while at the same time the dependence on pattern loading effect may be reduced. Consequently, a significantly reduced variability of transistor characteristics may be achieved.

Abstract: A semiconductor device, including a device isolation layer arranged on a predetermined region of a semiconductor substrate to define an active region, the active region including a central top surface of a (100) crystal plane and an inclined edge surface extending from the central top surface to the device isolation layer, a semiconductor pattern covering the central top surface and the inclined edge surface of the active region, the semiconductor pattern including a flat top surface of a (100) crystal plane that is parallel with the central top surface of the active region and a sidewall that is substantially perpendicular to the flat top surface, and a gate pattern overlapping the semiconductor pattern.

Abstract: A unit pixel of an image sensor and a photo detector are disclosed. The photo detector of the present invention configured to absorb light can include: a light-absorbing part configured to absorb light by being formed in a floated structure; an oxide film being in contact with one surface of the light-absorbing part; a source being in contact with one side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; a drain facing the source so as to be in contact with the other side of the other surface of the oxide film and separated from the light-absorbing part with the oxide film therebetween; and a channel interposed between the source and the drain and configured to form flow of an electric current between the source and the drain.

Abstract: A method for selectively growing a nitride semiconductor, in which a mask is formed, with an opening formed therein, on a nitride semiconductor layer. A nitride semiconductor crystal is selectively grown on a portion of the nitride semiconductor layer exposed through the opening in the mask, the nitride semiconductor crystal shaped as a hexagonal pyramid and having crystal planes inclined with respect to a top surface of the nitride semiconductor. Here, the nitride semiconductor crystal has at least one intermediate stress-relieving area having crystal planes inclined at a greater angle than those of upper and lower areas of the nitride semiconductor crystal, the intermediate stress-relieving area relieving stress which occurs from continuity in the inclined crystal planes.

Abstract: Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (?Ec) ranging from 0.05-0.6 eV; patterning an epitaxy mask on the semi-insulating layer, wherein the epitaxy mask has a reverse image of a desired pattern of the fin; performing a selective epitaxial growth within the epitaxy mask; and removing the epitaxy mask such that the fin remains on the semi-insulating layer. The semi-insulating layer comprises, for example, a III-V semiconductor material and optionally further comprises a Si ?-doping layer to supply electron carriers to the III-V channel.

Abstract: Improved Fin Field Effect Transistors (FinFET) are provided, as well as improved techniques for forming fins for a FinFET. A fin for a FinFET is formed by forming a semi-insulating layer on an insulator that gives a sufficiently large conduction band offset (?Ee) ranging from 0.05-0.6 eV; patterning an epitaxy mask on the semi-insulating layer, wherein the epitaxy mask has a reverse image of a desired pattern of the fin; performing a selective epitaxial growth within the epitaxy mask; and removing the epitaxy mask such that the fin remains on the semi-insulating layer. The semi-insulating layer comprises, for example, a III-V semiconductor material and optionally further comprises a Si ?-doping layer to supply electron carriers to the III-V channel.

Abstract: A method is disclosed comprising providing a substrate comprising an insulating material and a second semiconductor material and pre-treating the substrate with a plasma produced from a gas selected from the group consisting of a carbon-containing gas, a halogen-containing gas, and a carbon-and-halogen containing gas. The method further comprises depositing a first semiconductor material on the pre-treated substrate by chemical vapor deposition, where the first semiconductor material is selectively deposited on the second semiconductor material. The method may be used to manufacture a semiconducting device, such as a microelectromechanical system device, or to manufacture a semiconducting device feature, such as an interconnect.

Abstract: A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.