Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: forming an active region on a substrate; forming at least one trench in the active region, the trench at least dividing the active region into a source region on one side of the trench and a drain region on the other side of the trench; and forming an elevated source region and an elevated drain region on the source region and the drain region respectively.

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, and a gate contact in the gate structure. The gate structure includes a gate electrode extending in a first direction and a gate capping pattern on the gate electrode. The gate contact is connected to the gate electrode. The gate electrode includes a protrusion extending along a boundary between the gate contact and the gate capping pattern.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) structure with a bipolar transistor stack within a substrate. The bipolar transistor stack may include: a collector, a base on the collector, and an emitter on a first portion of the base. A horizontal width of the emitter is less than a horizontal width of the base, and an upper surface of the emitter is substantially coplanar with an upper surface of the substrate. An extrinsic base structure is on a second portion of the base of the bipolar transistor stack, and horizontally adjacent the emitter. The extrinsic base structure includes an upper surface above the upper surface of the substrate.

Abstract: A method includes forming a dummy gate stack over a substrate; forming a gate spacer on a sidewall of the dummy gate stack; after forming the gate spacer, forming a source/drain region in the substrate and adjacent to the gate spacer; forming a first interlayer dielectric layer over the source/drain region and adjacent to the gate spacer; replacing the dummy gate stack with a metal gate stack; forming a protective layer over the metal gate stack and the gate spacer; after forming the protective layer, removing the first interlayer dielectric layer to expose a sidewall of the gate spacer and a sidewall of the protective layer; and forming a bottom conductive feature over the source/drain region.

Abstract: Methods of forming a DRAM bit line to improve line edge roughness (LER) and lower resistance are described. The method comprises implanting an inert species into a bit line metal layer having a first grain size on a substrate to form an amorphized bit line metal layer having a second grain size smaller than the first grain size. A film stack is then deposited on the amorphized bit line metal layer. The film stack and amorphized bit line metal layer are etched to form a patterned film stack on the substrate. The patterned film stack on the substrate is thermally annealed.

Abstract: A fully depleted silicon on insulator (FDSOI) is employed to reduce diffusion leakage (e.g., gate induced drain leakage, junction leakage, etc.) associated with the diffusion regions of a pixel cell. The buried oxide (BOX) layer, for example, fully isolates the transistor channel region, such as an (N) channel region of the pixel cell from the photodiode(s) of the pixel region, eliminating the junction leakage path, thus leading to a reduction in diffusion leakage and an increase device operation speed. An increase of full well capacity can also be realized by the absence of isolation structure, such as trench isolation or isolation implant structure.

Abstract: An ammonium fluoride gas may be used to form a protection layer for one or more interlayer dielectric layers, one or more insulating caps, and/or one or more source/drain regions of a semiconductor device during a pre-clean etch process. The protection layer can be formed through an oversupply of nitrogen trifluoride during the pre-clean etch process. The oversupply of nitrogen trifluoride causes an increased formation of ammonium fluoride, which coats the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) with a thick protection layer. The protection layer protects the interlayer dielectric layer(s), the insulating cap(s), and/or the source/drain region(s) during the pre-clean process from being etched by fluorine ions formed during the pre-clean process.

Abstract: Aspects of the disclosure provide a method including depositing an underlayer comprising silicon oxide over a substrate, depositing a polysilicon liner on the underlayer, and depositing an amorphous silicon layer on the polysilicon liner. Aspects of the disclosure provide a device intermediate including a substrate, an underlayer comprising silicon oxide formed over the substrate, a polysilicon liner disposed on the underlayer, and an amorphous silicon layer disposed on the polysilicon liner.

Abstract: A semiconductor package includes a semiconductor chip including a connection pad disposed on an active surface of the semiconductor chip, a passivation layer disposed on the connection pad and the active surface and having an opening exposing at least a portion of the connection pad, and a capping pad covering the connection pad exposed to the opening; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the active surface of the semiconductor chip and including a connection via connected to the capping pad and a redistribution layer connected to the connection via, wherein the capping pad includes: a central portion disposed in the opening, and a peripheral portion extending from the central portion onto the passivation layer, and having a crystal grain having a size different from that of the crystal grain of the central portion.

Abstract: Provided is a Chemical vapor deposition (CVD) equipment including a chamber having an inner space, a plurality of silicon wafers disposed in the inner space of the chamber in an upright position; and a plurality of shower nozzles configured to inject a mixed gas composed of a silicon deposition gas and an impurity gas toward each side edge of the plurality of wafers. The plurality of shower nozzles can be disposed at both sides of the plurality of the plurality of silicon wafers.

Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the IC. Fins on pedestals are defined, e.g., with a hard mask, in a fin layer on a semiconductor wafer and spaces between the pedestals are filled with dielectric material, e.g., shallow trench isolation (STI). Sacrificial sidewalls are formed along the sides of fins and pedestal sub-fins sidewalls are re-exposed. Pedestal sub-fins are doped with a punch-though dopant and punch-though dopant is diffused into the sub-fins and the bottoms of fins. After removing the hard mask and sacrificial sidewalls, metal FET gates are formed on the fins.

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer is arranged over the active region, and a semiconductor layer is arranged on the base layer. The semiconductor layer includes a stepped profile with a first section having a first width adjacent to the base layer and a second section having a second width that is less than the first width. An emitter is arranged on the second section of the semiconductor layer.

Abstract: Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.

Abstract: A semiconductor device includes a first interlayer dielectric film on a substrate, first and second wires respectively extending in a first direction within the first interlayer dielectric film, the first and second wires being adjacent to each other in a second direction different from the first direction, a hard mask pattern on the first interlayer dielectric film, the hard mask pattern including an opening, and an air gap within the first interlayer dielectric film, the air gap including a first portion overlapping vertically with the opening and a second portion not overlapping with the opening in the first direction.

Abstract: A semiconductor device includes an active region in a semiconductor substrate. A gate electrode is disposed over and crossing the active region. The active region includes a channel region, a source region and a drain region. A bottom conductive feature is disposed on the active region. A helmet layer is disposed on the gate electrode. A contact etch stop layer is disposed on a portion of the helmet layer. A first contact plug is disposed on the bottom conductive feature and the remaining portion of the helmet layer. A hard mask is disposed on the gate electrode. An etching selectivity between the helmet layer and the hard mask is larger than approximately 10.

Abstract: Enhanced printing solutions are enabled by providing ultraviolet curing conditions without requiring complete evacuation of atmospheric oxygen. Increased ink coverage and adjusted surface appearance are also provided.

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory cell thereof are provided. The semiconductor memory device formed from the manufacturing method includes a plurality of semiconductor memory cells and an electric isolating structure. Each semiconductor memory cell includes a substrate, a first gate, a second gate, a first gate dielectric layer, a second gate dielectric layer, and a first spacing film. The first gate and the second gate are formed on the substrate. The first gate dielectric layer is between the first gate and the substrate, whereas the second gate dielectric layer is between the second gate and the substrate. The first spacing film having a side and a top edge is between the first gate and the second gate. The second gate covers the side and the top edge.

Abstract: The disclosure relates to integrated circuit (IC) fabrication techniques. Methods according to the disclosure can include: forming a reaction layer on the upper surface of a conductor, the upper surface of a refractory metal liner, and the upper surface of an insulator layer; annealing the reaction layer such that a portion of the reaction layer reacts with the conductor to form a semiconductor-metal alloy region; removing a portion of the reaction layer to expose the refractory metal liner; removing a portion of the refractory metal liner to approximately a depth of the semiconductor-metal alloy region; and removing the semiconductor-metal alloy region to expose a portion of the conductor such that a remainder of the conductor and a remainder of the refractory metal liner are recessed relative to an upper surface of the insulator layer.

Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

Abstract: An integrated circuit wafer and fabrication method includes a probe pad structure in saw lanes between integrated circuits. The probe pad structure includes a probe pad with a plurality of pad segments. The pad segments are elements of an interconnect level of the wafer.

Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first gate structure formed over a substrate. The semiconductor structure includes a first spacer formed on a sidewall of the first gate structure. In addition, a top surface of the first spacer is parallel to a top surface of the substrate.

Abstract: A method of silicide formation in a semiconductor fabrication process is disclosed. An active area (RX) mask is used to form an active silicon area, and is then reused to form a trench transfer (TT) area. A trench block (TB) mask is logically ANDed with the active area (RX) mask to form a trench silicide (TS) region.

Abstract: Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA.

Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.

Abstract: A method is described what includes providing a substrate having a first trench and a second trench. An epitaxy material (crystalline material) is formed in the first trench and in the second trench. The top surface of the epitaxy material in the first trench is noncollinear with a top surface of the epitaxy material in the second trench. An amorphous semiconductor layer is formed on the crystalline material. Subsequently, the amorphous layer is converted, in part or in whole, into the crystalline semiconductor material. In an embodiment, a planarization process after the conversion provides crystalline regions having a coplanar top surface.

Abstract: A method for forming a semiconductor device includes physically attaching a first semiconductor die to front surface of a first substrate. The first die is electrically connected to routings on front surface of the first substrate. The routings are electrically connected with conductive pads on back surface of the first substrate. A second semiconductor die is physically attached to front surface of a second substrate. The die is electrically connected to routings on front surface of second substrate. These routings are electrically connected with conductive pads on front surface of the second substrate. A third semiconductor die is physically attached to the second die. The third die is electrically attached to the second die through a plurality of through substrate vias (TSVs) within the second die. The conductive pads on back surface of first substrate are electrically connected to the conductive pads on front surface of second substrate.

Abstract: In a manufacture method for a photovoltaic module, a plurality of strips of resin adhesive film having a desired width and unwound from a single feeding reel is simultaneously pasted on a solar cell. In particular, the manufacture method is implemented by performing the steps of: unwinding a resin adhesive film sheet from a reel on which the resin adhesive film sheet is wound; splitting the unwound resin adhesive film into two or more film strips in correspondence to lengths of wiring material to bond; pasting the strips of resin adhesive film on an electrode of the solar cell; and placing the individual lengths of wiring material on the electrode of the solar cell having the plural strips of resin adhesive film pasted thereon and thermally setting the resin adhesive film by heating so as to fix together the electrode of the solar cell and the wiring material.

Abstract: Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA.

Abstract: Integrated circuit devices include a semiconductor substrate having a plurality of trench isolation regions therein that define respective semiconductor active regions therebetween. A trench is provided in the semiconductor substrate. The trench has first and second opposing sidewalls that define opposing interfaces with a first trench isolation region and a first active region, respectively. A first electrical interconnect is provided at a bottom of the trench. An electrically insulating capping pattern is provided, which extends between the first electrical interconnect and a top of the trench. An interconnect insulating layer is also provided, which lines the first and second sidewalls and bottom of the trench. The interconnect insulating layer extends between the first electrical interconnect and the first active region. A recess is provided in the first active region. The recess has a sidewall that defines an interface with the interconnect insulating layer.

Abstract: In one aspect of this invention, a pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode having a first portion and a second portion extending from the first portion, and formed over the scan line, the data line and the switch, where the first portion is overlapped with the switch and the second portion is overlapped with the data line, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode in the pixel area, where the first portion is overlapped with the first portion of the shielding electrode so as to define a storage capacitor therebetween and the second portion has no overlapping with the second portion of the shielding electrode.

Abstract: A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug comprises a first region, a second region, a third region, and a fourth region, wherein the first region is disposed beneath the second region and doped with a first doping concentration, the second region is disposed above the first region and below the third region and is not doped, the third region is disposed above the second region and below the fourth region and is doped with a second doping concentration that is lower than the first doping concentration, and the fourth region is disposed above the third region and is doped with a third doping concentration that is higher than the first doping concentration; and annealing the resulting product formed with the landing

Abstract: A semiconductor device including a first memory die having a first memory type, a second memory die having a second memory type different from the first memory type, and a logic die such as a microprocessor. The first memory die can be electrically connected to the logic die using a first type of electrical connection preferred for the first memory type. The second memory die can be electrically connected to the logic die using a second type of electrical connection different from the first type of electrical connection which is preferred for the second memory type. Other devices can include dies all of the same type, or two or more dies of a first type and two or more dies of a second type different from the first type.

Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

Abstract: The invention permits a plurality of strips of resin adhesive film having a desired width and unwound from a single feeding reel to be simultaneously pasted on a solar cell. For this purpose, the invention comprises the steps of: unwinding a resin adhesive film sheet from a reel on which the resin adhesive film sheet is wound; splitting the unwound resin adhesive film into two or more film strips in correspondence to lengths of wiring material to bond; pasting the strips of resin adhesive film on an electrode of the solar cell; and placing the individual lengths of wiring material on the electrode of the solar cell having the plural strips of resin adhesive film pasted thereon and thermally setting the resin adhesive film by heating so as to fix together the electrode of the solar cell and the wiring material.

Abstract: A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug is divided into a first region, a second region, a third region, and a fourth region from a lower portion of the landing plug, and the first region is doped with a first doping concentration that is relatively lowest, the second region is doped with a second doping concentration that is higher than the first doping concentration, the third region is doped with a third doping concentration that is higher than the second doping concentration and the fourth region is not doped; and annealing the resulting product formed with the landing plug.

Abstract: The present invention connects a first wiring portion located at one side of a substrate and a second wiring portion located at the other side. A side electrode connected to the first wiring portion is formed, and the second wiring portion is formed on an insulating layer formed on the substrate. An exposed end of the second wiring portion formed when singulated into individual semiconductor package and the side electrode are wired by ink jet system using nano metal particles. Particularly, when copper is used, the wiring by the ink jet system is performed by the reduction of a metal surface oxidation film and/or removal of organic matters by atomic hydrogen.

Abstract: A dual gate of a semiconductor device includes a semiconductor substrate divided into a cell region with a recessed gate forming area and a peripheral region with PMOS and NMOS forming areas; first and second conductive type SiGe layers, the first conductive type SiGe layer being formed over the cell region and the PMOS forming area of the peripheral region, and the second conductive type SiGe layer being formed over the NMOS forming area of the peripheral region; first and second conductive type polysilicon layers, the first conductive type polysilicon layer being formed over the first conductive type SiGe layer and the second conductive type polysilicon layer being formed over the second conductive type SiGe layer; and a metallic layer and a hard mask layer stacked over the first and second conductive type polysilicon layers.

Abstract: A method for manufacturing a DRAM device on a silicon substrate includes: forming cell transistors in a memory cell area and other transistors in a peripheral circuit area; forming polysilicon plugs connected to diffused regions of the cell transistors and metallic plugs connected to diffused regions of the other transistors; heat treating at a temperature of 980 to 1,020 degrees C.; heat treating at a temperature of 700 to 850 degrees C.; implanting fluorine or boron fluoride into the diffused regions of the other transistors; and heat treating at a temperature of 500 to 850 degrees C.

Abstract: Interconnect structures including liner layers that are non-planar with at least the adjacent insulating layer and at least one capping layer on conductive features embedded in the insulating layer. The interconnect structure includes an insulating layer of a dielectric material having a top surface and a bottom surface between the top surface and a substrate. An opening, such as a trench, has sidewalls extending from the top surface of the insulating layer toward the bottom surface and is at least partially filled by a conductive feature. A capping layer is disposed on at least a top surface of the conductive feature. A conductive liner layer is disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer has sidewall portions projecting above the top surface of the insulating layer adjacent to the sidewalls of the opening.

Abstract: Disclosed is a structure and method for tuning silicide stress and, particularly, for developing a tensile silicide region on a gate conductor of an n-FET in order to optimize n-FET performance. More particularly, a first metal layer-protective cap layer-second metal layer stack is formed on an n-FET structure. However, prior to the deposition of the second metal layer, the protective layer is exposed to air. This air break step alters the adhesion between the protective cap layer and the second metal layer and thereby, effects the stress imparted upon the first metal layer during silicide formation. The result is a more tensile silicide that is optimal for n-FET performance.

Abstract: A method for preparing a doped polysilicon conductor according to this aspect of the present invention comprises the steps of (a) placing a substrate in a reaction chamber, (b) performing a deposition process to form a polysilicon layer on the substrate, (c) performing a grain growth process to form a plurality of polysilicon grains on the polysilicon layer, and (d) performing a dopant diffusion process to diffuse conductive dopants into the polysilicon layer via the polysilicon grains to form the doped polysilicon conductor.

Abstract: A light emitting device and a method of manufacturing the same are provided. A light emitting device has a structure wherein a substrate, an n-type clad layer, a light emitting layer, a p-type clad layer, an ohmic contact layer, and a reflective layer are successively stacked. The ohmic contact layer is formed by adding an additional element to an indium oxide. According to the light emitting device and the method of manufacturing the same, the characteristics of ohmic contact with a p-type clad layer is improved, thus increasing the efficiency and yield of wire bonding during packaging FCLEDS. Also, it is possible to increase the light emitting efficiency and life span of light emitting devices due to the low contactless resistance and the excellent electric current and voltage characteristic.

Abstract: The invention provides a manufacturing method of a circular thin film transistor of which shape is more controlled than the conventional case, while simplifying the steps and reducing the manufacturing time and cost by forming a circular thin film transistor by a maskless process such as a droplet discharge method. In the invention, a circular thin film transistor having a circular electrode is formed by stacking concentric circular thin films over a substrate by a maskless process such as a droplet discharge method. Moreover, a circular thin film transistor having a circular semiconductor layer may be formed by stacking concentric circular thin films over a substrate by a maskless process such as a droplet discharge method.

Abstract: A method to selectively etch, and hence pattern, a semiconductor film deposited non-selectively is described. In one embodiment, a carbon-doped silicon film is deposited non-selectively such that the film forms an epitaxial region where deposited on a crystalline surface and an amorphous region where deposited on an amorphous surface. A four-component wet etch mixture is tuned to selectively etch the amorphous region while retaining the epitaxial region, wherein the four-component wet etch mixture comprises an oxidizing agent, an etchant, a buffer and a diluent.

Abstract: For avoiding the metallic inner surface of a PECVD reactor to influence thickness uniformity and quality uniformity of a ?c-Si layer (19) deposited on a large-surface substrate, (15) before each substrate is single treated at least parts of the addressed wall are precoated with a dielectric layer (13).

Abstract: A method of manufacturing a semiconductor device having the steps of forming an insulating layer on a silicon substrate, forming a contact hole on the insulating layer, forming a selective silicon layer in the contact hole, and forming a selective conductive plug on the selective silicon layer.