Abstract: In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.

Abstract: There is provided an underlayer coating that causes no intermixing with photoresist layer, can be formed by a spin-coating method, and can be used as a hard mask in lithography process of manufacture of semiconductor device. Concretely, it is an underlayer coating forming composition used in manufacture of semiconductor device including metal nitride particles having an average particle diameter of 1 to 1000 nm, and an organic solvent. The metal nitride particles contain at least one element selected from the group consisting of titanium, silicon, tantalum, tungsten, cerium, germanium, hafnium, and gallium.

Abstract: The invention includes methods of forming implant regions between and/or under transistor gates. In one aspect, a pair of transistor gates is partially formed, and a layer of conductive material is left extending between the transistor gates. A dopant is implanted through the conductive material to form at least one implant region between and/or beneath the partially formed transistor gates, and subsequently the conductive material is removed from between the gates. The gates can be incorporated into various semiconductor assemblies, including, for example, DRAM assemblies.

Abstract: A method for manufacturing a semiconductor device by a small number of processes and by a means with high usability of materials to have high-definition and a gate insulating with a high step coverage property is disclosed. According to the present invention, a method for manufacturing a semiconductor device comprises the steps of forming a plurality of first conductive layers over a substrate; forming a first insulating layer to fill the gaps of the plurality of the first conductive layers; forming a second insulating layer over the first insulating layer and the plurality of the first conductive layers; and forming a semiconductor region and a second conductive layer over the second insulating layer.

Abstract: In an exemplary embodiment, a fin active region is protruded along one direction from a bulk silicon substrate on which a shallow trench insulator is entirely formed so as to cover the fin active region. The shallow trench insulator is removed to selectively expose an upper part and sidewall of the fin active region, along a line shape that at least one time crosses with the fin active region, thus forming a trench. The fin active region is exposed by the trench and thereon a gate insulation layer is formed. Thereby, productivity is increased and performance of the device is improved. A fin FET employs a bulk silicon substrate of which a manufacturing cost is lower than that of a conventional SOI type silicon substrate. Also, a floating body effect can be prevented, or is substantially reduced.

Abstract: The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.