Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Abstract: A method for manufacturing a semiconductor device includes a gate dielectric film formed over an active area of a semiconductor substrate, and a gate electrode formed over the gate dielectric film and formed of a silicidation film having a polysilicon area at the bottom of the gate electrode. Therefore, with embodiments, a work function can variously controlled and the gate pattern having different work function can be applied to the transistors by using a non-silicided polysilicon region due to the formation a partially silicided gate pattern, such that the resistance of the gate electrode and junction can be reduced, making it possible to maximize the device characteristics.

Abstract: A method of forming word lines of a memory includes providing a substrate and forming a conductive layer on the substrate. A metal silicide layer is formed on the conductive layer, and a mask pattern is formed on the metal silicide layer. A mask liner covering the mask pattern and the surface of the metal silicide layer is formed on the substrate to shorten distances between the word line regions. An etching process is performed on the mask liner and the mask pattern until the partial surface of the metal silicide layer is exposed. The metal silicide layer and the conductive layer are etched to form word lines by utilizing the mask liner and the mask pattern as a mask. A silicon content of the metal silicide layer must be less than or equal to 2 for reducing a bridge failure rate between the word lines.

Abstract: A semiconductor device and a manufacturing method thereof that can prevent mutual diffusion of impurity in a silicide layer and can decrease sheet resistance of an N-type polymetal gate electrode and a P-type polymetal gate electrode, respectively in the semiconductor device having gate electrodes of a polymetal gate structure and a dual gate structure are provided. The P-type polymetal gate electrode includes a P-type silicon layer containing P-type impurity, a silicide layer formed on the P-type silicon layer and having a plurality of silicide grains which are discontinuously disposed in a direction substantially parallel with the surface of the semiconductor substrate, a silicon film continuously formed on the surface of the P-type silicon layer exposed on the discontinuous part of the silicide layer and on the surface of the silicide layer, a second metal nitride layer formed on the silicon film, and a metal layer formed on the metal nitride layer.

Abstract: Methods of forming a metal salicide layer can include forming a metal layer on a substrate and forming a metal silicide layer on the metal layer using a first thermal process at a first temperature. Then a second process is performed, in-situ with the first thermal process, on the metal layer at a second temperature that is less than the first temperature.

Abstract: A method of manufacturing a semiconductor device includes providing a first layer over a wafer substrate, providing a polysilicon layer over the first layer, implanting nitrogen ions into the polysilicon layer, forming a polycide layer over the polysilicon layer, and forming source and drain regions.

Abstract: The width of the gate of a MOS transistor can be formed to have nanometer-width gate sizes, which are substantially less than the minimum feature size that can be photolithographically obtained with the method that is used to fabricate the MOS transistors, in a litho-less process by utilizing a conductive side wall spacer to form the gate of the MOS transistor.

Abstract: A semiconductor device is provided. A transistor is formed on a substrate, and a metal silicide layer is formed on the surface of a gate conductor layer and a source/drain region. Next, a surface treatment process is performed to selectively form a protection layer on the surface of the metal silicide layer. Then, a spacer of the transistor is partially removed using the protection layer as a mask, so as to reduce the width of the spacer. Then, a stress layer is formed on the substrate.

Abstract: Fully and uniformly silicided gate conductors are produced by deeply “perforating” silicide gate conductors with sub-lithographic, sub-critical dimension, nanometer-scale openings. A silicide-forming metal (e.g. cobalt, tungsten, etc.) is then deposited, polysilicon gates, covering them and filling the perforations. An anneal step converts the polysilicon to silicide. Because of the deep perforations, the surface area of polysilicon in contact with the silicide-forming metal is greatly increased over conventional silicidation techniques, causing the polysilicon gate to be fully converted to a uniform silicide composition. A self-assembling diblock copolymer is used to form a regular sub-lithographic nanometer-scale pattern that is used as an etching “template” for forming the perforations.

Abstract: A network element (10), such as a Packet Data Serving Node, detects (31) a change in operational status of a mobile station during a communication session and, in response to detecting such a change, automatically increases (32) memory capacity as is available to support additional communication sessions while simultaneously persisting at least some session information for potential subsequent use during the communication session. For example, this response can occur upon detecting that a mobile station has changed from an active to a dormant status. Then, upon returning to an active status, the network element can use the persisted information to facilitate rapid reconstruction of infrastructure support for the mobile station's call participation.

Abstract: A method of manufacturing a semiconductor device includes forming a first conductive film on a semiconductor substrate via a first insulating film; forming a second conductive film on the first conductive film via a second insulating film; patterning the first and the second conductive films and the second insulating film to form a plurality of gate electrodes; filling a third insulating film between the plurality of gate electrodes; exposing an upper portion of the second conductive film by removing the third insulating film; covering surfaces of the exposed upper portion of the second conductive film with fluoride (F) or carbon (C) or oxygen (O); and forming a metal film on an upper surface of the second conductive film; and forming silicide layers on the upper portion of the second conductive films by thermally treating the metal film.

Abstract: The disclosure provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming a layer of gate electrode material over a layer of gate dielectric material, wherein the layer of gate dielectric material is positioned over a substrate. This method further includes patterning the layer of gate electrode material and the layer of gate dielectric material into an NMOS gate structure, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode. This method further includes forming n-type source/drain regions within the substrate proximate the NMOS gate structure, and siliciding the NMOS gate electrode to form a silicided gate electrode. This method additionally includes placing a p-type dopant within the layer of gate electrode material or the NMOS gate electrode prior to or concurrently with siliciding.

Abstract: The invention provides a semiconductor device and method of manufacture therefore. The method for manufacturing the semiconductor device, in one embodiment, includes forming an NMOS gate structure over a substrate, wherein the NMOS gate structure includes an NMOS gate dielectric and an NMOS gate electrode. The method further includes forming n-type source/drain regions within the substrate proximate the NMOS gate structure, and forming a metal alloy layer over the NMOS gate electrode. The method additionally includes incorporating the metal alloy into the NMOS gate electrode to form an NMOS gate electrode fully silicided with the metal alloy.

Abstract: A method and apparatus are provided in which non-directional and directional metal (e.g. Ni) deposition steps are performed in the same process chamber. A first plasma is formed for removing material from a target; a secondary plasma for increasing ion density in the material is formed in the interior of an annular electrode (e.g. a Ni ring) connected to an RF generator. Material is deposited non-directionally on the substrate in the absence of the secondary plasma and electrical biasing of the substrate, and deposited directionally when the secondary plasma is present and the substrate is electrically biased. Nickel silicide formed from the deposited metal has a lower gate polysilicon sheet resistance and may have a lower density of pipe defects than NiSi formed from metal deposited in a solely directional process, and has a lower source/drain contact resistance than NiSi formed from metal deposited in a solely non-directional process.

Abstract: The present invention provides a method for producing thin nickel (Ni) monosilicide or NiSi films (having a thickness on the order of about 30 nm or less), as contacts in CMOS devices wherein an amorphous Ni alloy silicide layer is formed during annealing which eliminates (i.e., completely by-passing) the formation of metal-rich silicide layers. By eliminating the formation of the metal-rich silicide layers, the resultant NiSi film formed has improved surface roughness as compared to a NiSi film formed from a metal-rich silicide phase. The method of the present invention also forms Ni monosilicide films without experiencing any dependence of the dopant type concentration within the Si-containing substrate that exists with the prior art NiSi films.

Abstract: A method of fabricating a gate electrode for a semiconductor comprising the steps of: providing a substrate; providing on the substrate a layer of a first material of thickness tp, the first material being selected from the group consisting of Si, Si1-x—Gex alloy, Ge and mixtures thereof and a layer of metal of thickness tm; and annealing the layers, such that substantially all of the first material and the metal are consumed during reaction with one another.

Abstract: A fully-silicided gate electrode is formed from silicon and a metal by depositing at least two layers of silicon with the metal layer therebetween. One of the silicon layers may be amorphous silicon whereas the other silicon layer may be polycrystalline silicon. The silicon between the metal layer and the gate dielectric may be deposited in two layers having different crystallinities. This process enables greater control to be exercised over the phase of the silicide resulting from this silicidation process.

Abstract: Semiconductor devices and methods for fabricating the same are disclosed in which an amorphous layer is formed in an interface between a device isolation layer and a source or drain region to stably thin a silicide layer formed in the interface. A leakage current of the silicide layer formed in the interface between the device isolation layer and the source/drain region is reduced.

Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.

Abstract: A semiconductor device incorporating an alloy layer formed on a substrate; a gate electrode, a source electrode, and a drain electrode formed on the alloy layer at predetermined intervals therebetween; a gate insulating layer formed on the gate electrode in a gate electrode region; a first conductive layer formed on the substrate, including the source electrode and the drain electrode; and a second conductive layer and a metal silicide layer sequentially stacked on the first conductive layer and gate insulating layer.

Abstract: Methods of forming a transistor having integrated metal silicide transistor gate electrode on a semiconductor assembly are described. The transistor gate is partially fabricated by reacting the metal with epitaxial silicon while residing in a trench to form metal silicide. A transistor gate isolation capping layer is formed in the trench and on the metal silicide. Optional trench spacers can be added to reduce the critical dimension restraints of a given fabrication process and thus form a transistor having smaller feature sizes than the critical dimension.

Abstract: Methods are provided for semiconductor devices having low contact resistance. The method in accordance with one embodiment of the invention comprises forming an insulating layer overlying a semiconductor substrate, the semiconductor substrate having a device region therein. An opening is formed through the insulating layer to expose a portion of the device region, and the portion of the device region is then electrically contacted by a metallic liner layer. To reduce the resistance of the liner layer and hence the contact, ions of a conductivity determining impurity are implanted into the metallic liner layer. A metal layer is then deposited overlying the metallic liner layer to fill the opening through the insulating layer and to form a conductive plug.

Abstract: A method of fabricating a semiconductor device, includes (a) forming an oxide film entirely over a silicon substrate on which a MOS transistor is fabricated, (b) carrying out first thermal-annealing to the silicon substrate, (c) removing the oxide film in an area where later mentioned silicide is to be formed, (d) forming a metal film entirely over the silicide substrate, (e) carrying out second thermal-annealing to the silicon substrate to form silicide in the area, and (f) removing the metal film having been not reacted with the silicon substrate.

Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Abstract: A method of forming an abrupt junction device with a semiconductor substrate is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed on the gate dielectric. A sidewall spacer is formed on the semiconductor substrate adjacent the gate and the gate dielectric. A thickening layer is formed by selective epitaxial growth on the semiconductor substrate adjacent the sidewall spacer. Raised source/drain dopant implanted regions are formed in at least a portion of the thickening layer. Silicide layers are formed in at least a portion of the raised source/drain dopant implanted regions to form source/drain regions, beneath the silicide layers, that are enriched with dopant from the silicide layers. A dielectric layer is deposited over the silicide layers, and contacts are then formed in the dielectric layer to the silicide layers.

Abstract: In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon from the plug from diffusing into the capacitor's dielectric. The interface can also include an oxygen barrier to prevent the poly plug from oxidizing during processing. Below the interface is a silicide layer to help enhance electrical contact with the poly plug. In a preferred method, the interface is created by selectively depositing a layer of titanium over a recessed poly plug to the exclusion of the surrounding oxide. The deposition process allows for silicidation of the titanium. The top half of the titanium silicide is then nitridized. A conformal ruthenium or ruthenium oxide layer is subsequently deposited, covering the titanium nitride and lining the sides and bottom of the container cell.

Abstract: A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gate and active regions from the deposited selectivity poly. Accordingly, the present invention employing selectivity poly deposition can reduce or minimize contact surface resistance and improve the electrical characteristics of the semiconductor device by reducing the surface resistance in a miniature semiconductor device. In addition, because the size of the gate electrode is getting small, the present invention can be used as an essential part of the future generations of nano-scale technology. Moreover, mass semiconductor production systems can promptly employ the present invention with existing equipment.

Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of a source and a drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometaric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequity: (X/Y)>(X0/Y0).

Abstract: A field effect transistor having metallic silicide layers is formed in a semiconductor layer on an insulating layer of an SOI substrate. The metallic silicide layers are composed of refractory metal and silicon. The metallic silicide layers extend to bottom surfaces of source and drain regions. A ratio of the metal to the silicon in the metallic silicide layers is X to Y. A ratio of the metal to the silicon of metallic silicide having the lowest resistance among stoichiometric metallic silicides is X0 to Y0. X, Y, X0 and Y0 satisfy the following inequality: (X/Y)>(X0/Y0).

Abstract: A metal salicide layer is formed by sequentially depositing a physical vapor deposition (PVD) metal layer and a chemical vapor deposition (CVD) metal layer on a semiconductor device having an exposed silicon surface so as to form a double metal layer. The semiconductor device is annealed to react the double metal layer with the silicon surface. At least a portion of the double layer that has not reacted with the silicon surface is stripped. The semiconductor device is annealed after stripping at least the portion of the double metal layer.

Abstract: Provided are exemplary methods for forming a semiconductor devices incorporating silicide layers formed at temperatures below about 700° C., such as nickel silicides, that are formed after completion of a silicide blocking layer (SBL). The formation of the SBL tends to deactivate dopant species in the gate, lightly-doped drain and/or source/drain regions. The exemplary methods include a post-SBL activation anneal either in place of or in addition to the traditional post-implant activation anneal. The use of the post-SBL anneal produces CMOS transistors having properties that reflect reactivation of sufficient dopant to overcome the SBL process effects, while allowing the use of lower temperature silicides, including nickel silicides and, in particular, nickel silicides incorporating a minor portion of an alloying metal, such as tantalum, the exhibits reduced agglomeration and improved temperature stability.

Abstract: The invention relates to a method for fabricating a semiconductor device having a semiconductor body that comprises a first semiconductor structure having a dielectric layer and a first conductor, and a second semiconductor structure having a dielectric layer and a second conductor, that part of the first conductor which adjoins the dielectric layer having a work function different from the work function of the corresponding part of the second conductor. In one embodiment of the invention, after the dielectric layer has been applied to the semiconductor body, a metal layer is applied to the said dielectric layer, and then a silicon layer is deposited on the metal layer and is brought into reaction with the metal layer at the location of the first semiconductor structure, forming a metal silicide.

Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Abstract: The present invention provides a method for enhancing uni-directional diffusion of a metal during silicidation by using a metal-containing silicon alloy in conjunction with a first anneal in which two distinct thermal cycles are performed. The first thermal cycle of the first anneal is performed at a temperature that is capable of enhancing the uni-directional diffusion of metal, e.g., Co and/or Ni, into a Si-containing layer. The first thermal cycle causes an amorphous metal-containing silicide to form. The second thermal cycle is performed at a temperature that converts the amorphous metal-containing silicide into a crystallized metal rich silicide that is substantially non-etchable as compared to the metal-containing silicon alloy layer or a pure metal-containing layer. Following the first anneal, a selective etch is performed to remove any unreacted metal-containing alloy layer from the structure.

Abstract: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by physical vapor deposition, halogen atoms (120) and transition metal atoms (130) to form a halogen-containing metal layer (140) on a semiconductor substrate (150). The halogen-containing metal layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (400) comprising the metal silicide electrode.

Abstract: A method of self-aligned silicidation involves interruption of the silicidation process prior to complete reaction of the blanket material (e.g., metal) in regions directly overlying patterned and exposed other material (e.g., silicon). Diffusion of excess blanket material from over other regions (e.g., overlying insulators) is thus prevented. Control and uniformity are insured by use of conductive rapid thermal annealing in hot wall reactors, with massive heated plates closely spaced from the substrate surfaces. Interruption is particularly facilitated by forced cooling, preferably also by conductive thermal exchange with closely spaced, massive plates.

Abstract: There is provided a method of fabricating a MOS transistor having a fully silicided gate, including forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including a lower gate pattern, an insulating layer pattern, and an upper gate pattern, which are sequentially stacked. Source/drain regions are formed by implanting impurity ions into an active region using the gate pattern and the gate spacers as ion implantation masks. Then, a protecting layer is formed on the semiconductor substrate having the gate pattern, and the protecting layer is planarized until the upper gate pattern is exposed. Then, by removing the exposed upper gate pattern and the insulating layer pattern, the lower gate pattern is exposed. Then, the protecting layer is selectively removed, thereby exposing the source/drain regions. The exposed lower gate pattern is fully converted to a gate silicide layer, and a silicide layer is concurrently formed on the surfaces of the source/drain regions.

Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.

Abstract: The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1—C?C—R2), wherein R1 is H or CH3, and R2 is H, t-butyl, methyl or ethyl. The silicon substrate is thermally treated so that silicon is reacted with cobalt to form a cobalt silicide layer. Methods for manufacturing semiconductor devices including the cobalt silicide layers described herein and such devices are also provided.

Abstract: A method inhibits metal silicide encroachment in channel regions in a transistor that uses metal silicide as an electrical contact to its terminals. A metal layer is deposited overlying the transistor. A first anneal that is a low temperature anneal forms metal silicide regions to source, gate and drain terminals of the transistor. The low temperature inhibits lateral encroachment. Unsilicided portions of the metal are removed and followed by an ion implant of an element, such as nitrogen, that diffuses into the metal silicide regions. A second anneal at a higher temperature than the first anneal is completed wherein the implanted nitrogen ions prevent lateral encroachment of metal silicide.