Abstract: A method of manufacturing an L-shaped spacer is described. First, a substrate is provided and a protruding structure is formed thereon. Next, a dielectric material is formed on the substrate and covers the stacked structure. Then, the dielectric material on the top of the protruding structure and on portions of the substrate is removed to form an L-shaped spacer.

Abstract: Provided are a method of fabricating a multilayered thin film transistor using a plastic substrate and an active matrix display device including the thin film transistor fabricated by the method. The method includes: preparing a substrate formed of plastic; forming a buffer insulating layer on the plastic substrate; forming a silicon layer on the buffer insulating layer; patterning the silicon layer to form an active layer; forming a gate insulating layer on the active layer; stacking a plurality of gate metal layers on the gate insulating layer; patterning the plurality of gate metal layers; and etching a corner region of the lowest gate metal layer formed on the gate insulating layer of the patterned gate metal layers. Accordingly, a gate metal is formed which includes a multilayered gate metal layer and has an etched corner region, thereby reducing an electric field of the corner to reduce a leakage current of the TFT.

Abstract: A method for forming a low temperature polysilicon thin film transistor with a low doped drain structure comprises: a) forming a polysilicon island on a substrate; b) forming a dielectric layer, a metal layer and a cap layer in sequence cover to the polysilicon island; c) forming a photo-resist patterened layer on the cap layer; d) removing the portion of the metal layer and the portion of the cap layer which are uncovered by the photo-resist patterned layer, and the remaining metal layer is uncovered by the remaining cap layer with a predetermined distance at the same side; e) performing a high concentration ion-doping using the metal layer as a mask; f) removing the portion of the metal layer uncovered by the remaining cap layer; and g) performing a low concentration ion-doping using the metal layer as a mask.

Abstract: A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

Abstract: In a semiconductor device, a SiN first protective insulating film is formed on a semiconductor layer. A T-shaped gate electrode is formed on the semiconductor layer. A SiN second protective insulating film spreads in an umbrella shape from above the T-shaped gate electrode. A hollow region is formed between the two SiN films. The SiN films are coated with a SiN third protective insulating film with the hollow region remaining.

Abstract: A process for manufacturing a thin-film transistor device includes forming a dielectric insulation layer on a substrate, forming an amorphous silicon layer on the dielectric insulation layer, crystallizing the amorphous silicon layer, so as to obtain polycrystalline silicon, forming gate structures on the polycrystalline silicon, and forming first doped regions within the polycrystalline silicon laterally with respect to the gate structures. The crystallizing step includes forming first capping dielectric regions on the amorphous silicon layer, and then irradiating the amorphous silicon layer using a laser so as to form active areas of polycrystalline silicon separated by separation portions of amorphous silicon underlying the first capping dielectric regions.

Abstract: A semiconductor structure is provided which includes a first semiconductor device in a first active semiconductor region and a second semiconductor device in a second active semiconductor region. A first dielectric liner overlies the first semiconductor device and a second dielectric liner overlies the second semiconductor device, with the second dielectric liner overlapping the first dielectric liner at an overlap region. The second dielectric liner has a first portion having a first thickness contacting an apex of the second gate conductor and a second portion extending from peripheral edges of the second gate conductor which has a second thickness substantially greater than the first thickness. A first conductive via contacts at least one of the first or second gate conductors and the conductive via extends through the first and second dielectric liners at the overlap region. A second conductive via may contact at least one of a source region or a drain region of the second semiconductor device.

Abstract: A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

Abstract: A method for fabricating a tiered structure includes forming a gate on a semiconductor substrate. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped and a passivation layer is formed over the gate foot and the substrate. A gate head mask is formed over the gate foot with the gate head mask exposing a portion of the passivation layer on a top portion of the gate foot. The portion of the passivation layer on the top portion of the gate foot is removed to expose the top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.

Abstract: A method of forming a semiconductor device is provided. An interlayer dielectric is formed on a substrate. A di-block polymer layer that includes a plurality of first polymer blocks and a plurality of second polymer blocks is formed on the interlayer dielectric. The di-block polymer layer is divided into a first phase to which the first polymer blocks are bound and a second phase to which the second polymer blocks are bound. The second phase is removed so that at least part of the first phase remains in place, where the remaining first phase defines at least part of a pore. The interlayer dielectric that is exposed beneath the pore is etched to form an opening. The opening may have a smaller width than the minimum feature size that a photolithography process is capable of resolving. As a result, a linewidth of an electrode that may be formed to fill the opening may be reduced.

Abstract: A method of manufacturing a local recess channel transistor in a semiconductor device. A hard mask layer is formed on a semiconductor substrate that exposes a portion of the substrate. The exposed portion of the substrate is etched using the hard mask layer as an etch mask to form a recess trench. A trench spacer is formed on the substrate along a portion of sidewalls of the recess trench. The substrate along a lower portion of the recess trench is exposed after the trench spacer is formed. The exposed portion of the substrate along the lower portion of the recess trench is doped with a channel impurity to form a local channel impurity doped region surrounding the lower portion of the recess trench. A portion of the local channel impurity doped region surrounding the lower portion of the recess trench is doped with a Vth adjusting impurity to form a Vth adjusting impurity doped region inside the local channel impurity doped region. The width of the lower portion of the recess trench is expanded.

Abstract: In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).

Abstract: A method of manufacturing a transistor in which gate resistance is lowered and short channel effects are controlled by forming a trench-type gate. The threshold voltage can also be more tightly controlled.

Abstract: A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate, removing a portion of the first gate insulation layer to selectively expose a first region of the substrate using a first mask and performing an ion implantation on the selectively exposed first region of the substrate using the first mask, and forming a second gate insulation layer on the first gate insulation layer and the exposed first region of the substrate to form a resultant gate insulation layer having a first thickness over the first region of the substrate and a second thickness over a remaining region of the substrate, the first thickness and the second thickness being different.

Abstract: A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

Abstract: A method of fabricating a T-gate is provided. The method includes the steps of: forming a photoresist layer on a substrate; patterning the photoresist layer formed on the substrate and forming a first opening; forming a first insulating layer on the photoresist layer and the substrate; removing the first insulating layer and forming a second opening to expose the substrate; forming a second insulating layer on the first insulating layer; removing the second insulating layer and forming a third opening to expose the substrate; forming a metal layer on the second insulating layer on which the photoresist layer and the third opening are formed; and removing the metal layer formed on the photoresist layer. Accordingly, a uniform and elaborate opening defining the length of a gate may be formed by deposition of the insulating layer and a blanket dry etching process, and thus a more elaborate micro T-gate electrode may be fabricated.

Abstract: A method of fabricating a semiconductor device structure, includes: providing a substrate, providing an electrode on the substrate, forming a recess in the electrode, the recess having an opening, disposing a small grain semiconductor material within the recess, covering the opening to contain the small grain semiconductor material, within the recess, and then annealing the resultant structure.

Abstract: A semiconductor component, particularly a pHEMT, having a T-shaped gate electrode deposited in a double-recess structure, is produced with a method with self-adjusting alignment of the recesses and of the T-shaped gate electrode.

Abstract: In one implementation, a method for fabricating a tiered structure is provided, which includes forming a source and a drain on a substrate with a gate formed therebetween. Formation of the gate includes depositing a gate foot using a gate foot mask having an opening through it to define the gate foot over the substrate. After forming the gate foot, the gate foot mask is stripped. A gate head mask is formed over the gate foot with the gate head mask exposing a top portion of the gate foot. A gate head is formed on the top portion of the gate foot using the gate head mask. A lift-off process is performed, removing the gate head mask.

Abstract: A method for fabricating a pixel structure is provided. First, a gate, a scan line, and a first terminal are formed on a substrate. A gate insulating layer is formed over the substrate to cover the gate, the scan line, and the first terminal. After defining the semiconductor layer, the gate insulating layer is patterned to exposure the first terminal. A transparent conductive layer is formed over the substrate and a patterned photoresist layer is formed on the transparent conductive layer. The transparent conductive layer is patterned using the patterned photoresist layer as a mask, so as to define a source, a drain, a data line, a pixel electrode, a second terminal, and a contact pad. Because only four photomasks are used to implement the above method for fabricating the pixel structure, the cost of manufacturing can be reduced.

Abstract: Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the block-seed a first layer, of predetermined thickness of a second material, and subsequently selectively and anisotropically etching it to form a spacer-seed adjacent to the side wall. The cycle of deposition and selective etching steps of a predetermined material are repeated n times (n?2), with at least one spacer formed in each cycle. This predetermined material is different for each pair of consecutive depositions. The above n steps provides at least one multilayer body. Further selective etching removes every other spacers to provide a plurality of nanometric hosting seats, which forms contact terminals for a plurality of molecular transistors hosted in said hosting seats.

Abstract: A field effect transistor having a T- or ?-shaped fine gate electrode of which a head portion is wider than a foot portion, and a method for manufacturing the field effect transistor, are provided. A void is formed between the head portion of the gate electrode and a semiconductor substrate using an insulating layer having a multi-layer structure with different etch rates. Since parasitic capacitance between the gate electrode and the semiconductor substrate is reduced by the void, the head portion of the gate electrode can be made large so that gate resistance can be reduced. In addition, since the height of the gate electrode can be adjusted by adjusting the thickness of the insulating layer, device performance as well as process uniformity and repeatability can be improved.

Abstract: A semiconductor structure including at least one transistor located on a surface of a semiconductor substrate, wherein the at least one transistor has a sub-lithographic channel length, is provided. Also provided is a method to form such a semiconductor structure using self-assembling block copolymer that can be placed at a specific location using a pre-fabricated hard mask pattern.

Abstract: Flash memory and methods of fabricating the same are disclosed. An illustrated example flash memory includes a first source formed within a semiconductor substrate; an epitaxial layer formed on an upper surface of the semiconductor substrate; an opening formed within the epitaxial layer to expose the first source; a floating gate device formed inside the opening; and a select gate device formed on the epitaxial layer at a distance from the floating gate device.

Abstract: Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench.

Abstract: Disclosed are embodiments of a method of fabricating a bipolar transistor with a self-aligned raised extrinsic base. In the method a dielectric pad is formed on a substrate with a minimum dimension capable of being produced using current state-of-the-art lithographic patterning. An opening is aligned above the dielectric pad and etched through an isolation oxide layer to an extrinsic base layer. The opening is equal to or greater in size than the dielectric pad. Another smaller opening is etched through the extrinsic base layer to the dielectric pad. A multi-step etching process is used to selectively remove the extrinsic base layer from the surfaces of the dielectric pad and then to selectively remove the dielectric pad. An emitter is then formed in the resulting trench. The resulting transistor structure has a distance between the edge of the lower section of the emitter and the edge of the extrinsic base that is minimized, thereby, reducing resistance.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A method of fabricating a recess channel array transistor. Using a mask layer pattern having a high etch selectivity with respect to a silicon substrate, the silicon substrate and an isolation insulating layer are etched to form a recess channel trench. After forming a gate insulating layer and a recess gate stack on the recess channel trench, a source and a drain are formed in the silicon substrate adjacent to both sidewalls of the recess gate stack, thereby completing the recess channel array transistor. Because the mask layer pattern having the high etch selectivity with respect to the silicon substrate is used, a depth of the recess channel trench is easily controlled while good etching uniformity of the silicon substrate is obtained.

Abstract: An FET has a T-shaped gate. The FET has a halo diffusion self-aligned to the bottom portion of the T and an extension diffusion self aligned to the top portion. The halo is thereby separated from the extension implant, and this provides significant advantages. The top and bottom portions of the T-shaped gate can be formed of layers of two different materials, such as germanium and silicon. The two layers are patterned together. Then exposed edges of the bottom layer are selectively chemically reacted and the reaction products are etched away to provide the notch. In another embodiment, the gate is formed of a single gate conductor. A metal is conformally deposited along sidewalls, recess etched to expose a top portion of the sidewalls, and heated to form silicide along bottom portions. The silicide is etched to provide the notch.

Abstract: A semiconductor device and a fabricating method thereof are disclosed. The semiconductor device includes polysilicon gate electrodes, a gate oxide layer, sidewall floating gates, a block oxide layer, source/drain areas, and sidewall spacers. In addition, the method includes the steps of: forming a block dielectric layer and a sacrificial layer on a semiconductor substrate; forming trenches by etching the sacrificial layer; forming sidewall floating gates on lateral faces of the trenches; forming a block oxide layer on the sidewall floating gates; forming polysilicon gate electrodes by a patterning process; removing the sacrificial layer; forming source/drain areas by implanting impurity ions into the resulting structure; injecting carriers or electric charges into the sidewall floating gates; and forming spacers on lateral faces of the polysilicon gate electrodes and the sidewall floating gates.

Abstract: A semiconductor device has: a semiconductor substrate having a pair of current input/output regions via which current flows; an insulating film formed on the semiconductor substrate and having a gate electrode opening; and a mushroom gate electrode structure formed on the semiconductor substrate via the gate electrode opening, the mushroom gate electrode structure having a stem and a head formed on the stem, the stem having a limited size on the semiconductor substrate along a current direction and having a forward taper shape upwardly and monotonically increasing the size along the current direction, the head having a size expanded stepwise along the current direction, and the stem contacting the semiconductor substrate in the gate electrode opening and riding the insulating film near at a position of at least one of opposite ends of the stem along the current direction.

Abstract: A method for creating an inverse T field effect transistor is provided. The method includes creating a horizontal active region and a vertical active region on a substrate. The method further comprises forming a sidewall spacer on a first side of the vertical active region and a second side of the vertical active region. The method further includes removing a portion of the horizontal active region, which is not covered by the sidewall spacer. The method further includes removing the sidewall spacer. The method further includes forming a gate dielectric over at least a first part of the horizontal active region and at least a first part of the vertical active region. The method further includes forming a gate electrode over the gate dielectric. The method further includes forming a source region and a drain region over at least a second part of the horizontal active region and at least a second part of the vertical active region.

Abstract: A component built-in module including a core layer formed of an electric insulating material, and an electric insulating layer and a plurality of wiring patterns, which are formed on at least one surface of the core layer. The electric insulating material of the core layer is formed of a mixture including at least an inorganic filler and a thermosetting resin. At least one or more of active components and/or passive components are contained in an internal portion of the core layer. The core layer has a plurality of wiring patterns and a plurality of inner vias formed of a conductive resin. The electric insulating material formed of the mixture including at least an inorganic filler and a thermosetting resin of the core layer has a modulus of elasticity at room temperature in the range from 0.6 GPa to 10 GPa. Thus, it is possible to provide a thermal conductive component built-in module capable of filling the inorganic filler with high density; burying the active component such as a semiconductor etc.

Abstract: A thin SiGe layer is provided as an additional lower gate electrode layer and is arranged between a thin gate oxide and a gate electrode layer, preferably of polysilicon. The SiGe layer can be etched selectively to the gate electrode and the gate oxide and is laterally removed adjacent the source/drain regions in order to form recesses, which are subsequently filled with a material that is appropriate for charge-trapping. The device structure and production method are appropriate for an integration scheme comprising local interconnects of memory cells, a CMOS logic periphery and means to compensate differences of the layer levels in the array and the periphery.

Abstract: The present invention provides a method for fabricating low-resistance, sub-0.1 ?m channel T-gate MOSFETs that do not exhibit any poly depletion problems. The inventive method employs a damascene-gate processing step and a chemical oxide removal etch to fabricate such MOSFETs. The chemical oxide removal may be performed in a vapor containing HF and NH3 or a plasma containing HF and NH3.

Abstract: The structure and method of forming a notched gate MOSFET disclosed herein addresses such problems as device reliability. A gate dielectric (e.g. gate oxide) is formed on the surface of an active area on the semiconductor substrate, preferably defined by an isolation trench region. A layer of polysilicon is then deposited on the gate dielectric. This step is followed by depositing a layer of silicon germanium) (SiGe). The sidewalls of the polysilicon layer are then laterally etched, selective to the SiGe layer to create a notched gate conductor structure, with the SiGe layer being broader than the underlying polysilicon layer. Sidewall spacers are preferably formed on sidewalls of the SiGe layer and the polysilicon layer. A silicide layer is preferably formed as a self-aligned silicide from a polysilicon layer deposited over the SiGe layer, to reduce resistance of the gate conductor. One or more other processing steps (e.g.

Abstract: There are provided methods of fabricating a semiconductor device having a T-shaped gate and an L-shaped spacer. In the method, an insulating layer and a sacrificial layer are formed in sequence on a semiconductor substrate having a vertical gate pattern. By etching the sacrificial layer, a sacrificial spacer is formed. By etching the insulating layer until an upper surface of at least the vertical gate pattern is exposed, there is formed an L-shaped spacer, which includes a vertical portion located between sidewalls of the vertical gate pattern and the sacrificial spacer, and a horizontal portion extended from the vertical portion and located between the semiconductor substrate and the sacrificial spacer. By selectively etching a part of the vertical portion of the L-shaped spacer, an empty space is formed between upper sidewalls of the vertical gate pattern and the sacrificial spacer.

Abstract: A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111–114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t–114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer.

Abstract: A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring. Further, air-gap spacers are formed over a stacked gate structure. The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers. The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.