Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

Abstract: Provided is a transistor with stable electrical characteristics. Provided is a semiconductor device including an oxide semiconductor over a substrate, a first conductor in contact with a top surface of the oxide semiconductor, a second conductor in contact with the top surface of the oxide semiconductor, a first insulator over the first and second conductors and in contact with the top surface of the oxide semiconductor, a second insulator over the first insulator, a third conductor over the second insulator, and a third insulator over the third conductor. The third conductor overlaps with the first conductor with the first and second insulators positioned therebetween, and overlaps with the second conductor with the first and second insulators positioned therebetween. The first insulator contains oxygen. The second insulator transmits less oxygen than the first insulator. The third insulator transmits less oxygen than the first insulator.

Abstract: A semiconductor device with multi-level work function and multi-valued channel doping is provided. The semiconductor device comprises a nanowire structure and a gate region. The nanowire structure is formed as a channel between a source region and a drain region. The nanowire structure has a first doped channel section joined with a second doped channel section. The first doped channel section is coupled to the source region and has a doping concentration greater than the doping concentration of the second doped channel section. The second doped channel section is coupled to the drain region. The gate region is formed around the junction at which the first doped section and the second doped section are joined. The gate region has a first work function gate section joined with a second work function gate section. The first work function gate section is located adjacent to the source region and has a work function greater than the work function of the second work function gate section.

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

Abstract: A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

Abstract: A semiconductor memory cell, a semiconductor memory device, and a method for manufacturing the same are disclosed. The semiconductor memory cell may comprise: a substrate; a channel region on the substrate; a gate region above the channel region; a source region and a drain region on the substrate and at opposite sides of the channel region; and a buried layer, which is disposed between the substrate and the channel region and comprises a material having a forbidden band narrower than that of a material for the channel region material. The buried layer material has a forbidden band narrower than that of the channel region material, so that a hole barrier is formed in the buried layer. Due to the barrier, it is difficult for holes stored in the buried layer to leak out, resulting in an improved information holding duration of the memory cell utilizing the floating-body effect.

Abstract: A semiconductor device includes: a first semiconductor layer formed over a substrate; a second semiconductor layer formed over the first semiconductor layer; an insulating film including a first insulating film formed over the second semiconductor layer, a second insulating film, and a third insulating film stacked sequentially over the first insulating film, and an electrode formed over the insulating film, wherein, in the first insulating film, a region containing halogen ions is formed under a region provided with the electrode, and the third insulating film contains a halogen.

Abstract: A semiconductor device according to an embodiment includes: a substrate; a first semiconductor layer formed on the substrate and having a strain; a second and a third semiconductor layers formed at a distance from each other on the first semiconductor layer, and having a different lattice constant from a lattice constant of the first semiconductor layer; a gate insulating film formed on a first portion of the first semiconductor layer, the first portion being located between the second semiconductor layer and the third semiconductor layer; and a gate electrode formed on the gate insulating film.

Abstract: Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the channel region whereby the carbon doped SiGe region retains stress/strain on the channel region after subsequent heat processing.

Abstract: A method for depositing a silicon oxide layer on a substrate including a silicon region and a silicon-germanium region, including the steps of: forming a very thin silicon layer having a thickness ranging from 0.1 to 1 nm above silicon-germanium; and depositing a silicon oxide layer on the substrate.

Abstract: A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.

Abstract: A semiconductor structure is provided. The semiconductor structure may include a substrate (100); a buffer layer or an insulation layer (200) formed on the substrate; a first strained wide bandgap semiconductor material layer (400) formed on the buffer layer or the insulation layer; a strained narrow bandgap semiconductor material layer (500) formed on the first strained wide bandgap semiconductor material layer; a second strained wide bandgap semiconductor material layer (700) formed on the strained narrow bandgap semiconductor material layer; a gate stack (300) formed on the second strained wide bandgap semiconductor material layer; and a source and a drain (600) formed in the first strained wide bandgap semiconductor material layer, the strained narrow bandgap semiconductor material layer and the second strained wide bandgap semiconductor material layer respectively.

Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein a bulk semiconductor material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and an insulation material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages of body-tied structures.

Abstract: There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer.

Abstract: Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.

Abstract: Disclosed is a memory device and method of operation thereof. The memory device may include a source region and a drain region of a first dopant type, the source and drain regions contain a first semiconductor material; a body region of a second dopant type, the body region being sandwiched between the source and drain regions, the body comprising a second semiconductor material; a gate dielectric layer over at least the body region; and a gate comprising a conductive material over the gate dielectric layer. Specifically, one of the first semiconductor material and the second semiconductor material is lattice matched with the other of the first semiconductor material and the second semiconductor material and has an energy gap smaller than the energy gap of the other of the first semiconductor material and the second semiconductor material.

Abstract: Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

Abstract: A gate electrode includes a polysilicon film in contact with a gate insulating film, a barrier film provided on the polysilicon film, a metal film provided on the barrier film and made of refractory metal. An interlayer insulating film is arranged so as to cover the gate insulating film and the gate electrode provided on the gate insulating film. The interlayer insulating film has a substrate contact hole partially exposing a silicon carbide substrate in a region in contact with the gate insulating film. A interconnection is electrically connected to the silicon carbide substrate through the substrate contact hole and is electrically insulated from the gate electrode by the interlayer insulating film.

Abstract: It is disclosed a semiconductor device and a method for manufacturing the same. One method comprises providing a semiconductor layer that is formed on an insulating layer; forming a mask pattern on the semiconductor layer, which exposes a portion of the semiconductor layer; removing the exposed portion of the semiconductor layer of a predetermined thickness, thereby forming a groove; forming a gate stack in the mask pattern and the groove; removing the mask pattern to expose a portion of sidewalls of the gate stack. The method not only meets the requirement for a precise thickness of the SOI, but also increases the thickness of the source/drain regions as compared to a device having a uniform SOI thickness at the gate stack, thereby facilitating a reduction of the parasitic resistance of the source/drain regions.

Abstract: Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si1-XGeX) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm. The method also includes forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation and forming a gate opposing the body region and separated therefrom by a gate dielectric.

Abstract: Disclosed are embodiments of field effect transistors (FETs) having suppressed sub-threshold corner leakage, as a function of channel material band-edge modulation. Specifically, the FET channel region is formed with different materials at the edges as compared to the center. Different materials with different band structures and specific locations of those materials are selected in order to effectively raise the threshold voltage (Vt) at the edges of the channel region relative to the Vt at the center of the channel region and, thereby to suppress of sub-threshold corner leakage. Also disclosed are design structures for such FETs and method embodiments for forming such FETs.

Abstract: Methods are provided for fabricating a transistor. An exemplary method involves depositing an oxide layer overlying a layer of semiconductor material, forming an oxygen-diffusion barrier layer overlying the oxide layer, forming a layer of high-k dielectric material overlying the oxygen-diffusion barrier layer, forming a layer of conductive material overlying the layer of high-k dielectric material, selectively removing portions of the layer of conductive material, the layer of high-k dielectric material, the oxygen-diffusion barrier layer, and the oxide layer to form a gate stack, and forming source and drain regions about the gate stack. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.

Abstract: A method for producing stacked and self-aligned components on a substrate, including: providing a substrate made of monocrystalline silicon having one face enabling production of components, forming a stack of layers on the face of the substrate, selective etching by a gaseous mixture comprising gaseous HCl conveyed by a carrier gas and at a temperature between 450° C. and 900° C., depositing resin, implementing lithography of the resin, replacing resin eliminated during the lithography with a material for confining remaining resin, and forming elements of the components.

Abstract: Processes are provided for selectively depositing thin films comprising one or more noble metals on a substrate by vapor deposition processes. In some embodiments, atomic layer deposition (ALD) processes are used to deposit a noble metal containing thin film on a high-k material, metal, metal nitride or other conductive metal compound while avoiding deposition on a lower k insulator such as silicon oxide. The ability to deposit on a first surface, such as a high-k material, while avoiding deposition on a second surface, such as a silicon oxide or silicon nitride surface, may be utilized, for example, in the formation of a gate electrode.

Abstract: A method for producing a wafer with a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method using steps in the following order: simultaneously polishing the front and the back side of the silicon single crystal substrate; depositing a stress compensating layer on the back side of the silicon single crystal substrate; polishing the front side of the silicon single crystal substrate; cleaning the silicon single crystal substrate having the stress compensating layer deposited on the back side; and depositing a fully or partially relaxed layer of SiGe on the front side of the silicon single crystal substrate.

Abstract: Methods of fabricating compound semiconductor devices are described.

Abstract: In a manufacturing flow for adapting the band gap of the semiconductor material with respect to the work function of a metal-containing gate electrode material, a strain-inducing material may be deposited to provide an additional strain component in the channel region. For instance, a layer stack with silicon/carbon, silicon and silicon/germanium may be used for providing the desired threshold voltage for a metal gate while also providing compressive strain in the channel region.

Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a substrate that includes a semiconductor region including Ge as a primary component; a compound layer that is formed above the semiconductor region, that includes Ge and that has a non-metallic characteristic; an insulator film that is formed above the compound layer; an electrode that is formed above the insulator film; and source/drain regions that is formed in the substrate so as to sandwich the electrode therebetween.

Abstract: A metal-insulator-semiconductor field-effect transistor (MISFET) includes a semiconductor layer with source and drain regions of a first conductivity type spaced apart therein. A channel region of a first conductivity type extends between the source and drain regions. A gate contact is on the channel region. A dielectric channel depletion layer is between the gate contact and the channel region. The dielectric channel depletion layer provides a net charge having the same polarity as the first conductivity type charge carriers, and which may deplete the first conductivity type charge carriers from an adjacent portion of the channel region when no voltage is applied to the gate contact.

Abstract: A semiconductor structure includes a silicon substrate layer, a relaxed silicon-germanium layer on the silicon substrate layer and a strained single crystal silicon layer on the silicon-germanium layer. The silicon-germanium layer may include a thickness of 500 angstroms or less. The method for forming the semiconductor structure includes epitaxially forming the silicon-germanium layer and the single crystal silicon layer. The silicon-germanium layer is stressed upon formation. After the single crystal silicon layer is formed over the silicon-germanium layer, an RTA or laser heat treatment process selectively melts the silicon-germanium layer but not the single crystal silicon layer. The substantially molten silicon-germanium relaxes the compressive stresses in the silicon-germanium layer and yields a relaxed silicon-germanium layer and a strained single crystal silicon layer upon cooling.

Abstract: A method for fabricating a stressed MOS device in and on a semiconductor substrate is provided. The method comprises the steps of forming a gate electrode overlying the semiconductor substrate and etching a first trench and a second trench in the semiconductor substrate, the first trench and the second trench formed in alignment with the gate electrode. A stress inducing material is selectively grown in the first trench and in the second trench and conductivity determining impurity ions are implanted into the stress inducing material to form a source region in the first trench and a drain region in the second trench. To preserve the stress induced in the substrate, a layer of mechanically hard material is deposited on the stress inducing material after the step of ion implanting.

Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.

Abstract: A method for inspecting a semiconductor device includes carrying out a first test for inspecting characteristics of semiconductor devices under a shielded (dark) condition to discriminate non-defective devices; and carrying out a second test on the semiconductor devices which have passed the first test as non-defective devices, for inspecting characteristics of the semiconductor devices. The second test is carried out while a predetermined color of light is applied to the semiconductor devices.

Abstract: A semiconductor component is disclosed herein comprising a drift zone and a drift control zone. The drift control zone is arranged adjacent to the drift zone and is dielectrically insulated from the drift zone by a dielectric layer. The drift control zone includes at least one first semiconductor layer and one second semiconductor layer. The first semiconductor layer has a higher charge carrier mobility than the second semiconductor layer.

Abstract: Methods are provided for treating germanium surfaces in preparation for subsequent deposition, particularly gate dielectric deposition by atomic layer deposition (ALD). Prior to depositing, the germanium surface is treated with plasma products or thermally reacted with vapor reactants. Examples of surface treatments leave oxygen bridges, nitrogen bridges, —OH, —NH and/or —NH2 terminations that more readily adsorb ALD reactants. The surface treatments avoid deep penetration of the reactants into the germanium bulk but improve nucleation.

Abstract: Embodiments of the invention provide a method of forming embedded silicon germanium (eSiGe) in source and drain regions of a p-type field-effect-transistor (pFET) through a disposable spacer process; depositing a gap-filling layer directly on the eSiGe in the source and drain regions in a first process; depositing a layer of offset spacer material on top of the gap-filling layer in a second process different from the first process; etching the offset spacer material and the gap-filling layer, thus forming a set of offset spacers and exposing the eSiGe in the source and drain regions of the pFET; and finishing formation of the pFET.

Abstract: A method for forming gate spacers for semiconductor devices includes forming a patterned gate structure on substrate, where the patterned gate structure contains an interface layer on the substrate, a high-k film on the interface layer, and a gate electrode on the high-k film. The method further includes depositing a nitride barrier layer on the patterned gate structure using processing conditions that minimize or prevent oxidation of the substrate and the gate electrode, depositing a spacer material on the nitride barrier layer, and anisotropically etching the spacer material to form a gate spacer on the patterned gate structure.

Abstract: Methods, devices and systems for a FinFET are provided. One method embodiment includes forming a FinFET by forming a relaxed silicon germanium (Si1-XGeX) body region for a fully depleted Fin field effect transistor (FinFET) having a body thickness of at least 10 nanometers (nm) for a process design rule of less than 25 nm. The method also includes forming a source and a drain on opposing ends of the body region, wherein the source and the drain are formed with halo ion implantation and forming a gate opposing the body region and separated therefrom by a gate dielectric.

Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

Abstract: A semiconductor workpiece including a substrate, a relaxed buffer layer including a graded portion formed on the substrate, and at least one strained transitional layer within the graded portion of the relaxed buffer layer and method of manufacturing the same.

Abstract: Chemical vapor deposition processes utilize chemical precursors that allow for the deposition of thin films to be conducted at or near the mass transport limited regime. The processes have high deposition rates yet produce more uniform films, both compositionally and in thickness, than films prepared using conventional chemical precursors. In preferred embodiments, a higher order silane is employed to deposit thin films containing silicon that are useful in the semiconductor industry in various applications such as transistor gate electrodes.

Abstract: A semiconductor structure and method of manufacturing a semiconductor device, and more particularly, an NFET device. The devices includes a stress receiving layer provided over a stress inducing layer with a material at an interface there between which reduces the occurrence and propagation of misfit dislocations in the structure. The stress receiving layer is silicon (Si), the stress inducing layer is silicon-germanium (SiGe) and the material is carbon which is provided by doping the layers during formation of the device. The carbon can be doped throughout the whole of the SiGe layer also.

Abstract: The invention concerns a method for oxidizing a surface region of a SiGe layer that includes an oxidizing thermal treatment of the SiGe layer for oxidizing the surface region. The method includes two phases—a first phase of oxidizing thermal treatment, carried out directly on the SiGe layer, so as to obtain an oxidized region which is thick enough for forming a capping oxide which can protect the underlying SiGe from pitting during the subsequent second phase, but thin enough for keeping the thickness of the oxidized surface region under a threshold thickness range, corresponding to the generation of dislocations within the SiGe layer; and—a second phase of high temperature annealing in an inert atmosphere which is carried out on the SiGe layer after the first phase. The SiGe layer is capped with the oxidized region created during the first phase, and the high temperature annealing allows the diffusion of Ge from a Ge-enriched region into the underlying part of the SiGe layer.

Abstract: A semiconductor device having a field effect transistor and a method of forming the same are provided. The semiconductor device preferably includes a device active pattern disposed on a predetermined region of the substrate. The gate electrode preferably crosses over the device active pattern, interposed by a gate insulation layer. A support pattern is preferably interposed between the device active pattern and the substrate. The support pattern can be disposed under the gate electrode. A filling insulation pattern is preferably disposed between the device active pattern and the filling insulation pattern. The filling insulation pattern may be disposed under the source/drain region. A device active pattern under the gate electrode is preferably formed of a strained silicon having a lattice width wider than a silicon lattice.

Abstract: The present invention provides for a low-temperature method to crystallize a silicon-germanium film. Metal-induced crystallization of a deposited silicon film can serve to reduce the temperature required to crystallize the film. Increasing germanium content in a silicon-germanium alloy further decreases crystallization temperature. By using metal-induced crystallization to crystallize a deposited silicon-germanium film, temperature can be reduced substantially. In preferred embodiments, for example in a monolithic three dimensional array of stacked memory levels, reduced temperature allows the use of aluminum metallization. In some embodiments, use of metal-induced crystallization in a vertically oriented silicon-germanium diode having conductive contacts at the top and bottom end is be particularly advantageous, as increased solubility of the metal catalyst in the contact material will reduce the risk of metal contamination of the diode.

Abstract: Briefly, the present invention provides an electronic device, typically a transistor or a capacitor, comprising at least one electrically conductive electrode and, adjacent to the electrode, a dielectric layer; wherein the dielectric layer comprises a polymeric matrix and, dispersed in the polymeric matrix, metal oxide particles; wherein the metal oxide particles have organic functional groups covalently bound to their surface, and wherein the organic functional groups are not covalently bound to the polymeric matrix. In another aspect, the present invention provides a printable dispersion, typically a jet-printable dispersion, comprising: a) a curable composition and b) metal oxide particles; wherein the metal oxide particles have organic functional groups covalently bound to their surface, and wherein the organic functional groups are not covalently bound to any part of the curable composition.

Abstract: There are provided an analog capacitor having at least three high-k dielectric layers, and a method of fabricating the same. The analog capacitor includes a lower electrode, an upper electrode, and at least three high-k dielectric layers interposed between the lower electrode and the upper electrode. The at least three high-k dielectric layers include a bottom dielectric layer contacting the lower electrode, a top dielectric layer contacting the upper electrode, and a middle dielectric layer interposed between the bottom dielectric layer and the top dielectric layer. Further, each of the bottom dielectric layer and the top dielectric layer is a high-k dielectric layer, the absolute value of the quadratic coefficient of VCC thereof being relatively low compared to that of the middle dielectric layer, and the middle dielectric layer is a high-k dielectric layer having a low leakage current compared to those of the bottom dielectric layer and the top dielectric layer.

Abstract: A semiconductor device comprising a semiconductor substrate and a MOSFET provided on the semiconductor substrate, the MOSFET including a gate insulating film and a gate electrode provided on the gate insulating film, wherein the gate insulating film has a higher dielectric constant in a side contacting the semiconductor substrate than in a side contacting the gate electrode.

Abstract: The invention includes non-volatile memory and logic devices associated with crystalline Si/Ge. The devices can include TFT constructions. The non-volatile devices include a floating gate or floating plate over the Si/Ge, and a pair of source/drain regions. The source/drain regions can extend into the Si/Ge. The memory or logic devices further include an insulative material over the floating gate or plate, and a control gate separated from the floating gate or plate by the insulative material. The crystalline Si/Ge can have a relaxed crystalline lattice, and a crystalline layer having a strained crystalline lattice can be formed between the relaxed crystalline lattice and the floating gate or plate. The devices can be fabricated over any of a variety of substrates. The floating plate option can provide lower programming voltage and orders of magnitude superior endurance compared to other options.

Abstract: A field effect transistor (FET) and method of forming the FET comprises a substrate; a silicon germanium (SiGe) layer over the substrate; a semiconductor layer over and adjacent to the SiGe layer; an insulating layer adjacent to the substrate, the SiGe layer, and the semiconductor layer; a pair of first gate structures adjacent to the insulating layer; and a second gate structure over the insulating layer. Preferably, the insulating layer is adjacent to a side surface of the SiGe layer and an upper surface of the semiconductor layer, a lower surface of the semiconductor layer, and a side surface of the semiconductor layer. Preferably, the SiGe layer comprises carbon. Preferably, the pair of first gate structures are substantially transverse to the second gate structure. Additionally, the pair of first gate structures are preferably encapsulated by the insulating layer.