Abstract: A plasma etching method capable of forming a tapering etching structure having a smooth surface is provided. A fluorine-containing gas and a nitrogen gas are used and plasma is generated from these gases simultaneously, and a silicon substrate K is etched by the plasma while an etch-resistant layer is formed on the silicon substrate K by the plasma and then a fluorine-containing gas and an oxygen-containing gas are used and plasma is generated from these gases simultaneously, and the silicon substrate K is etched by the plasma while an etch-resistant layer is formed on the silicon substrate K by the plasma generated from the oxygen-containing gas, thereby forming a tapering etching structure H having a wide top opening width and a narrow bottom width.

Abstract: A chuck, a system including a chuck and a method for making a semiconductor device are disclosed. In one embodiment the chuck includes a first conductive region configured to be capacitively coupled to a first RF power generator, a second conductive region configured to be capacitively coupled to a second RF power generator and an insulation region that electrically insulates the first conductive region from the second conductive region.

Abstract: A plasma etching method is provided to perform a plasma etching on a silicon oxide film or a silicon nitride film formed below an amorphous carbon film by using a pattern of the amorphous carbon film as a final mask in a multilayer mask including a photoresist layer having a predetermined pattern, an organic bottom anti-reflection coating (BARC) film formed below the photoresist layer, an SiON film formed below the BARC film, and the amorphous carbon film formed below the SiON film. An initial mask used at the time when the plasma etching of the silicon oxide film or the silicon nitride film is started is under a state in which the SiON film remains on the amorphous carbon film and a ratio of a film thickness of the amorphous carbon film to a film thickness of the residual SiON film is smaller than or equal to about 14.

Abstract: A method of etching a silicon layer through a patterned mask is provided. The method uses an etch chamber in which the silicon layer is placed. The method includes (a) providing the silicon layer having the patterned mask formed thereon, (b) providing an etch gas comprising a fluorine containing gas and an oxygen and hydrogen containing gas into the etch chamber in which the silicon layer has been placed, (c) generating a plasma from the etch gas, (d) etching features into the silicon layer through the patterned mask using the plasma, and (e) stopping the etch gas. The oxygen and hydrogen containing gas contains water vapor.

Abstract: A method for etching features in a plurality of silicon based bilayers forming a stack on a wafer in a plasma processing chamber is provided. A main etch gas is flowed into the plasma processing chamber. The main etch gas is formed into a plasma, while providing a first pressure. A wafer temperature of less than 20° C. is maintained. The pressure is ramped to a second pressure less than the first pressure as the plasma etches through a plurality of the plurality of silicon based bilayers. The flow of the main etch gas is stopped after a first plurality of the plurality of bilayers is etched.

Abstract: A thinning method of a wafer is provided. The method includes the following steps. First, a wafer having a first surface, a second surface, and a side surface is provided, and the side surface is connected between the first surface and the second surface. At least one semiconductor device is formed on the first surface. Then, an anisotropy etching process is performed to the second surface with a mask to remove portions of the wafer while remaining the side surface thereby forming a number of grooves in the second surface and at least one reinforcing wall between the grooves. As a result, a thinned wafer is obtained.

Abstract: According to one embodiment, there is disclosed a magnetic random access memory comprising: a semiconductor substrate; a selective transistor formed at the surface region of the semiconductor substrate and having a gate electrode, a gate insulating film, a source and a drain; and a magnetoresistive element formed on the drain including a magnetic storage layer in which a magnetization direction is variable, a magnetic reference layer in which a magnetization direction is fixed, and a nonmagnetic layer sandwiched between the magnetic storage layer and the magnetic reference layer.

Abstract: According to one embodiment, a silicon film, in which an impurity density of a center portion is higher than that of an upper portion and a lower portion, is formed above a base layer, a mask pattern is formed above the silicon film, a recess is formed in the silicon film by selectively etching the silicon film through the mask pattern, a silicon oxide film is formed on a surface of the recess by an oxidation process of the silicon film, and the silicon film under the recess is etched through the mask pattern after the oxidation process.

Abstract: A compression member for use in a showerhead electrode assembly of a capacitively coupled plasma chamber. The member applies a compression force to a portion of a film heater adjacent a power supply boot on an upper surface of a thermal control plate and is located between the thermal control plate and a temperature-controlled top plate. The member is composed of an electrically insulating elastomeric material which can work over a large range of compressions and temperatures.

Abstract: Methods and systems for temperature enhanced chucking and dechucking of resistive substrates in a plasma processing apparatus are described herein. In certain embodiments, methods and systems incorporate modulating a glass carrier substrate temperature during a plasma etch process to chuck and dechuck the carrier at first temperatures elevated relative to second temperatures utilized during plasma etching. In embodiments, one or more of plasma heat, lamp heat, resistive heat, and fluid heat transfer are controlled to modulate the carrier substrate temperature between chucking temperatures and process temperatures with each run of the plasma etch process.

Abstract: When forming sophisticated transistors on the basis of a highly stressed dielectric material formed above a transistor, the stress transfer efficiency may be increased by reducing the size of the spacer structure of the gate electrode structure prior to depositing the highly stressed material. Prior to the deposition of the highly stressed material, an additional cleaning process may be implemented in order to reduce the presence of any metal contaminants, in particular in the vicinity of the gate electrode structure, which would otherwise result in an increased fringing capacitance.

Abstract: According to one embodiment, a manufacturing method of a magnetic memory includes forming a magnetoresistive element in a cell array section on a semiconductor substrate, forming a dummy element in a peripheral circuit section on the semiconductor substrate, the dummy element having the same stacked structure as the magnetoresistive element and being arranged at the same level as the magnetoresistive element, collectively flattening the magnetoresistive element and the dummy element, applying a laser beam to the dummy element to form the dummy element into a non-magnetic body, and forming an upper electrode on the flattened magnetoresistive element.

Abstract: A plasma processing apparatus is provided which includes an inert gas supply route connected to a process gas supply piping which supplies a process gas into a processing chamber in a vacuum vessel, a valve which opens or closes the inert gas supply route, and an adjuster which adjusts a flow rate of the inert gas. When processing of a sample is complete, an inert gas is supplied into the process gas supply piping so that a pressure in the process gas supply piping is maintained at a pressure higher than a pressure at which a compound of the process gas and a material of an inner wall of the process gas supply piping vaporizes.

Abstract: Embodiments of a strained semiconductor device are provided, as are embodiments of a method for fabricating such a strained semiconductor device. In one embodiment, the method includes providing a partially-fabricated semiconductor device including a semiconductor substrate having a source side and a drain side, a gate stack formed on the semiconductor substrate, and a channel region formed within the semiconductor substrate beneath the gate stack and extending from the source side to the drain side of the semiconductor substrate. A cavity is produced in only one of the source side and the drain side of the semiconductor substrate, and a strain-inducing material is formed within the cavity to create an asymmetric heterojunction structure within the semiconductor substrate.

Abstract: According to one embodiment, a second conductive layer is provided on a second insulating film and connected to a first conductive layer via an opening portion in the second insulating film. A first contact is connected to the second conductive layer. A third conductive layer is provided on the second insulating film and connected to the first conductive layer via an opening portion in the second insulating film. A second contact is connected to the third conductive layer. A fourth conductive layer is provided on the second insulating film and connected to the first conductive layer via an opening portion in the second insulating film. A third contact is connected to the fourth conductive layer. The floating gate layer and the first conductive layer are made of the same material, and the control gate layer, the second, third and fourth conductive layers are made of the same material.

Abstract: The present invention introduces a new technique allowing the fabrication of high-aspect ratio nanoscale semiconductor structures and local device modifications using FIB technology. The unwanted semiconductor sputtering in the beam tail region prevented by a thin slow-sputter-rate layer which responds much slower and mostly to the high-intensity ion beam center, thus acting as a saturated absorber funnel-like mask for the semiconductor. The protective layer can be deposited locally using FIB, thus enabling this technique for local device modifications, which is impossible using existing technology. Furthermore, such protective layers allow much higher resolution and nanoscale milling can be achieved with very high aspect ratios, e.g. Ti layer results in aspect ratio higher than 10 versus bare semiconductor milling ratio of about 3.

Abstract: A method to determine minimum etch mask dosage or thickness as a function of etch depth or maximum etch depth as a function of etch mask implantation dosage or thickness, for fabricating structures in or on a substrate through etch masking via addition or removal of a masking material and subsequent etching.

Abstract: A method for designing, fabricating, and predicting a desired structure in and/or on a host material through defining etch masks and etching the host material is provided. The desired structure can be micro- or nanoscale structures, such as suspended nanowires and corresponding supporting pillars, and can be defined one layer at a time. Arbitrary desired structures can also be defined and obtained through etching. Further, given the desired structure, a starting structure can be predicted where etching of the starting structure yields the desired structure.

Abstract: Systems for and methods of laser-enhanced plasma processing of semiconductor materials are disclosed. The method includes supporting a semiconductor material in a processing chamber interior and subjecting the semiconductor material to a plasma process. The method also includes simultaneously heating the wafer surface with a laser beam through a window in the processing chamber to increase the reaction rate of the plasma process. Other methods include performing laser heating of the semiconductor material before or after the plasma process but while the semiconductor material resides in the same chamber interior.

Abstract: A method for forming features through a photoresist mask into an underlying layer is provided. The photoresist mask has patterned mask features. The photoresist mask has patterned mask features. A treatment gas containing H2 and N2 is provided. A plasma is generated from the treatment gas, and the photoresist mask is exposed to the plasma. The treatment gas is stopped, and then the features are etched into the underlying layer through the plasma-treated photoresist mask.

Abstract: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.

Abstract: Circuits, methods, chambers, systems, and computer programs are presented for processing wafers. A wafer processing apparatus includes top and bottom electrodes inside a processing chamber; a first, second, third, and fourth radio frequency (RF) power sources; and one or more resonant circuits. The first, second, and third RF power sources are coupled to the bottom electrode. The top electrode may be coupled to the fourth RF power source, to electrical ground, or to the one or more resonant circuits. Each of the one or more resonant circuits, which are coupled between the top electrode and electrical ground, include a tune-in element operable to vary a frequency-dependent impedance presented by the resonant circuit. The wafer processing apparatus is configurable to select the RF power sources for wafer processing operations, as well as the connections to the top electrode in order to provide plasma and etching uniformity for the wafer.

Abstract: A method for manufacturing a silicon structure according to the present invention includes, in a so-called dry-etching process wherein gas-switching is employed, the steps of: etching a portion in the silicon region at a highest etching rate under a high-rate etching condition such that the portion does not reach the etch stop layer; subsequently etching under a transition etching condition in which an etching rate is decreased with time from the highest etching rate in the high-rate etching condition; and thereafter, etching the silicon region under a low-rate etching condition of a lowest etching rate in the transition etching condition.

Abstract: A method includes the steps of: (a) fixing a front surface of a wafer (semiconductor wafer) having the front surface, a plurality of chip regions formed on the front surface, a dicing region formed between the chip regions, and a rear surface opposite to the front surface to the supporting member; (b) in a state of having the wafer fixed to the supporting member, grinding the rear surface of the wafer to expose the rear surface; (c) in a state of having the wafer fixed to the supporting member, dividing the wafer into the chip regions; (d) etching side surfaces of the chip regions to remove crushed layers formed in the step (c) on the side surfaces and obtain a plurality of semiconductor chips. After the steps (e) and (d), the plurality of divided chip regions are peeled off from the supporting member to obtain a plurality of semiconductor chips.

Abstract: A chamber filler kit for an inductively coupled plasma processing chamber in which semiconductor substrates are processed by inductively coupling RF energy through a window facing a substrate supported on a cantilever chuck. The kit includes at least one chamber filler which reduces the lower chamber volume in the chamber below the chuck. The fillers of the kit can be mounted in a standard chamber having a chamber volume of over 60 liters and by using different sized chamber fillers it is possible to reduce the chamber volume to provide desired gas flow conductance and accommodate changes in vacuum pressure during processing of the substrate. The chamber filler kit can be used to modify a standard chamber to accommodate different processing regimes such as rapid alternating processes wherein wide pressure changes are needed without varying a gap between the substrate and the window.

Abstract: A method for fabricating a dual damascene structure includes providing a first photoresist layer coated on an underlying dielectric stack, exposing said first photoresist layer to a first predetermined pattern of light, coating a second photoresist layer onto the pre-exposed first photoresist layer, exposing said second photoresist layer to a second predetermined pattern of light, optionally post-exposure baking the multi-tiered photoresist layers and developing said photoresist layers to form a multi-tiered dual damascene structure in the photoresist layers.

Abstract: A semiconductor device manufacture method includes: forming a first film above a semiconductor substrate; forming a first mask film above the first film; patterning the first mask film; executing a plasma process for a side wall of the patterned first mask film to transform the side wall into a transformed layer; after the plasma process, forming a second mask film covering the first mask film; etching the second mask film to remove the second mask film above the first mask film and leave the second mask film formed on the side wall; after the etching the second mask film, removing the transformed layer; and after the removing the transformed layer, etching the first film by using the first mask film and the second mask film as mask.

Abstract: A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.

Abstract: An insulating layer containing a silicon peroxide radical is used as an insulating layer in contact with an oxide semiconductor layer for forming a channel. Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.

Abstract: A wafer is provided into an entrance load lock chamber. A vacuum is created in the entrance load lock chamber. The wafer is transported to a processing tool. The wafer is processed in a process chamber to provide a processed wafer, wherein the processing forms halogen residue. A degas step is provided in the process chamber after processing the wafer. The processed wafer is transferred into a degas chamber. The processed wafer is treated in the degas chamber with UV light and a flow of gas comprising at least one of ozone, oxygen, or H2O. The flow of gas is stopped. The UV light is stopped. The processed wafer is removed from the degas chamber.

Abstract: The present invention provides a method for fabricating a patterned structure in a semiconductor device, which includes the following processes. First, a target layer, a first mask and a first patterned mask are sequentially formed on a substrate. Then, a first etching process is performed to form a plurality of characteristic structures on the substrate, wherein each of the characteristic structures comprises a patterned first mask and a patterned target layer. A second patterned mask is formed on the substrate, wherein the second patterned mask covers a portion of the characteristic structures and exposes a predetermined region. A second etching process is performed to fully eliminate the characteristic structures within the predetermined region. Finally, a third etching process is performed to fully eliminate the target layer not covered by the patterned first mask.

Abstract: Disclosed is a plasma etching method capable of carrying out an etching process while preventing an etching shape defect such as a bowing from occurring. The plasma etching method includes etching an organic film formed on the substrate to a middle depth using an inorganic film as a mask by generating plasma between an upper electrode a surface of which is formed with a silicon containing material and a lower electrode where a substrate to be processed is placed thereon in a processing chamber; forming a protective film including the silicon containing material of the upper electrode on a side wall of an etching region formed from the etching process by applying a negative DC voltage on the upper electrode while generating the plasma; and continuing the etching process using the plasma thereby etching the organic film to a predetermined depth.

Abstract: A method for processing a silicon substrate includes providing a combination of a first silicon substrate, a second silicon substrate, and an intermediate layer including a plurality of recessed portions, which is provided between the first silicon substrate and the second silicon substrate, forming a first through hole that goes through the first silicon substrate by executing etching of the first silicon substrate on a surface of the first silicon substrate opposite to a bonding surface with the intermediate layer by using a first mask, and exposing a portion of the intermediate layer corresponding to the plurality of recessed portions of the intermediate layer, forming a plurality of openings on the intermediate layer by removing a portion constituting a bottom of the plurality of recessed portions, and forming a second through hole that goes through the second silicon substrate by executing second etching of the second silicon substrate by using the intermediate layer on which the plurality of openings ar

Abstract: In a semiconductor device producing method according to one embodiment, an insulating film containing silicon is formed on a semiconductor substrate, a resist is deposited on the insulating film, the resist is patterned into a predetermined pattern, and the insulating film is processed by a dry etching treatment in which gas containing C, F, Br, H, and O is used with the resist having the predetermined pattern as a mask. A deposited film in which C and Br are coupled is produced on the resist.

Abstract: Examples of the present disclosure provide devices and methods for processing a memory cell. A method embodiment includes removing a key-hole shaped column from a material, to define a profile for the memory cell. The method also includes partially filling the key-hole shaped column with a first number of materials. The method further includes filling the remaining portion of the key-hole shaped column with a second number of materials.

Abstract: A replaceable chamber element for use in a plasma processing system, such as a plasma etching system, is described. The replaceable chamber element includes a chamber component configured to be exposed to plasma in a plasma processing system, wherein the chamber component is fabricated of a ferroelectric material.

Abstract: A pressure control valve assembly of a plasma processing chamber in which semiconductor substrates are processed includes a housing having an inlet, an outlet and a conduit extending between the inlet and the outlet, the inlet adapted to be connected to an interior of the plasma processing chamber and the outlet adapted to be connected to a vacuum pump which maintains the plasma processing chamber at desired pressure set points during rapid alternating phases of processing a semiconductor substrate in the chamber. A drive mechanism attached to first and second valve plates effects rotation of the first and second valve plates to switch the valve plates between first and second angular orientations to change the degree of alignment of first and second open areas of the valve plates and thereby increase or decrease conductance to achieve desired pressure settings in the chamber.

Abstract: A method for selectively etching a substrate is described. The method includes preparing a substrate comprising a silicon nitride layer overlying a silicon-containing contact region, and patterning the silicon nitride layer to expose the silicon-containing contact region using a plasma etching process in a plasma etching system. The plasma etching process uses a process composition having as incipient ingredients a process gas containing C, H and F, and a non-oxygen-containing additive gas, wherein the non-oxygen-containing additive gas includes H, or C, or both H and C, and excludes a halogen atom.

Abstract: A method for controlling a plasma processing system using wafer bias information derived from RF voltage information is proposed. The RF voltage is processed via an analog or digital methodology to obtain peak voltage information at least for each of the fundamental frequencies and the broadband frequency. The peak voltage information is then employed to derive the wafer bias information to serve as a feedback or control signal to hardware/software of the plasma processing system.

Abstract: The invention provides a method of processing a wafer using Ion Energy (IE)-related multilayer process sequences and Ion Energy Controlled Multi-Input/Multi-Output (IEC-MIMO) models and libraries that can include one or more measurement procedures, one or more IEC-etch sequences, and one or more Ion Energy Optimized (IEO) etch procedures. The IEC-MIMO process control uses dynamically interacting behavioral modeling between multiple layers and/or multiple IEC etch sequences. The multiple layers and/or the multiple IEC etch sequence can be associated with the creation of lines, trenches, vias, spacers, contacts, and gate structures that can be created using IEO etch procedures.

Abstract: A semiconductor device manufacturing method, the method including: forming a semiconductor element on a semiconductor substrate; and by using microwaves as a plasma source, forming an insulation film on the semiconductor element by performing a CVD process using microwave plasma having an electron temperature of plasma lower than 1.5 eV and an electron density of plasma higher than 1×1011 cm?3 near a surface of the semiconductor substrate.

Abstract: A dry etching method for texturing a surface of a substrate is disclosed. The method includes performing a first dry etching onto the surface of the substrate thereby forming a surface texture with spikes and valleys, the first dry etching comprising etching the surface of the substrate in a plasma comprising fluorine (F) radicals and oxygen (O) radicals, wherein the plasma comprises an excess of oxygen (O) radicals. The method may further include performing a second dry etching onto the surface texture thereby smoothening the surface texture, the second dry etching comprising chemical isotropic etching the surface texture, obtained after the first dry etching, in a plasma comprising fluorine (F) radicals, wherein the spikes are etched substantially faster than the valleys.

Abstract: The described process allows trenches to be etched in a structure comprising a support substrate and a multilayer, formed on the substrate, for the definition of wave guides of an integrated optical device and comprises a selective plasma attack in the multilayer through a masking structure that leaves uncovered areas of the multilayer corresponding to the trenches to be etched. Such a masking structure is obtained by forming a mask of metallic material on the multilayer that leaves uncovered the areas corresponding to the trenches to be etched and forming a mask of non-metallic material, for example photoresist, on it that leaves uncovered regions comprising at least part of the areas and an edge portion of the mask of metallic material.

Abstract: When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.

Abstract: A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved.

Abstract: A chemical solution that removes undesired metal hard mask yet remains selective to the device wiring metallurgy and dielectric materials. The present invention decreases aspect ratio by selective removal of the metal hard mask before the metallization of the receiving structures without adverse damage to any existing metal or dielectric materials required to define the semiconductor device, e.g. copper metallurgy or device dielectric. Thus, an improved aspect ratio for metal fill without introducing any excessive trapezoidal cross-sectional character to the defined metal receiving structures of the device will result.

Abstract: Oxygen is released from the insulating layer, whereby oxygen deficiency in the oxide semiconductor layer and an interface state between the insulating layer and the oxide semiconductor layer can be reduced. Accordingly, a semiconductor device where reliability is high and variation in electric characteristics is small can be manufactured.

Abstract: An apparatus for etching high aspect ratio features is provided. A plasma processing chamber is provided, comprising a chamber wall forming a plasma processing chamber enclosure, a lower electrode, an upper electrode, a gas inlet, and a gas outlet. A high frequency radio frequency (RF) power source is electrically connected to at least one of the upper electrode or lower electrode. A bias power system is electrically connected to both the upper electrode and the lower electrode, wherein the bias power system is able to provide a bias to the upper and lower electrodes with a magnitude of at least 500 volts, and wherein the bias to the lower electrode is pulsed to intermittently. A gas source is in fluid connection with the gas inlet. A controller is controllably connected to the gas source, the high frequency RF power source, and the bias power system.

Abstract: A top plate assembly is positioned above and spaced apart from the substrate support, such that a processing region exists between the top plate assembly and the substrate support. The top plate assembly includes a central plasma generation microchamber and a plurality of annular-shaped plasma generation microchambers positioned in a concentric manner about the central plasma generation microchamber. Adjacently positioned ones of the central and annular-shaped plasma generation microchambers are spaced apart from each other so as to form a number of axial exhaust vents therebetween. Each of the central and annular-shaped plasma generation microchambers is defined to generate a corresponding plasma therein and supply reactive constituents of its plasma to the processing region between the top plate assembly and the substrate support.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can form a plurality of grooves extending in a first direction on a semiconductor substrate. The method can form an insulating layer on the inner face of the groove and on the top face of the semiconductor substrate. The method can deposit a first conductive layer on the insulating layer so as to fill in the groove. The method can deposit a second conductive layer on the first conductive layer. The method can form a hard mask in a region including part of a region immediately above the groove on the second conductive layer. The method can form a columnar body including the hard mask and the second conductive layer by etching the second conductive layer using the hard mask as a mask.