Abstract: A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.

Abstract: A method of forming a semiconductor device includes depositing a first layer over a substrate and patterning the first layer using an extreme ultraviolet (EUV) lithography process to form a patterned layer and expose portions of the substrate. The method includes, in a plasma processing chamber, generating a first plasma from a gas mixture including SiCl4 and one or more of argon, helium, nitrogen, and hydrogen. The method includes exposing the substrate to the first plasma to deposit a second layer including silicon over the patterned layer.

Abstract: An electronic device is provided, the electronic device having a keyboard including a biometric input device. The biometric input device may be a biometric key or button. A cap of a biometric key or button may include a textured ceramic cover, such as a textured sapphire cover. The cap may further include a rear decorative coating and a front antireflective coating disposed on or over the textured ceramic cover. The cap may have one or more visual and or tactile properties which resemble those of an adjacent key of the keyboard.

Abstract: FET IC structures that enable formation of integrated capacitors in a “flipped” SOI IC structure made using a back-side access process, such as a “single layer transfer” (SLT) process, and which eliminate or mitigate unwanted parasitic couplings to a handle wafer. In some embodiments, a conductive interconnect layer may be patterned, pre-SLT, to form an isolated first capacitor plate. In other embodiments, pre-SLT, a conductive region of the active layer of an IC may be patterned to form an isolated first capacitor plate, with one or more interconnect layers being fabricated in position to form an electrical contact to the first capacitor plate. In either case, a post-SLT top-side layer of conductive material may be patterned to form a second capacitor plate. Couplings to the resulting capacitor structures include only external connections, only internal connections, or both internal and external connections.

Abstract: Processing forms an integrated circuit structure having first and second layers on opposite sides of an insulator, and an interconnect structure extending through the insulator between the first layer and the second layer. The interconnect structure is formed in an opening extending through the insulator between the first layer and the second layer and has an electrical conductor in the opening extending between the first layer and the second layer and a thermally conductive electrical insulator liner along sidewalls of the opening extending between the first layer and the second layer. The electrical conductor is positioned to conduct electrical signals between the first layer and the second layer, and the thermally conductive electrical insulator liner is positioned to transfer heat between the first layer and the second layer.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed at the first surface of the substrate, where the stress-sensitive sensor is sensitive to mechanical stress; a stress-decoupling trench that has a vertical extension that extends from the first surface into the substrate, where the stress-decoupling trench vertically extends partially into the substrate towards the second surface although not completely to the second surface; and a plurality of particle filter trenches that vertically extend from the second surface into the substrate, wherein each of the plurality of particle filter trenches have a longitudinal extension that extends orthogonal to the vertical extension of the stress-decoupling trench.

Abstract: Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a seed layer on a second side of a substrate opposite the first side of the substrate, using a shadow mask, applying a mask layer over the seed layer, forming a backside metal layer over the seed layer, removing the mask layer, and singulating the plurality of die included in the substrate through removing substrate material in the die street and through removing seed layer material in the die street.

Abstract: A method for treating a substrate having millimeter and/or micrometer and/or nanometer structures. The method includes applying at least one protective material to the structures, wherein the at least one protective material can be dissolved in a solvent, and the structures are produced by an imprinting process.

Abstract: Methods, systems, computer-readable media, and apparatuses for high density Micro-Electro-Mechanical Systems (MEMS) are presented. In some embodiments, a method for manufacturing a micro-electro-mechanical device on a substrate can comprise etching a release via through a layer of the device. The method can further comprise creating a cavity in the layer of the device using the release via as a conduit to access the desired location of the cavity, the cavity enabling movement of a transducer of the device. The method can then comprise depositing low impedance, electrically conductive material into the release via to form an electrically conductive path through the layer. Finally, the method can comprise electrically coupling the electrically conductive material to an electrode of the transducer.

Abstract: An interconnect structure and a method of forming are provided. The method includes forming an opening in a dielectric layer and an etch stop layer, wherein the opening extends only partially through the etch stop layer. The method also includes creating a vacuum environment around the device. After creating the vacuum environment around the device, the method includes etching through the etch stop layer to extend the opening and expose a first conductive feature. The method also includes forming a second conductive feature in the opening.

Abstract: A wafer thinning apparatus includes a first metrology tool configured to measure an initial thickness of the wafer. The wafer thinning apparatus further includes a controller connected to the first metrology tool, and configured to determine a polishing time based on the initial thickness, a predetermined thickness and a material removal rate. The wafer thinning apparatus further includes a polishing tool connected to the controller configured to polish the wafer for a period of time equal to the polishing time. The wafer thinning apparatus includes a second metrology tool connected to the controller and the polishing tool, and configured to measure a polished thickness. The controller is configured to update the material removal rate based on the polished thickness, the predetermined thickness and the polishing time.

Abstract: A wafer holder is provided for use in a polishing machine. The wafer holder has a frame composed of a thermoset material and/or a thermoplastic material. The frame has at least one cavity for receiving and supporting a wafer to be polished in the polishing machine. A polymer film pad is permanently affixed in the at least one cavity.

Abstract: The wafer chuck apparatus has a chuck body that includes an interior and a top surface. A plurality of micro-channel regions is formed in the top surface. Each micro-channel region is defined by an array of micro-channel sections that are in pneumatic communication with each other. The micro-channel regions are pneumatically isolated from each other. One or more vacuum manifold regions are defined in the interior of the chuck body and are in pneumatic communication with corresponding micro-channel regions through respective vacuum holes. The configuration of the micro-channel regions makes the wafer chuck apparatus particularly useful in chucking wafers that have a substantial amount of warp.

Abstract: Method for manufacturing a bonded SOI wafer by bonding a bond wafer and base wafer, each composed of a silicon single crystal, via an insulator film, including the steps: depositing a polycrystalline silicon layer on the base wafer bonding surface side, polishing the polycrystalline silicon layer surface, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the base wafer polycrystalline silicon layer and bond wafer via the insulator film; thinning the bonded bond wafer to form an SOI layer; wherein, in the step of depositing the polycrystalline silicon layer, a wafer having a chemically etched surface as base wafer; chemically etched surface is subjected to primary polishing followed by depositing the polycrystalline silicon layer on surface subjected to the primary polishing, and in the step polishing the polycrystalline silicon layer surface, which is subjected to secondary polishing or secondary and finish polishing.

Abstract: A display apparatus includes a substrate and a plurality of pixels disposed on the substrate. Each pixel includes a gate electrode on the substrate, a common electrode insulated from the gate electrode on the substrate, a first insulating layer covering the gate electrode and the common electrode, a semiconductor pattern disposed on the first insulating layer to overlap with the gate electrode, source and drain electrodes disposed on the semiconductor pattern and spaced apart from each other, and a pixel electrode disposed on the first insulating layer to cover the drain electrode and form an electric field with the common electrode. The display apparatus may be manufactured by first to fourth photolithography processes using first to fourth masks, and the first mask may be a slit mask or a diffraction mask.

Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion.

Abstract: Disclosed herein is a decompression processing apparatus for processing a wafer in a decompressed state including a chamber having a decompressing unit configured to decompress the inside of the chamber, an opening and closing door configured to open and close a carrying-in-and-out opening for carrying the wafer into and out of the chamber, and an inert gas supply source configured to supply an inert gas to the inside of the chamber. The inside of the chamber is maintained in a dry state by continuing to supply the inert gas in a state in which the opening and closing door is opened.

Abstract: A polishing unit of a polishing apparatus according to an embodiment includes: a polishing head having a pressing member configured to hold a polishing tape and press the polishing tape against a peripheral portion of a substrate from above; a tape supply and recovery mechanism configured to supply the polishing tape to the polishing head and recover the polishing tape from the polishing head; a first moving mechanism configured to move the polishing head in a radial direction of the substrate; and a second moving mechanism configured to move the tape supply and recovery mechanism in the radial direction of the substrate. The positioning unit includes a positioning block having a contacting surface, and alignment of the polishing tape is conducted by the second moving mechanism moving the tape supply and recovery mechanism so that a substrate-side edge of the polishing tape makes contact with the contacting surface.

Abstract: A semiconductor structure and a method of fabricating thereof are provided. The method includes the following steps. A substrate with an upper surface and a lower surface is received. A first recess extending from the upper surface to the lower surface is formed and the first recess has a first depth. A second recess extending from the upper surface to the lower surface is formed and the second recess has a second depth less than the first depth. A first conducting layer is formed in the first recess and the second recess. A first insulating layer is formed over the first conducting layer. A second conducting layer is formed over the first insulating layer and isolated from the first conducting layer with the first insulating layer. The substrate is thinned from the lower surface to expose the second conducting layer in the first recess.

Abstract: An optical device wafer processing method includes a shield tunnel forming step of applying a pulsed laser beam having a transmission wavelength to a sapphire substrate along an area corresponding to each division line from the back side of the sapphire substrate in the condition where the focal point of the pulsed laser beam is set inside the sapphire substrate, thereby forming a plurality of shield tunnels arranged along the area corresponding to each division line, each shield tunnel being composed of a fine hole and an amorphous region formed around the fine hole for shielding the fine hole. The optical device wafer processing method further includes a dividing step of applying an external force to the optical device wafer after performing a light emitting layer forming step, thereby dividing the optical device wafer along the division lines to obtain the individual optical device chips.

Abstract: A method for removing material from a substrate includes providing the substrate with first and second opposing major surfaces. A masking layer is disposed along one of the first major surface and the second major surface, and is provided with a plurality of openings. The substrate is placed within an etching apparatus and material is removed from the substrate through openings using the etching apparatus. The thickness of the substrate is measured within the etching apparatus using a thickness transducer. The measured thickness is compared to a predetermined thickness and the material removal step is terminated responsive to the measured thickness corresponding to the predetermined thickness. In one embodiment, the method is used to more accurately form recessed regions in semiconductor die, which can be used in, for example, stacked device configurations.

Abstract: A flexible display device includes a display module and a window member disposed on the display module. The window member includes a base film, elastomer patterns disposed on one surface of the base film, and a hard coating layer disposed on the one surface of the base film to cover the elastomer patterns.

Abstract: A method for manufacturing a capacitive transducer is provided having a structure in which a vibrating film is supported to be able to vibrate. The method includes forming a sacrificial layer on a first electrode; forming a layer on the sacrificial layer, the layer forming at least part of the vibrating film; removing the sacrificial layer, including forming etching holes to communicate with the sacrificial layer; forming a sealing layer for sealing the etching holes; and etching at least part of the sealing layer. Before forming the sealing layer, an etching stop layer is formed on the layer forming at least part of the vibrating film. In the step of etching at least part of the sealing layer, the sealing layer is removed until the etching stop layer is reached.

Abstract: According to some embodiments of the invention, a light-emitting device package includes a body including top and bottom surfaces and a cavity in the body, the cavity extending from the top surface towards the bottom surface and having a floor. The light-emitting device package also includes a plurality of LED (light-emitting-diode) dies disposed on the floor of the cavity. A socket is formed over the plurality of LED dies. The socket includes a top surface, a socket sidewall, and a bottom surface, the socket sidewall disposed between the top surface and the bottom surface of the socket. A lens is disposed over the over the socket. The lens includes two or more optical materials with different indices of refraction. The lens includes a cap and a plug. The cap has an upper surface and a lower surface, and the plug has a lower surface and a plug sidewall between the lower surface of the plug and the lower surface of the cap.

Abstract: A polishing unit of a polishing apparatus according to an embodiment includes: a polishing head having a pressing member configured to hold a polishing tape and press the polishing tape against a peripheral portion of a substrate from above; a tape supply and recovery mechanism configured to supply the polishing tape to the polishing head and recover the polishing tape from the polishing head; a first moving mechanism configured to move the polishing head in a radial direction of the substrate; and a second moving mechanism configured to move the tape supply and recovery mechanism in the radial direction of the substrate. The positioning unit includes a positioning block having a contacting surface, and alignment of the polishing tape is conducted by the second moving mechanism moving the tape supply and recovery mechanism so that a substrate-side edge of the polishing tape makes contact with the contacting surface.

Abstract: A thin metal substrate having high thermal conductivity includes a copper foil layer, an insulating polymer layer and a thermal conductive adhesive layer. The thermal conductive adhesive layer has a resin and a thermal conductive powder dispersed in the resin. The insulating polymer layer is disposed between the copper foil layer and the thermal conductive adhesive layer. Since the thermal conductive adhesive layer has the thermal conductive powder and the insulating polymer layer has insulating and anti-breakdown abilities, the substrate has a reduced thickness, high heat dissipating efficiency and improved insulating performance.

Abstract: A polishing method which can remove foreign matters from an entire back surface of a substrate at a high removal rate is provided. The polishing method includes placing a polishing tool in sliding contact with an outer circumferential region of a back surface of a substrate while holding a center-side region of the back surface of the substrate, and placing a polishing tool in sliding contact with the center-side region of the back surface of the substrate while holding a bevel portion of the substrate to polish the back surface in its entirety.

Abstract: To provide a method of manufacturing an element chip in which creep-up of a conductive material can be suppressed in a mounting step. In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by an insulating film, the substrate is divided into the element chips by exposing the substrate to a first plasma, the element chips having a first surface, a second surface, and a side surface are held spaced from each other on a carrier, and the side surface and the insulating film are in a state of being exposed.

Abstract: A method for producing mirror-polished wafer, the method produces a plurality of mirror-polished wafers by performing, on plurality of silicon wafers obtained by slicing a silicon ingot, slicing strain removing step of removing strain on a surface caused by slicing, etching step of removing strain caused by the slicing strain removing step, and double-side polishing step of performing mirror polishing on both surfaces of the silicon wafers subjected to etching, each step being performed by batch processing, wherein silicon wafers which are processed in double-side polishing step by batch processing are selected from silicon wafers processed in same batch in the slicing strain removing step and the number of silicon wafers to be selected is made to be equal to the number of silicon wafers processed in the slicing strain removing step or submultiple thereof. As a result, a method that can produce mirror-polished wafers having high flatness is provided.

Abstract: A wafer in which a modified layer is internally formed along planned dividing lines is placed on a placement table and a water tank allows the wafer placed on the placement table to be submerged in cleaning water. An ultrasonic supply unit supplies ultrasonic waves to the wafer submerged in the cleaning water. By the ultrasonic waves supplied by the ultrasonic supply unit, the wafer is divided along the planned dividing lines and is turned into small pieces to generate plural chips and the generated chips are cleaned.

Abstract: According to various embodiments, a method for processing a semiconductor substrate may include: covering a plurality of die regions of the semiconductor substrate with a metal; forming a plurality of dies from the semiconductor substrate, wherein each die of the plurality of dies is covered with the metal; and, subsequently, annealing the metal covering at least one die of the plurality of dies.

Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.

Abstract: A method for forming a thin film pattern includes: forming a first resist pattern on a substrate; forming a second resist pattern on the substrate and the first resist pattern, forming a first metal layer overlapping an exposed portion of the substrate and exposed portions of the first and second resist patterns; removing the second resist pattern and a portion of the first metal layer, through a first lift-off process to expose portions of the substrate and the first resist pattern; forming a second metal layer overlapping portions of each of the substrate, the first resist pattern and the first metal layer; and removing the first resist pattern and the first and second metal layers, through a second lift-off process, to form first and second metal patterns from remaining portions of the first and second metal layers. The first and second resist patterns have different dissolution characteristics.

Abstract: Growth of GaP and III-V GaP alloys in the wurtzite crystal structure by vapor phase epitaxy (VPE) is provided. Such material has a direct band gap and is therefore much more useful for optoelectronic devices than conventional GaP and GaP alloys having the zincblende crystal structure and having an indirect band gap.

Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer using a fluid.

Abstract: A semiconductor device includes a first semiconductor chip including a first surface, a second surface and a first terminal arranged on the first surface, a second semiconductor chip including a first surface, a second surface and a second terminal arranged on the first surface of the second semiconductor chip, a support substrate including a first surface bonded to the second surfaces of the first semiconductor chip and the second semiconductor chip, and an isolation groove formed on the first surface of the support substrate. The isolation includes a pair of side surfaces continuously extending from opposing side surfaces of the first semiconductor chip and the second semiconductor chip, respectively, and the isolation groove is formed into the support substrate to extend from the first surface of the support substrate. The isolation groove has a depth less than a thickness of the support substrate.

Abstract: A package includes a molding compound, a through-via penetrating through the molding compound, a device die molded in the molding compound, and a buffer layer on and contacting the molding compound. An opening is through the buffer layer to the through-via. The buffer layer has ripples in a plane parallel to an interface between the molding compound and the buffer layer and around a circumference of the opening. Other embodiments contemplate an additional package bonded to the package, and methods for forming the package.

Abstract: A substrate laminating low film, a substrate laminated structure and a method of manufacturing an organic light emitting display are disclosed. One inventive aspect includes a base member, a first adhesion layer formed on the base member, and a second adhesion layer formed on the first adhesion layer. The second adhesion layer has a second adhesion strength less than the first adhesion strength of the first adhesion layer.

Abstract: An adhesive sheet of the invention includes a substrate and an adhesive composition laminated thereon, the substrate including polyvinyl chloride and a polyester-based plasticizer, wherein the adhesive composition includes two different (meth)acrylate copolymer components (A) and (B) in a mass ratio ranging from 10:90 to 90:10, wherein a content of a cross-linking agent which reacts with functional groups of the component (A) and the component (B) is in a range of 0.5 to 20 mass parts with respect to 100 mass parts of a sum of the component (A) and the component (B), and wherein 10 to 95 mass % of the monomer unit composing the component (A) is 2-ethylhexyl acrylate, and 10 to 95 mass % of the monomer unit composing the component (B) is butyl acrylate.

Abstract: A method for separating a layer for transfer includes forming a crack guiding layer on a substrate and forming a device layer on the crack-guiding layer. The crack guiding layer is weakened by exposing the crack-guiding layer to a gas which reduces adherence at interfaces adjacent to the crack guiding layer. A stress inducing layer is formed on the device layer to assist in initiating a crack through the crack guiding layer and/or the interfaces. The device layer is removed from the substrate by propagating the crack.

Abstract: A method of making a split gate non-volatile memory (NVM) includes forming a charge storage layer on the substrate, depositing a first conductive layer, and depositing a capping layer. These layers are patterned to form a control gate stack. A second conductive layer is deposited over the substrate and is patterned to leave a first portion of the second conductive layer over a portion of the control gate stack and adjacent to a first side of the control gate stack. The first portion of the second conductive layer and the control gate stack are planarized to leave a dummy select gate from the first portion of the second conductive layer, where a top surface of a remaining portion of the first conductive layer is lower relative to a top surface of the dummy select gate. The dummy select gate is replaced with a select gate including metal.

Abstract: A NAND flash memory chip includes narrow word lines that are directly patterned from sidewall spacers and larger structures that are patterned from sidewall spacers with covering material. Sidewall spacers with covering material define wider features than sidewalls alone. Closely spaced sidewalls with covering material define large structures such as contact pads and select lines.

Abstract: Various embodiments of the present invention include a semiconductor device, the semiconductor device including a first semiconductor chip disposed on a substrate, a first sealing resin sealing the first semiconductor chip, a built-in semiconductor device disposed on the first sealing resin, and a second sealing resin sealing the first sealing resin and the built-in semiconductor device and covering a side surface of the substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device, in which downsizing and cost reduction can be realized.

Abstract: Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer.

Abstract: A shallow trench isolation (STI) structure includes a top surface formed completely of silicon nitride. The top surface of the STI structure is coplanar with a top substrate surface or extends above the top substrate surface. The STI structures include further dielectric materials beneath the silicon nitride and an oxide liner and any portions that extend above the substrate surface are formed of silicon nitride.

Abstract: In one embodiment, semiconductor die are singulated from a semiconductor wafer having a backmetal layer by placing the semiconductor wafer onto a carrier tape with the backmetal layer adjacent the carrier tape, forming singulation lines through the semiconductor wafer to expose the backmetal layer within the singulation lines, and separating portions of the backmetal layer within the singulation lines using a pressurized fluid applied to the carrier tape.

Abstract: The present disclosure relates to nitride semiconductor and a fabricating method thereof, and a nitride semiconductor according to an exemplary embodiment of the present disclosure includes a nitride based first and second electrode placed with a distance on a substrate, a nitride based channel layer which connects the first and second electrode, an insulating layer which covers the channel layer, and a third electrode which is formed to cover the insulating layer on the insulating layer.

Abstract: A semiconductor structure has embedded stressor material for enhanced transistor performance. The method of forming the semiconductor structure includes etching an undercut in a substrate material under one or more gate structures while protecting an implant with a liner material. The method further includes removing the liner material on a side of the implant and depositing stressor material in the undercut under the one or more gate structures.

Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.

Abstract: A method and structure for fabricating a monolithic integrated MEMS device. The method includes providing a substrate having a surface region and forming at least one conduction material and at least one insulation material overlying at least one portion of the surface region. At least one support structure can be formed overlying at least one portion of the conduction and insulation surface regions, and at least one MEMS device can be formed overlying the support structure(s) and the conduction and insulation surface regions. In a variety of embodiments, the support structure(s) can include dielectric or oxide materials. The support structure(s) can then be removed and a cover material can be formed overlying the MEMS device(s), the conduction and insulation materials, and the substrate. In various embodiments, the removal of the support structure(s) can be accomplished via a vapor etching process.