Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a semiconductor pillar, and a plurality of memory cells. The stacked body includes a plurality of stacked gate electrodes and inter-electrode insulating layers provided between the gate electrodes. The semiconductor pillar punches through the stacked body. The plurality of memory cells is provided in stacking direction. The memory cell includes a charge trap layer provided between the semiconductor pillar and the gate electrode via an air gap. The block insulating layer is provided between the charge trap layer and the gate electrode. Each of the plurality of memory cells is provided with a support portion configured to keep air gap distance between the charge trap layer and the semiconductor pillar.

Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

Abstract: Modulation-doped multi-gate devices are generally described. In one example, an apparatus includes a semiconductor substrate having a surface, one or more buffer films coupled to the surface of the semiconductor substrate, a first barrier film coupled to the one or more buffer films, a multi-gate fin coupled to the first barrier film, the multi-gate fin comprising a source region, a drain region, and a channel region of a multi-gate device wherein the channel region is disposed between the source region and the drain region, a spacer film coupled to the multi-gate fin, and a doped film coupled to the spacer film.

Abstract: Provided is an excellent nonvolatile storage device having advantageous in miniaturization and less variation in initial threshold value, and exhibiting a high writing efficiency, without an erasing failure and a retention failure. The nonvolatile storage device is characterized by including a film stack extending from between a semiconductor substrate and a gate electrode onto at least a surface of the gate electrode lying on a first impurity diffusion region side, the film stack including a charge accumulating layer and a tunnel insulating film sequentially from a gate electrode side.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.

Abstract: The present invention provides a semiconductor structure and a method for manufacturing the same. The method comprises: providing a substrate, forming sequentially a first high-k dielectric layer, an adjusting layer, a second high-k dielectric layer and a metal gate on the substrate, etching the first high-k dielectric layer, the adjusting layer, the second high-k dielectric layer and the metal gate to form a gate stack. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes to arrange an adjusting layer between two layers of high-k dielectric layer, which effectively avoids reaction of the adjusting layer with the metal gate because of their direct contact, so as to maintain the performance of semiconductor devices.

Abstract: A memory device having at least one multi-level memory cell is disclosed, and each multi-level memory cell configured to store n multiple bits, where n is an integer, wherein the multiple bits are stored in a charge storage layer trapping charge carriers injected by application of a voltage to set or reset a threshold voltage Vt of the memory cell to one of 2n levels. Each memory cell may be programmed to one of 2n multiple levels, wherein each level represents n multiple bits.

Abstract: Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor region, a tunnel insulator provided above the semiconductor region, a charge storage insulator provided above the tunnel insulator, a block insulator provided above the charge storage insulator, a control gate electrode provided above the block insulator, and an interface region including a metal element, the interface region being provided at one interface selected from between the semiconductor region and the tunnel insulator, the tunnel insulator and the charge storage insulator, the charge storage insulator and the block insulator, and the block insulator and the control gate electrode.

Abstract: Devices and methods for isolating adjacent charge accumulation layers in a semiconductor device are disclosed. In one embodiment, a semiconductor device comprises a bit line formed in a semiconductor substrate, a charge accumulation layer formed on the semiconductor substrate, a word line formed on the charge accumulation layer across the bit line, and a channel region formed in the semiconductor substrate below the word line and between the bit line and its adjacent bit line. For the semiconductor device, the charge accumulation layer is formed above the channel region in a widthwise direction of the word line, and a width of the word line is set to be narrower than a distance between an end of the channel region and a central part of the channel region in a lengthwise direction of the word line.

Abstract: Patterns of a nonvolatile memory device include a semiconductor substrate that defines active regions extending in a longitudinal direction, an isolation structure formed between the active regions, a tunnel insulating layer formed on the active regions, a charge trap layer formed on the tunnel insulating layer, a first dielectric layer formed on the charge trap layer and the isolation structure, wherein the first dielectric layers is extended along a lateral direction, a control gate layer formed on the first dielectric layer, wherein the control gate layer is extended along the lateral direction, and a second dielectric layer formed on a sidewall of the control gate layer along the lateral direction and coupled to the first dielectric layer.

Abstract: A nonvolatile memory device includes a first channel comprising a pair of first pillars vertically extending from a substrate and a first coupling portion positioned under the pair of first pillars and coupling the pair of first pillars, a second channel adjacent to the first channel comprising a pair of second pillars vertically extending from the substrate and a second coupling portion positioned under the pair of second pillars and coupling the pair of second pillars, a plurality of gate electrode layers and interlayer dielectric layers alternately stacked along the first and second pillar portions, and first and second trenches isolating the plurality of gate electrode layers between the pair of first pillar portions and between the pair of second pillar portions, respectively.

Abstract: Provided is an information storage medium using nanocrystal particles, a method of manufacturing the information storage medium, and an information storage apparatus including the information storage medium. The information storage medium includes a conductive layer, a first insulating layer formed on the conductive layer, a nanocrystal layer that is formed on the first insulating layer and includes conductive nanocrystal particles that can trap charges, and a second insulating layer formed on the nanocrystal layer.

Abstract: A method of manufacturing a nonvolatile memory device comprises providing a semiconductor substrate defining active regions and isolation regions with a gate insulating layer and a floating gate formed over each active region and isolation layer formed in the respective isolation regions, forming a dielectric layer on a surface of the isolation layers and the floating gates, forming a polysilicon layer over the dielectric layer through a polysilicon deposition process using a nitrogen source gas, a silicon source gas, and an impurity doping gas, and patterning the polysilicon layer to form a control gate.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a silicon oxynitride layer on a semiconductor device for use in a variety of electronic systems. The silicon oxynitride layer may be structured to control strain in a silicon channel of the semiconductor device to modify carrier mobility in the silicon channel, where the silicon channel is configured to conduct current under appropriate operating conditions of the semiconductor device.

Abstract: According to one embodiment, a method for fabricating a semiconductor device including a memory cell portion and a select gate portion, the method includes etching a charge accumulation layer, a tunnel insulating film, and a semiconductor substrate to make a trench, burying a first insulating film in the trench to contact with a side surface of the charge accumulation layer, performing heat processing to compress the first insulating film, forming a second insulating film on the charge accumulation layer and the first insulating film, etching the second insulating film in the select gate portion to expose a surface of the charge accumulation layer, forming a silicon layer to contact with the exposed surface of the charge accumulation layer, forming a metal layer on the silicon layer, and performing heat processing to silicide an entire boundary region between the charge accumulation layer and the tunnel insulating film.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.

Abstract: A non-volatile memory device includes a memory cell region which is formed on a semiconductor substrate to store predetermined information, and a peripheral circuit region which is formed on the semiconductor substrate. The memory cell region includes a gate electrode; and a charge storage layer, the charge storage layer being formed to be a notch or wedge shape having an edge extending into both sides of a bottom end of the gate electrode. The peripheral circuit region includes no charge storage layer therein.

Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.

Abstract: Embodiments of the present technology are directed toward charge trapping region process margin engineering for charge trapping field effect transistor. The techniques include forming a plurality of shallow trench isolation regions on a substrate, wherein the tops of the shallow trench isolation regions extend above the substrate by a given amount. A portion of the substrate is oxidized to form a tunneling dielectric region. A first set of one or more nitride layers are deposited on the tunneling dielectric region and shallow trench isolation regions, wherein a thickness of the first set of nitride layers is approximately half of the given amount that the tops of the shallow trench isolation regions extend above the substrate. A portion of the first set of nitride layers is etched back to the tops of the trench isolation regions. A second set of one or more nitride layers is deposited on the etched back first set of nitride layers.

Abstract: Methods of fabricating 3D charge-trap memory cells are described, along with apparatus and systems that include them. In a planar stack formed by alternate layers of electrically conductive and insulating material, a substantially vertical opening may be formed. Inside the vertical opening a substantially vertical structure may be formed that comprises a first layer, a charge-trap layer, a tunneling oxide layer, and an epitaxial silicon portion. Additional embodiments are also described.

Abstract: A semiconductor device including a plurality of decoupling capacitors formed on a semiconductor substrate, and a plurality of decoupling capacitor contact plugs disposed between the semiconductor substrate and the plurality of decoupling capacitors, the plurality of decoupling capacitor contact plugs being electrically connected to the plurality of decoupling capacitors and including an array of first decoupling capacitor contact plugs and second decoupling capacitor contact plugs.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a first stacked body on a substrate by alternately stacking a first film and a second film, forming a second stacked body on the first stacked body by alternately stacking a third film and a fourth film, making a through-hole to pierce the second stacked body and the first stacked body by performing etching, an etching rate of the third film being lower than an etching rate of the first film in the etching, forming a charge storage film on an inner surface of the through-hole, and forming a semiconductor member in the through-hole. The first film and the second film are formed of mutually different materials. The third film and the fourth film are formed of mutually different materials. And, the first film and the third film are formed of mutually different materials.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of gate electrode films arranged parallel to each other along a direction, a semiconductor member extending in the direction, and passing through the plurality of gate electrode films, and a charge storage film provided between the gate electrode films and the semiconductor member. Protrusions are provided projecting along the direction at the ends of the gate electrode films in opposition to the semiconductor member. A gaseous layer is formed in a part of a gap between the gate electrode films.

Abstract: A nonvolatile semiconductor memory device includes: a semiconductor member; a memory film provided on a surface of the semiconductor member and being capable of storing charge; and a plurality of control gate electrodes provided on the memory film, spaced from each other, and arranged along a direction parallel to the surface. Average dielectric constant of a material interposed between one of the control gate electrodes and a portion of the semiconductor member located immediately below the control gate electrode adjacent to the one control gate electrode is lower than average dielectric constant of a material interposed between the one control gate electrode and a portion of the semiconductor member located immediately below the one control gate electrode.

Abstract: Methods of fabricating a silicon oxide layer using an inorganic silicon precursor and methods of fabricating a semiconductor device using the same are provided. The methods of fabricating a semiconductor device include forming a tunnel insulating layer and a charge storage layer on a substrate; forming a dielectric layer structure on the charge storage layer using an atomic layer deposition (ALD) method, the dielectric layer structure including a first dielectric layer formed of silicon oxide, a second dielectric layer on the first dielectric layer formed of a material different from the material forming the first dielectric layer, and a third dielectric layer formed of the silicon oxide on the second dielectric layer; and forming a control gate on the dielectric layer structure.

Abstract: A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever

Abstract: A semiconductor device includes a region in a semiconductor substrate having a top surface with a first charge storage layer on the top surface. A first conductive line is on the first charge storage layer. A second charge storage layer is on the top surface. A second conductive line is on the second charge storage layer. A third charge storage layer is on the top surface. A third conductive line is on the third charge storage layer. A fourth charge storage layer has a first side adjoining a first sidewall of the first conductive line and a second side adjoining a first sidewall of the second conductive line. A fifth charge storage layer has a first side adjoining a second sidewall of the second conductive line and a second side adjoining a first sidewall of the third conductive line. Source and drain regions are formed in the substrate on either side of the semiconductor device.

Abstract: A method for manufacturing a semiconductor device includes: forming a stacked body of a dielectric layer including a silicon oxide and a conductive layer including silicon above a substrate; and forming a hole penetrating through the dielectric layer and the conductive layer in the stacked body, the forming the hole including: forming a first mask layer including a silicon oxide above the stacked body; etching the conductive layer while using the first mask layer as a mask; and forming a second mask layer having more silicon content than the dielectric layer above the first mask layer to etch the dielectric layer while using the second mask layer as a mask.

Abstract: A blocking dielectric engineered, charge trapping memory cell includes a charge trapping element that is separated from a gate by a blocking dielectric including a buffer layer in contact with the charge trapping element, such as silicon dioxide which can be made with high-quality, and a second capping layer in contact with said one of the gate and the channel. The capping layer has a dielectric constant that is higher than that of the first layer, and preferably includes a high-? material. The second layer also has a conduction band offset that is relatively high. A bandgap engineered tunneling layer between the channel and the charge trapping element is provided which, in combination with the multilayer blocking dielectric described herein, provides for high-speed erase operations by hole tunneling. In an alternative, a single layer tunneling layer is used.

Abstract: A method of manufacturing a semiconductor device according to an embodiment, includes: forming a stack structure by alternately stacking control gate electrodes and interlayer insulating films; forming a through-hole that penetrates through the stack structure in a stacking direction of the control gate electrodes and the interlayer insulating films; forming a first insulating film that covers an inner surface of the through-hole; forming a charge storage layer that covers an inner surface of the first insulating film; forming a second insulating film that covers an inner surface of the charge storage layer; forming a semiconductor layer that covers an inner surface of the second insulating film; and oxidizing an interface between the semiconductor layer and the second insulating film by performing a heat treatment in an atmosphere containing O2 gas at a temperature of 600° C. or lower.

Abstract: Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, metal salt ions are added to a core of a copolymer solution. A metal salt reduction causes the metal atoms to aggregate in the core, forming a metal nanodot. The copolymer solution is applied to a gate oxide on a substrate using spin coating or dip coating. Due to the copolymer configuration, the nanodots are held in a uniform 2D grid on the gate oxide. The polymers are selected to provide a desired nanodot size and spacing between nanodots. A polymer cure and removal process leaves the nanodots on the gate oxide. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.

Abstract: The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeholder structures so as to expose the channel area of the transistor. Thereafter, corresponding fins may be patterned and a gate electrode structure may be formed. Consequently, reduced cycle times may be accomplished due to the avoidance of the epitaxial growth process.

Abstract: A method of fabricating a semiconductor device and a flash memory device are provided. The method of fabricating the semiconductor device includes: forming a nitride film on a semiconductor substrate; forming a sacrificial vertical structure on the nitride film; forming sacrificial spacers on lateral surfaces of the sacrificial vertical structure; performing an initial patterning of the nitride film using the sacrificial vertical structure and the sacrificial spacers as etch masks; removing the sacrificial spacers after the initial patterning of the nitride film and forming gate electrodes on the lateral surfaces of the sacrificial vertical structure; and removing the sacrificial vertical structure from between the gate electrodes and performing a secondary patterning of the nitride film using the gate electrodes as etch masks.

Abstract: Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern.

Abstract: Some embodiments provide microelectronic fabrication methods in which a sacrificial pattern is formed on a substrate. A spacer formation layer is formed on the substrate, the spacer formation layer covering the sacrificial pattern. The spacer formation layer is etched to expose an upper surface of the sacrificial pattern and to leave at least one spacer on at least one sidewall of the sacrificial pattern. A first portion of the sacrificial pattern having a first width is removed while leaving intact a second portion of the sacrificial pattern having a second width greater than the first width to thereby form a composite mask pattern including the at least one spacer and a portion of the sacrificial layer. An underlying portion of the substrate is etched using the composite mask pattern as an etching mask.

Abstract: A method for fabricating a non-volatile memory device includes repeatedly stacking interlayer dielectric layers and gate conductive layers on a substrate; etching the interlayer dielectric layers and the gate conductive layers to form cell channel holes that expose the substrate, forming a protective layer along a resultant structure, forming a capping layer on the protective layer to fill the cell channel holes, planarizing the protective layer and the capping layer until an uppermost one of the interlayer dielectric layers is exposed, forming a gate conductive layer for select transistors and an interlayer dielectric layer for select transistors on a resultant structure, etching the interlayer dielectric layer and the gate conductive layer, to form select transistor channel holes that expose the capping layer while removing the capping layer buried in the cell channel holes, and removing the protective layer.

Abstract: A method of manufacturing a semiconductor device includes forming silicon pillar 11 on substrate 10, forming a protective film which covers an upper end portion and a lower end portion of a side surface of silicon pillar 11, forming a constricted portion by anisotropic etching in a portion of the side surface of silicon pillar 11 which is not covered with the protective film after forming the protective film, removing the protective film after forming the constricted portion, forming gate oxide film 12 which covers the side surface of silicon pillar 11 in which the constricted portion is formed, and forming gate electrode 13 which covers gate oxide film 12.

Abstract: In one embodiment, a nonvolatile semiconductor memory device includes a substrate; a tunnel insulating film on the substrate; a charge storage layer on the tunnel insulating film; a block insulating film on the charge storage layer; a first element isolation insulating film in an element isolation trench in the substrate, having a bottom surface lower than an interface between the substrate and the tunnel insulating film, and having a top surface lower than an interface between the charge storage layer and the block insulating film; a second element isolation insulating film on the first element isolation insulating film, protruding to a top surface of the block insulating film, in contact with a side surface of the block insulating film, and having a higher Si concentration than the block insulating film; and a control gate electrode on the block insulating film and on the second element isolation insulating film.

Abstract: A nonvolatile semiconductor memory apparatus includes: a source and drain regions formed at a distance from each other in a semiconductor layer; a first insulating film formed on the semiconductor layer located between the source region and the drain region, the first insulating film including a first insulating layer and a second insulating layer formed on the first insulating layer and having a higher dielectric constant than the first insulating layer, the second insulating layer having a first site performing hole trapping and releasing, the first site being formed by adding an element different from a base material to the second insulating film, the first site being located at a lower level than a Fermi level of a material forming the semiconductor layer; a charge storage film formed on the first insulating film; a second insulating film formed on the charge storage film; and a control gate electrode formed on the second insulating film.

Abstract: A non-volatile memory (NVM) cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate, a drain region in a portion of the silicon substrate, and a well region disposed in a portion of the silicon substrate between the source and drain regions. The cell includes a bottom oxide layer formed on the main surface of the substrate. The bottom oxide layer is disposed on a portion of the main surface proximate the well region. The cell includes a charge storage layer disposed above the bottom oxide layer, a dielectric tunneling layer disposed above the charge storage layer and a control gate formed above the dielectric tunneling layer. The dielectric tunneling layer includes a first oxide layer, a nitride layer and a second oxide layer. Erasing the NVM cell includes applying a positive gate voltage to inject holes from the gate.

Abstract: A semiconductor device includes a bit line that is provided in a semiconductor substrate, a silicide layer that has side faces and a bottom face surrounded by the bit line and is provided within the bit line, an ONO film that is provided on the semiconductor substrate, and sidewalls that are in contact with the side faces of a trapping layer in the ONO film over the portions of the bit line located on both sides of the silicide layer, the sidewalls being formed with silicon oxide films including phosphorus.

Abstract: A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor region, a tunnel insulating film provided on the semiconductor region, a charge storage insulating film provided on the tunnel insulating film and having a hafnium oxide including a cubic region, a block insulating film provided on the charge storage insulating film, and a control gate electrode provided on the block insulating film.

Abstract: An impurity doping system is disclosed, which includes an impurity doping device for doping an impurity into a surface of a solid state base body, a measuring device for measuring an optical characteristic of an area into which the impurity is doped, and an annealing device for annealing the area into which the impurity is doped. The impurity doping system realizes an impurity doping not to bring about a rise of a substrate temperature, and measures optically physical properties of a lattice defect generated by the impurity doping step to control such that subsequent steps are optimized.

Abstract: A semiconductor memory device includes a memory cell transistor and a first MOS transistor. The memory cell transistor includes a first insulating film, a second insulating film, a control gate electrode, and a first diffusion layer. The first insulating film formed on the first active region. The second insulating film formed on the first insulating film. The control gate electrode formed so as to include a first metal film formed on the second insulating film and a first conductive film formed on the first metal film. The first MOS transistor includes a second conductive film, a second metal film, a third conductive film, and a second diffusion layer. The second conductive film formed on a second active region. The second metal film formed on the second conductive film. The third conductive film formed on a second metal film.

Abstract: Methods of manufacturing vertical semiconductor devices may include forming a mold structure including sacrificial layers and insulating interlayers with a first opening formed therethrough. The sacrificial layers and the insulating interlayers may be stacked repeatedly and alternately on a substrate. The first opening may expose the substrate. Blocking layers may be formed by oxidizing portions of the sacrificial layers exposed by the first opening. A first semiconductor layer pattern, a charge trapping layer pattern and a tunnel insulation layer pattern, respectively, may be formed on the sidewall of the first opening. A second semiconductor layer may be formed on the first polysilicon layer pattern and the bottom of the first opening. The sacrificial layers and the insulating interlayers may be partially removed to form a second opening. The sacrificial layers may be removed to form grooves between the insulating interlayers. Control gate electrodes may be formed in the grooves.

Abstract: A dummy gate stack is created in an area different from a region where the non-volatile memory (NVM) array is located. The dummy gate stack is used to simulate an actual NVM gate stack used in the NVM array. During an etch of the NVM gate stack, the dummy gate stack is also etched so that the end of both the stack etches occur at the same time. This allows for improved end point detection of the NVM gate stack etch due to increased endpoint material being exposed at the end of the etch. Also other tiling features may be formed during the etch of the dummy gate stack.

Abstract: In a vertical power semiconductor device having the super junction structure both in a device section and a terminal section, an n-type impurity layer is formed on the outer peripheral surface in the super junction structure. This allows an electric field on the outer peripheral surface of the super junction structure region to be reduced. Accordingly, a reliable vertical power semiconductor device of a high withstand voltage can be provided.

Abstract: A non-volatile memory device may include a semiconductor substrate including an active region at a surface thereof, a first memory cell string on the active region, and a second memory cell string on the active region. The first memory cell string may include a first plurality of word lines crossing the active region between a first ground select line and a first string select line, and about a same first spacing may be provided between adjacent ones of the first plurality of word lines. The second memory cell string may include a second plurality of word lines crossing the active region between a second ground select line and a second string select line, and about the same first spacing may be provided between adjacent ones of the second plurality of word lines. Related methods are also discussed.