Abstract: A method of processing a substrate including the following steps: providing a silicon substrate that has an etching mask layer with an opening portion at a first surface thereof and has plane orientation of {100} with the surface of the silicon being exposed from the opening portion; preparing a recessed portion that faces from the first surface to a second surface, which is an opposite surface of the first surface, in the opening portion of the silicon substrate; and forming a penetration port that passes through the first surface and the second surface of the silicon substrate by executing crystalline anisotropic etching in the silicon substrate using an etching liquid in which an etching rate for etching a (100) surface of silicon is higher than an etching rate for etching a (110) surface of silicon, from the recessed portion of the silicon substrate toward the second surface.

Abstract: A semiconductor process for improved etch control in which an anisotropic selective etch is used to better control the shape and depth of trenches formed within a semiconductor material. The etchants exhibit preferential etching along at least one of the crystallographic directions, but exhibit an etch rate that is much slower in a second crystallographic direction. As such, one dimension of the etching process is time controlled, a second dimension of the etching process is self-aligned using sidewall spacers of the gate stack, and a third dimension of the etching process is inherently controlled by the selective etch phenomenon of the selective etchant along the second crystallographic direction. A deeper trench is implemented by first forming a lightly doped drain (LDD) region under the gate stack and using the sidewall spacers in combination with the LDD regions to deepen the trenches formed within the semiconductor material.

Abstract: A semiconductor device system, structure, and method of manufacture of a source/drain to retard dopant out-diffusion from a stressor are disclosed. An illustrative embodiment comprises a semiconductor substrate, device, and method to retard sidewall dopant out-diffusion in source/drain regions. A semiconductor substrate is provided with a gate structure, and a source and drain on opposing sides of the gate structure. Recessed regions are etched in a portion of the source and drain. Doped stressors are embedded into the recessed regions. A barrier dopant is incorporated into a remaining portion of the source and drain.

Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

Abstract: The invention provides an etchant composition employed for selectively etching a metallic material in production of a semiconductor device from an insulating material having high dielectric constant, an insulating material of silicon oxide film or silicon nitride film, and a metallic material, characterized in that the etchant composition is an aqueous solution containing a fluorine compound, and a chelating agent having, in the molecular structure thereof, a phosphorus oxo-acid as a functional group; or is an aqueous solution containing a fluorine compound, a chelating agent having, in the molecular structure thereof, a phosphorus oxo-acid as a functional group, and an inorganic acid and/or an organic acid. The invention also provides a method for producing a semiconductor device employing the etchant composition. According to the invention, a metallic material can be etched selectively and efficiently.

Abstract: A semiconductor device with a thinned semiconductor chip and a method for producing the latter is disclosed. In one embodiment, the thinned semiconductor chip has a top side with contact areas and a rear side with a rear side electrode. In this case, the rear side electrode is cohesively connected to a chip pad of a circuit carrier via an electrically conductive layer. In another embodiment, the thinned semiconductor chips of this semiconductor device according to the invention have low-microdefect edge side regions with semiconductor element structures and edge sides patterned by etching technology.

Abstract: A semiconductor template having a top surface aligned along a (100) crystallographic orientation plane and an inverted pyramidal cavity defined by a plurality of walls aligned along a (111) crystallographic orientation plane. A method for manufacturing a semiconductor template by selectively removing silicon material from a silicon template to form a top surface aligned along a (100) crystallographic plane of the silicon template and a plurality of walls defining an inverted pyramidal cavity each aligned along a (111) crystallographic plane of the silicon template.

Abstract: A method of forming buried cavities in a wafer of monocrystalline semiconductor material with at least one cavity formed in a substrate of monocrystalline semiconductor material by timed TMAH etching silicon; covering the cavity with a material inhibiting epitaxial growth; and growing a monocrystalline epitaxial layer above the substrate and the cavities. Thereby, the cavity is completely surrounded by monocrystalline material. Starting from this wafer, it is possible to form a thin membrane. The original wafer must have a plurality of elongate cavities or channels, parallel and adjacent to one another. Trenches are then excavated in the epitaxial layer as far as the channels, and the dividers between the channels are removed by timed TMAH etching.

Abstract: A silicon processing method includes: forming a mask pattern on a principal plane of a single-crystal silicon substrate; and applying crystal anisotropic etching to the principal surface to form a structure including a (111) surface and a crystal surface equivalent thereto and having width W1 and length L1. The principal plane includes a (100) surface and a crystal surface equivalent thereto or a (110) surface and a crystal surface equivalent thereto. A determining section for determining the width W1 of the structure is formed in the mask pattern. The width of the determining section for the width W1 of the mask pattern is width W2. The width of the mask pattern other than the determining section is larger than the width W2 over a length direction of the mask pattern.

Abstract: The invention includes an etchant composition containing isopropyl alcohol and one or more of HF, NH4F and tetramethyl ammonium fluoride (TMAF). The invention encompasses a method of processing a substrate. A substrate is provided which has a first material containing at least one of polysilicon, monocrystalline silicon and amorphous silicon, and a second material. The substrate is exposed to an etch composition which comprises isopropyl alcohol and at least one of HF, NH4F and TMAF. The invention includes a method of processing a semiconductor construction including providing a construction which has a capacitor electrode material and an oxide material along at least a portion of the capacitor electrode material. At least some of the oxide material is removed by isotropic etching utilizing an etchant composition comprising isopropyl alcohol.

Abstract: In accordance with an embodiment of the present invention, a gate structure for a U-shape Metal-Oxide-Semiconductor (UMOS) device includes a dielectric layer formed into a U-shape having side walls and a floor to form a trench surrounding a dielectric layer interior region, a doped poly-silicon layer deposited adjacent to the dielectric layer within the dielectric layer interior region where the doped poly-silicon layer has side walls and a floor surrounding a doped poly-silicon layer interior region, a first metal layer deposited on the doped poly-silicon layer on a side opposite from the dielectric layer where the first metal layer has side walls and a floor surrounding a first metal layer interior region, and an undoped poly-silicon layer deposited to fill the first metal layer interior region.

Abstract: Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain regions with an improved tip shape to improve the performance of the transistor by improving control of short channel effects, increasing the saturation current, improving control of the metallurgical gate length, increasing carrier mobility, and decreasing contact resistance at the interface between the source and drain and the silicide.

Abstract: A method of manufacturing a metal line according to embodiments includes forming an interlayer dielectric layer over a semiconductor substrate. A dielectric layer is formed over the interlayer dielectric layer. A trench may be formed by etching the dielectric layer and the interlayer dielectric layer. A metal material may be disposed over the interlayer dielectric layer including the trench. A first planarization process may be performed on the metal material using the dielectric layer as an etch stop layer. A wet etch process may be performed on the semiconductor substrate subjected the first planarization process. A second planarization process may be performed on interlayer dielectric layer subjected to the wet etch process.

Abstract: A method of manufacturing a semiconductor device comprises: a step of forming an inter-layer insulating film on a semiconductor substrate; a step of forming a first metal film on the inter-layer insulating film; a step of forming a first resist on the first metal film and patterning the first resist; a step of performing anisotropic etching on the first metal film using the first resist as a mask; a step of removing the first resist; a step of forming a second metal film on the inter-layer insulating film so as to cover the remaining first metal film; a step of forming a second resist on the second metal film in an area where the first metal film exists on the inter-layer insulating film and part of an area where the first metal film does not exist; a step of performing anisotropic etching on the second metal film using the second resist as a mask and forming a bonding pad having the first metal film and the second metal film and an upper layer wiring which has the second metal film, yet not the first metal f

Abstract: A (100) silicon substrate is prepared having an insulating film formed on front and back surfaces of the silicon substrate. A resist pattern is formed on the insulating film and partially etched to form an etching mask on the front and back surfaces. The silicon substrate is subjected to anisotropical etching dependent upon an orientation to form a concave horn and a through hole, the concave horn having a bottom with a (100) plane and four inclined sidewalls with a (111) plane, and the through hole gradually narrowing from the front and back surfaces toward an inside of the silicon substrate and having a bottleneck portion with the (111) plane at an intermediate position in the silicon substrate. An LED chip is mounted on the bottom of the concave horn to form an LED package. The LED package is provided which presents high wiring reliability and simplified manufacture processes.

Abstract: Disclosed is an acid etching resistance material comprising a compound having a repeating unit represented by the following general formula (1): (in the general formula (1), R1 is a hydrogen atom or methyl group; R3 is a cyclic group selected from an alicyclic group and an aromatic group; R4 is a polar group; R2 is a group represented by the following general formula (2); and j is 0 or 1): (in the general formula (2), R5 is a hydrogen atom or methyl group).

Abstract: Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the block-seed a first layer, of predetermined thickness of a second material, and subsequently selectively and anisotropically etching it to form a spacer-seed adjacent to the side wall. The cycle of deposition and selective etching steps of a predetermined material are repeated n times (n?2), with at least one spacer formed in each cycle. This predetermined material is different for each pair of consecutive depositions. The above n steps provides at least one multilayer body. Further selective etching removes every other spacers to provide a plurality of nanometric hosting seats, which forms contact terminals for a plurality of molecular transistors hosted in said hosting seats.

Abstract: The present invention provides structures and methods for a transistor formed on a V-shaped groove. The V-shaped groove contains two crystallographic facets joined by a ridge. The facets have different crystallographic orientations than what a semiconductor substrate normally provides such as the substrate orientation or orientations orthogonal to the substrate orientation. Unlike the prior art, the V-shaped groove is formed self-aligned to the shallow trench isolation, eliminating the need to precisely align the V-shaped grooves with lithographic means. The electrical properties of the new facets, specifically, the enhanced carrier mobility, are utilized to enhance the performance of transistors. In a transistor with a channel on the facets that are joined to form a V-shaped profile, the current flows in the direction of the ridge joining the facets avoiding any inflection in the direction of the current.

Abstract: A method for aligning multiple substrates. The method includes providing a handle substrate, providing a spacer substrate, and forming a plurality of first alignment marks on a first surface of the handle substrate. The method also includes forming a plurality of self-limiting alignment marks on a first surface of the spacer substrate and forming a plurality of openings in the spacer substrate, each of the plurality of openings surrounded by standoff regions. The method further includes aligning the first surface of the handle substrate and the first surface of the spacer substrate using the first alignment marks and the self-limiting alignment marks and bonding the handle substrate to the spacer substrate to form a composite substrate structure. In a specific embodiment, the plurality of self-limiting alignment marks and the plurality of openings are formed using an anisotropic wet etching process that preferentially etches the spacer substrate.

Abstract: A three-dimensional structure composed of highly-reliable silicon ultrafine wires, a method for producing the three-dimensional structure, and a device including the same are provided. The three-dimensional structure composed of silicon fine wires includes wires (2) on the order of nanometers to micrometers formed by wet etching utilizing the crystallinity of a single-crystal material.

Abstract: A method for forming a wiring pattern according to an aspect of the invention forms a wiring pattern in a certain area on a substrate by using a droplet discharge technique, and includes forming a bank surrounding the certain area on the substrate; discharging a first functional liquid containing a material of the wiring pattern to an area surrounded by the bank to form a first wiring pattern; discharging a second functional liquid onto the first wiring pattern to form a second wiring pattern; and collectively baking the wiring pattern of a plurality of layers including the first wiring pattern and the second wiring pattern.

Abstract: The present invention relates to a method for fabricating a cavity in substrate for a component for electromagnetic waves, the method comprising providing said cavity by removal of material from said substrate by removal of material by immersing the substrate in a liquid bath of a chemical etchant, so that resultant cavity has a top and a bottom side and sidewalls, and said cavity at one of said top and/or bottom sides exhibits an at least a four sided opening having an opening with at least two different adjacent angles. The invention also relates to the component for microwave applications.

Abstract: A method for texturing surfaces of silicon wafers comprising the steps of dipping the silicon wafers in an etching solution of water, concentrated hydrofluoric acid and concentrated nitric acid and setting a temperature for the etching solution. The etching solution comprises, in percent, 20% to 55% water, 10% to 40% concentrated hydrofluoric acid and 20% to 60% concentrated nitric acid and the temperature of the etching solution is between 0 and 15 degrees Celsius.

Abstract: A three-dimensional structure composed of highly-reliable silicon ultrafine wires, a method for producing the three-dimensional structure, and a device including the same are provided. The three-dimensional structure composed of silicon fine wires includes wires (2) on the order of nanometers to micrometers formed by wet etching utilizing the crystallinity of a single-crystal material.