Characterized By Process Involved To Create Mask, E.g., Lift-off Mask, Sidewall, Or To Modify The Mask, E.g., Pre-treatment, Post-treatment (epo) Patents (Class 257/E21.235)
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Patent number: 11967532Abstract: A method of forming a semiconductor structure includes forming a semiconductor fin over a substrate, forming a dummy gate stack over the semiconductor fin, depositing a dielectric layer over the dummy gate stack, and selectively etching the dielectric layer, such that a top portion and a bottom portion of the dielectric layer form a step profile. The method further includes removing portions of the dielectric layer to form a gate spacer and subsequently forming a source/drain feature in the semiconductor fin adjacent to the gate spacer.Type: GrantFiled: July 8, 2021Date of Patent: April 23, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ta-Chun Lin, Kuo-Hua Pan, Chih-Yung Lin, Jhon Jhy Liaw
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Patent number: 11862464Abstract: A second band-like mask material layer having a first band-like mask material layer of a same planar shape on its top is formed on a mask material layer on a semiconductor layer. Then, fourth band-like mask material layers having third band-like mask material layers of same planar shape on their top are formed on both side surfaces of the first and second band-like mask material layers. Sixth band-like mask material layers having fifth band-like mask material layers of same planar shape on their top are formed on the outside thereof. Then, an orthogonal band-like mask material layer is formed on the first band-like mask material layer, in a direction orthogonal to a direction in which the first band-like mask material layer extends. Semiconductor pillars are formed on overlapping areas of this orthogonal band-like mask material layer and the second and sixth band-like mask material layers by etching the semiconductor layer.Type: GrantFiled: June 11, 2021Date of Patent: January 2, 2024Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Nozomu Harada, Yisuo Li
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Patent number: 11776812Abstract: Devices are made by self-aligned quad pitch patterning (SAQP), staircase patterning and double staircase patterning. Methods for making devices by self-aligned quad pitch patterning (SAQP) use a single spacer in the process. Methods for making devices by staircase patterning and double staircase patterning do not use a spacer. An intermediate process step called self-aligned double patterning (SADP) is used to double the pitch following the spacer deposition. A pattern is formed on a substrate, the pattern having ultra-fine resolutions by repeating the SADP step twice for pitch quadrupling and introducing a reversal layer to form a fine trench pattern and hole pattern. The pattern designs or pattern layouts have improved LER/LWR (line edge roughness and line width roughness respectively) for below 12 nm lines and trenches in order to create self-aligned cross pitch quad trenches.Type: GrantFiled: May 20, 2021Date of Patent: October 3, 2023Assignee: Tokyo Electron LimitedInventors: Daniel Fulford, Anton J. Devilliers
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Patent number: 11705338Abstract: A band-shaped Si pillar having a mask material layer on the top portion thereof is formed on a P+ layer. SiGe layers having mask material layers on the top portions thereof are then formed in contact with the side surfaces of the band-shaped Si pillar and the surfaces of N+ layers and the P+ layer. Si layers having mask material layers on the top portions thereof are then formed in contact with the side surfaces of the SiGe layers and the surfaces of the N+ layers. The outer peripheries of the bottom portions of the Si layers are then removed using the mask material layers as a mask to form band-shaped Si pillars. The mask material layers and the SiGe layers are then removed. Si pillars separated in the Y direction are then formed in the band-shaped Si pillars.Type: GrantFiled: March 29, 2021Date of Patent: July 18, 2023Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Nozomu Harada
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Patent number: 11557480Abstract: Semiconductor devices and fabrication methods thereof are provided. The method may include forming a first sacrificial film on a to-be-etched layer having; and forming second sacrificial layers on the first sacrificial film. A first trench or a second trench is between adjacent second sacrificial layers; and a width of the second trench is greater than a width of the first trench. The method also includes forming a first sidewall spacer on a sidewall surface of a second sacrificial layer, a ratio between the width of the first trench and a thickness of the first sidewall spacer being greater than 2:1; and etching the first sacrificial film using the first sidewall spacer as an etching mask to form first sacrificial layers. A third trench or a second trench is between adjacent first sacrificial layers. The method also includes forming a second sidewall spacer to fill the third trench.Type: GrantFiled: October 22, 2020Date of Patent: January 17, 2023Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Bin Zhang
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Patent number: 11502041Abstract: The present disclosure is related to a method of forming a pattern, including the steps of: providing a structure including a substrate and a target layer, in which the target layer is disposed on the substrate, and the target layer includes a central area and a periphery area; forming a plurality of core patterns and a linear spacer pattern on the central area, in which a width of the linear spacer pattern is wider than 50 nm; covering a photoresist on the periphery area; removing a portion of the central area not covered by the plurality of core patterns and not covered by the linear spacer pattern to form a pattern in the central area, and removing the photoresist, the linear spacer pattern and the plurality of core patterns to expose the pattern.Type: GrantFiled: April 22, 2020Date of Patent: November 15, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Ying-Cheng Chuang
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Patent number: 11430657Abstract: A method for fabricating a semiconductor device includes providing a to-be-etched layer, including alternately arranged first regions and second regions in a first direction. Each first region adjoins adjacent second regions, and each second region includes a trench region. The method includes forming a first mask layer on the to-be-etched layer; implanting doping ions into the first mask layer outside of the trench region; forming a doped separation layer in the first mask layer of the second region to divide the first mask layer into portions arranged in a second direction perpendicular to the first direction; forming a first trench in the first mask layer of the first region; and removing the first mask layer formed in the trench region on both sides of the doped separation layer to form a second trench divided into portions arranged in the second direction by the doped separation layer.Type: GrantFiled: February 28, 2020Date of Patent: August 30, 2022Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Wei Shi, Youcun Hu
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Patent number: 10985264Abstract: A method for fabricating semiconductor device includes: forming a first semiconductor layer and an insulating layer on a substrate; removing the insulating layer and the first semiconductor layer to form openings; forming a second semiconductor layer in the openings; and patterning the second semiconductor layer, the insulating layer, and the first semiconductor layer to form fin-shaped structures.Type: GrantFiled: April 9, 2019Date of Patent: April 20, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chin-Hung Chen, Ssu-I Fu, Chih-Kai Hsu, Chia-Jung Hsu, Yu-Hsiang Lin
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Patent number: 10777413Abstract: Methods of fabricating an interconnect structure. A hardmask is deposited over a dielectric layer, and a block mask is formed that is arranged over an area on the hardmask. After forming the block mask, a first mandrel and a second mandrel are formed on the hardmask. The first mandrel is laterally spaced from the second mandrel, and the area on the hardmask is arranged between the first mandrel and the second mandrel. The block mask may be used to provide a non-mandrel cut separating the tips of interconnects subsequently formed in the dielectric layer.Type: GrantFiled: July 12, 2018Date of Patent: September 15, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Yuping Ren, Guoxiang Ning, Haigou Huang, Sunil K. Singh
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Patent number: 10636869Abstract: FinFET, P-N junctions and methods for forming the same are described herein. In one example, a FinFET is described that includes a fin having a channel region wrapped by a gate, the channel region connecting a source and a drain. A first isolation layer is disposed on a first side of the fin and a second isolation layer is disposed on a second side of the fin, where the second side is opposite of the first side. The second isolation layer has a thickness greater than a thickness of the first isolation layer.Type: GrantFiled: March 9, 2018Date of Patent: April 28, 2020Assignee: XILINX, INC.Inventors: James Karp, Michael J. Hart
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Patent number: 10475941Abstract: A photodetector has a two dimensional conductive channel and a quantum dot layer configured to generate charge on exposure to incident electromagnetic radiation. The surface texture of the quantum dot layer has texturing to provide surface roughness which increases the amount of electromagnetic radiation absorbed in the quantum dot layer in comparison to a photodetector having a flat (non-textured) incident electromagnetic radiation surface.Type: GrantFiled: September 12, 2016Date of Patent: November 12, 2019Assignee: NOKIA TECHNOLOGIES OYInventors: Alexander Bessonov, Adam Robinson, Darryl Cotton, Richard White
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Patent number: 10310379Abstract: A method for patterning a substrate, comprising: providing a photoresist patterning feature on the substrate, the substrate defining a substrate plane, the photoresist patterning feature having a softening temperature below 200° C. The method may include directing a first ion species into the photoresist patterning feature during a first exposure; and depositing a sidewall layer on the patterning feature after the directing at a deposition temperature, the deposition temperature being 200° C. or greater.Type: GrantFiled: March 14, 2017Date of Patent: June 4, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Tristan Y. Ma, Maureen K. Petterson, John Hautala, Steven R. Sherman
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Patent number: 9972538Abstract: Methods for fabricating a semiconductor device include forming a composite film, forming a rough pattern on the composite film, forming a smooth pattern by subjecting the rough pattern to ion implantation and a plasma treatment, and patterning the composite film using the smooth pattern as a first mask.Type: GrantFiled: June 29, 2016Date of Patent: May 15, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Cheol Kim, Dong-Hoon Khang, Do-Hyoung Kim, Seung-Jin Mun, Yong-Joon Choi, Seung-Mo Ha
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Patent number: 9799765Abstract: In an embodiment, this invention relates to a vertical field-effect transistor component including a bottom source-drain layer and a method of creating the same. The method of forming a bottom source-drain layer of a vertical field-effect transistor component can comprise forming an anchor structure on a substrate. A sacrificial layer can be deposited on a middle region of the substrate and a channel layer can be deposited on the sacrificial layer. A plurality of vertical fins can be formed on the substrate and the sacrificial layer can be removed such that the plurality of vertical fins in the middle region form a plurality of floating fins having a gap located between the plurality of floating fins and the substrate. The bottom source-drain layer can then be formed such that the bottom source-drain layer fills in the gap.Type: GrantFiled: June 29, 2016Date of Patent: October 24, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Shogo Mochizuki, Junli Wang
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Patent number: 9716184Abstract: In an embodiment, this disclosure relates to a method of creating an alignment feature within a sidewall image transfer process by the addition of a block mask. The presence of the alignment feature would enable better overlay and alignment for subsequent lithographic stacks.Type: GrantFiled: May 18, 2016Date of Patent: July 25, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Sivananda K. Kanakasabapathy, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
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Patent number: 9536744Abstract: In an embodiment, this disclosure relates to a method of creating an alignment feature within a sidewall image transfer process by the addition of a block mask. The presence of the alignment feature would enable better overlay and alignment for subsequent lithographic stacks.Type: GrantFiled: December 17, 2015Date of Patent: January 3, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Sivananda K. Kanakasabapathy, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
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Patent number: 9509251Abstract: An amplifier module includes a module substrate. Conductive interconnect structures and an amplifier device are coupled to a top surface of the module substrate. The interconnect structures partially cover the module substrate top surface to define conductor-less areas at the top surface. The amplifier device includes a semiconductor substrate, a transistor, a conductive feature coupled to a bottom surface of the semiconductor substrate and to at least one of the interconnect structures, and a filter circuit electrically coupled to the transistor. The conductive feature only partially covers the semiconductor substrate bottom surface to define a conductor-less region that spans a portion of the bottom surface. The conductor-less region is aligned with at least one of the conductor-less areas at the module substrate top surface. The filter circuit includes a passive component formed over a portion of the semiconductor substrate top surface that is directly opposite the conductor-less region.Type: GrantFiled: August 21, 2015Date of Patent: November 29, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventor: Jeffrey K. Jones
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Patent number: 9412566Abstract: Methods are disclosed for depositing material onto and/or etching material from a substrate in a surface processing tool having a processing chamber, a controller and one or more devices for adjusting the process parameters within the chamber. The method comprises: the controller instructing the one or more devices according to a series of control steps, each control step specifying a defined set of process parameters that the one or more devices are instructed to implement, wherein at least one of the control steps comprises the controller instructing the one or more devices to implement a defined set of constant process parameters for the duration of the step, including at least a chamber pressure and gas flow rate through the chamber, which duration is less than the corresponding gas residence time (Tgr) of the processing chamber for the step.Type: GrantFiled: February 27, 2013Date of Patent: August 9, 2016Assignee: Oxford Instruments Nanotechnology Tools LimitedInventors: Mark Edward McNie, Michael Joseph Cooke, Leslie Michael Lea
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Patent number: 9397013Abstract: A method of controlling an etching process for forming fine patterns of a semiconductor device includes forming a lower pattern having a plurality of openings on a substrate, obtaining a width value of the lower pattern, and controlling a process recipe of an etching process for forming the lower pattern by using the width value.Type: GrantFiled: September 15, 2015Date of Patent: July 19, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Chongkwang Chang, Sungwoo Kang, Chunghowan Kim, Youngmook Oh, Seobum Lee, Gahyun Lim
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Patent number: 9029179Abstract: A method for producing a MEMS device having improved charge elimination characteristics includes providing a substrate having one or more layers, and applying a first charge elimination layer onto at least one portion of one given layer of the substrate. The method may then (1) apply a sacrificial layer onto the first charge elimination layer, (2) apply a second charge elimination layer onto at least a portion of the sacrificial layer, and (3) deposit a movable layer onto at least a portion of the second charge elimination layer. To form a structure within the movable layer the method may etch the movable layer. The method may then etch the sacrificial layer to release the structure.Type: GrantFiled: June 28, 2012Date of Patent: May 12, 2015Assignee: Analog Devices, Inc.Inventors: Fang Liu, Kuang L. Yang
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Patent number: 8969998Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of element-separating insulators, and contacts. The plurality of element-separating insulators partition the upper layer portion into a plurality of active areas extending in a first direction. The contacts are connected to the active areas. A recess is made in a part in the first direction of an upper surface of each of the active areas. The recess is made across the entire active area in a second direction orthogonal to the first direction. Positions in the first direction of two of the contacts connected respectively to mutually-adjacent active areas are different from each other. One of the contacts is in contact with a side surface of the recess and not in contact with a bottom surface of the recess.Type: GrantFiled: September 6, 2011Date of Patent: March 3, 2015Assignee: Kabushiki Kaisha ToshibaInventor: Kiyohito Nishihara
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Patent number: 8916428Abstract: A semiconductor device having dislocations and a method of fabricating the semiconductor device is disclosed. The exemplary semiconductor device and method for fabricating the semiconductor device enhance carrier mobility. The method includes providing a substrate having an isolation feature therein and two gate stacks overlying the substrate, wherein one of the gate stacks is atop the isolation feature. The method further includes performing a pre-amorphous implantation process on the substrate. The method further includes forming spacers adjoining sidewalls of the gate stacks, wherein at least one of the spacers extends beyond an edge the isolation feature. The method further includes forming a stress film over the substrate. The method also includes performing an annealing process on the substrate and the stress film.Type: GrantFiled: January 5, 2012Date of Patent: December 23, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsan-Chun Wang, Chun Hsiung Tsai
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Patent number: 8906757Abstract: Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.Type: GrantFiled: November 12, 2012Date of Patent: December 9, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Myeong-Cheol Kim, Il-Sup Kim, Cheol Kim, Jong-Chan Shin, Jong-Wook Lee, Choong-Ho Lee, Si-Young Choi, Jong-Seo Hong
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Patent number: 8895453Abstract: A layer with a laterally varying thickness, a substrate with a first surface and an insulation layer formed on the first surface of the substrate is provided. A plurality of at least one of recesses and openings is formed in the insulation layer, wherein the plurality is arranged at a pitch. Each of the at least one of recesses and openings has a lateral width, wherein at least one of the pitch and the lateral width varies in a lateral direction. The plurality of the at least one of recesses and openings defines a given region in the insulation layer. The insulation layer having the plurality of the at least one of the recesses and openings is tempered at elevated temperatures so that the insulation layer at least partially diffluences to provide the insulation layer with a laterally varying thickness at least in the given region.Type: GrantFiled: April 12, 2013Date of Patent: November 25, 2014Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Johannes Laven, Holger Schulze
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Patent number: 8889561Abstract: Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.Type: GrantFiled: December 10, 2012Date of Patent: November 18, 2014Assignee: GlobalFoundries Inc.Inventors: Youngtag Woo, Jongwook Kye, Dinesh Somasekhar
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Patent number: 8778201Abstract: A pattern forming material contains a block copolymer or graft copolymer and forms a structure having micro polymer phases, in which, with respect to at least two polymer chains among polymer chains constituting the block copolymer or graft copolymer, the ratio between N/(Nc?No) values of monomer units constituting respective polymer chains is 1.4 or more, where N represents total number of atoms in the monomer unit, Nc represents the number of carbon atoms in the monomer unit, No represents the number of oxygen atoms in the monomer unit.Type: GrantFiled: October 21, 2011Date of Patent: July 15, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Koji Asakawa, Toshiro Hiraoka, Yoshihiro Akasaka, Yasuyuki Hotta
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Patent number: 8765612Abstract: A double patterning process is described. A substrate having a first area and a second area is provided. A target layer is formed over the substrate. A patterned first photoresist layer is formed over the target layer, wherein the patterned first photoresist layer has openings and has a first thickness in the first area, and at least a portion of the patterned first photoresist layer in the second area has a second thickness less than the first thickness. A second photoresist layer is then formed covering the patterned first photoresist layer and filling in the openings.Type: GrantFiled: September 14, 2012Date of Patent: July 1, 2014Assignee: Nanya Technology CorporationInventors: Jenn-Wei Lee, Hung-Jen Liu
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Patent number: 8629064Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing.Type: GrantFiled: June 23, 2011Date of Patent: January 14, 2014Assignee: ASML Netherlands B.V.Inventors: Xiaoyang Li, Duan-Fu Stephen Hsu
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Patent number: 8575004Abstract: The present invention related to a lift-off structure adapted to a substrate having a photoelectric device, the structure comprising: a buffer layer, forming on the substrate; an upper sacrificial layer, forming on the buffer layer; an etch stop layer, forming on the upper sacrificial layer, and the photoelectric device structure forming on the etch stop layer.Type: GrantFiled: October 14, 2011Date of Patent: November 5, 2013Assignee: Institute of Nuclear Energy Research Atomic Energy Council, Executive YuanInventors: Yu-Li Tsai, Chih-Hung Wu, Jei-Li Ho, Chao-Huei Huang, Min-De Yang
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Patent number: 8574971Abstract: An approach for patterning and etching without a mask is provided in a manufacturing a thin-film transistor, a gate electrode, a gate insulating layer, a semiconductor layer, an ohmic contact layer and source metal layer of a substrate. A first photoresist pattern including a first photo pattern and a second photo pattern is formed using a digital exposure device by generating a plurality of spot beams, the first photo pattern is formed to a first region of the base substrate and has a first thickness, and the second photo pattern is formed to a second region adjacent to the first region, and has a second thickness and a width in a range of about 50% to about 60% of a diameter of the spot beam. The source metal layer is patterned to form a source electrode and a drain electrode, and the source electrode and the drain electrode are spaced apart from each other in the first region of an active pattern.Type: GrantFiled: October 8, 2010Date of Patent: November 5, 2013Assignee: Samsung Display Co., Ltd.Inventors: Sang-Hyun Yun, Cha-Dong Kim, Jung-In Park, Hi-Kuk Lee
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Patent number: 8569185Abstract: A method for fabricating an integrated device is disclosed. In an embodiment, a hard mask layer with a limited thickness is formed over a gate electrode layer. A treatment is provided to the hard mask layer to make the hard mask layer more resistant to a wet etch solution. Then, a patterning is provided on the treated hard mask layer and the gate electrode to from a gate structure.Type: GrantFiled: February 5, 2010Date of Patent: October 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Hui Ouyang, Han-Pin Chung, Shiang-Bau Wang
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Patent number: 8541311Abstract: Embodiments of a method for fabricating integrated circuits are provided. In one embodiment, the method includes the steps of depositing a dielectric layer over a semiconductor device, forming a plurality of trimmed hardmask structures at predetermined locations over the dielectric layer, embedding the plurality of trimmed hardmask structures in a surrounding hardmask layer, removing the plurality of trimmed hardmask structures to create a plurality of openings through the surrounding hardmask layer, and etching the dielectric layer through the plurality of openings to form a plurality of etch features therein.Type: GrantFiled: December 22, 2010Date of Patent: September 24, 2013Assignee: GLOBALFOUNDRIES, Inc.Inventor: Dmytro Chumakov
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Patent number: 8486287Abstract: Fabrication methods disclosed herein provide for a nanoscale structure or a pattern comprising a plurality of nanostructures of specific predetermined position, shape and composition, including nanostructure arrays having large area at high throughput necessary for industrial production. The resultant nanostracture patterns are useful for nanostructure arrays, specifically sensor and catalytic arrays.Type: GrantFiled: October 14, 2004Date of Patent: July 16, 2013Assignee: The Regents of the University of CaliforniaInventors: Ji Zhu, Jeff Grunes, Yang-Kyu Choi, Jeffrey Bokor, Gabor Somorjai
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Patent number: 8461054Abstract: A method of manufacturing a liquid crystal display device which includes pixel electrodes and common electrodes which are alternatively arranged in each pixel defined on a substrate, including the steps of: forming a conductive film on the substrate; forming a mask layer, of which etching selection ratio is different from the conductive layer, on the conductive layer; forming a photo-resist pattern of a fixed pattern on the mask layer; forming a mask pattern, which has an undercut shape to the photo-resist pattern, by etching the mask layer by use of the photo-resist pattern as an etching mask; removing the photo-resist pattern; and etching the conductive film by use of the mask pattern as an etching mask, to provide at least any one of the common electrode and the pixel electrode.Type: GrantFiled: October 7, 2008Date of Patent: June 11, 2013Assignee: LG Display Co., Ltd.Inventors: Kye-Chan Song, Jeong Oh Kim, Young Kwon Kang
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Patent number: 8460948Abstract: A method for manufacturing an ink jet recording head is employed which has a metal mask formation process for forming a metal mask having a predetermined shape containing a silicide film formed by silicidation of the surface of a flow path forming substrate wafer containing a silicon substrate and a liquid flow path formation process for forming a liquid flow path by anisotropically etching the flow path forming substrate wafer using the metal mask as a mask.Type: GrantFiled: April 3, 2012Date of Patent: June 11, 2013Assignee: Seiko Epson CorporationInventor: Yasuyuki Matsumoto
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Patent number: 8450214Abstract: A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.Type: GrantFiled: August 30, 2012Date of Patent: May 28, 2013Assignee: Micron Technology, Inc.Inventors: Whonchee Lee, Janos Fucsko, David H. Wells
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Patent number: 8435416Abstract: A pattern forming material contains a block copolymer or graft copolymer and forms a structure having micro polymer phases, in which, with respect to at least two polymer chains among polymer chains constituting the block copolymer or graft copolymer, the ratio between N/(Nc-No) values of monomer units constituting respective polymer chains is 1.4 or more, where N represents total number of atoms in the monomer unit, Nc represents the number of carbon atoms in the monomer unit, No represents the number of oxygen atoms in the monomer unit.Type: GrantFiled: October 21, 2011Date of Patent: May 7, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Koji Asakawa, Toshiro Hiraoka, Yoshihiro Akasaka, Yasuyuki Hotta
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Patent number: 8358010Abstract: A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer; realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area.Type: GrantFiled: February 28, 2005Date of Patent: January 22, 2013Assignee: STMicroelectronics S.r.l.Inventors: Danilo Mascolo, Gianfranco Cerofolini
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Patent number: 8324110Abstract: Disclosed are a field effect transistor structure and a method of forming the structure. A gate stack is formed on the wafer above a designated channel region. Spacer material is deposited and anisotropically etched until just prior to exposing any horizontal surfaces of the wafer or gate stack, thereby leaving relatively thin horizontal portions of spacer material on the wafer surface and relatively thick vertical portions of spacer material on the gate sidewalls. The remaining spacer material is selectively and isotropically etched just until the horizontal portions of spacer material are completely removed, thereby leaving only the vertical portions of the spacer material on the gate sidewalls. This selective isotropic etch removes the horizontal portions of spacer material without damaging the wafer surface. Raised epitaxial source/drain regions can be formed on the undamaged wafer surface adjacent to the gate sidewall spacers in order to tailor source/drain resistance values.Type: GrantFiled: February 2, 2010Date of Patent: December 4, 2012Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Yu Zhu
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Patent number: 8298954Abstract: A cap material layer is deposited on a metal nitride layer. An antireflective coating (ARC) layer, an organic planarizing layer (OPL), and patterned line structures are formed upon the cap material layer. The pattern in the patterned line structures is transferred into the ARC layer and the OPL. Exposed portions of the cap material layer are etched simultaneously with the etch removal of the patterned line structures and the ARC layer. The OPL is employed to etch the metal nitride layer. The patterned cap material layer located over the metal nitride layer protects the top surface of the metal nitride layer, and enables high fidelity reproduction of the pattern in the metal nitride layer without pattern distortion. The metal nitride layer is subsequently employed as an etch mask for pattern transfer into an underlying layer.Type: GrantFiled: May 6, 2011Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: John C. Arnold, Sean D. Burns, Matthew E. Colburn, David V. Horak, Yunpeng Yin
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Patent number: 8212345Abstract: A backgrinding machine 10 of a semiconductor wafer W includes: a table 13 set on the working plane of a mount 11; a multiple number of holding jigs 20 arranged via check tables 15 on table 13; a grinding machine 30 for performing a grinding process of the rear side of semiconductor wafer W held by holding jig 20; and a washing device 40 for ground semiconductor wafers W. Each holding jig 20 is constructed of a concave 22 depressed on the surface of a base plate 21, a multiple number of supporting projections 23 projectively arrayed on the bottom surface of concave 22, a deformable contact film 24, covering the concave 22, being supported by the multiple supporting projections 23, for detachably holding semiconductor wafer W in close contact with it; and an exhaust path 25 for conducting air from the concave 22 covered by contact film 24 to the outside.Type: GrantFiled: November 12, 2010Date of Patent: July 3, 2012Assignees: Shin-Etsu Polymer Co., Ltd., Lintec CorporationInventors: Kiyofumi Tanaka, Satoshi Odashima, Noriyoshi Hosono, Hironobu Fujimoto, Takeshi Segawa
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Patent number: 8183152Abstract: A method of fabricating a semiconductor device facilitates the forming of a conductive pattern of features having different widths. A conductive layer is formed on a substrate, and a mask layer is formed on the conductive layer. First spaced apart patterns are formed on the mask layer and a second pattern including first and second parallel portion is formed beside the first patterns on the mask layer. First auxiliary masks are formed over ends of the first patterns, respectively, and a second auxiliary mask is formed over the second pattern as spanning the first and second portions of the second pattern. The mask layer is then etched to form first mask patterns below the first patterns and a second mask pattern below the second pattern. The first and second patterns and the first and second auxiliary masks are removed. The conductive layer is then etched using the first and second mask patterns as an etch mask.Type: GrantFiled: October 14, 2010Date of Patent: May 22, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwang Sim, Yoon-Moon Park, Keon-Soo Kim, Min-Sung Song, Young-Ho Lee
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Patent number: 8133804Abstract: A method of reducing the roughness profile in a plurality of patterned resist features. Each patterned resist feature includes a first sidewall and a second sidewall opposite the first sidewall, wherein each patterned resist feature comprises a mid frequency line width roughness and a low frequency linewidth roughness. A plurality of ion exposure cycles are performed, wherein each ion exposure cycle comprises providing ions at a tilt angle of about five degrees or larger upon the first sidewall, and providing ions at a tilt angle of about five degrees or larger upon the second sidewall. Upon the performing of the plurality of ion exposure cycles the mid frequency and low frequency linewidth roughness are reduced.Type: GrantFiled: October 1, 2010Date of Patent: March 13, 2012Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Joseph C. Olson, Patrick M. Martin
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Patent number: 8106470Abstract: An integrated circuit structure includes a substrate having a top surface; a first conductive layer over and contacting the top surface of the substrate; a dielectric layer over and contacting the first conductive layer, wherein the dielectric layer includes an opening exposing a portion of the first conductive layer; and a proof-mass in the opening and including a second conductive layer at a bottom of the proof-mass. The second conductive layer is spaced apart from the portion of the first conductive layer by an air space. Springs anchor the proof-mass to portions of the dielectric layer encircling the opening. The springs are configured to allow the proof-mass to make three-dimensional movements.Type: GrantFiled: March 31, 2010Date of Patent: January 31, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ting-Hau Wu, Chun-Wen Cheng, Chun-Ren Cheng, Shang-Ying Tsai, Jung-Huei Peng, Jiou-Kang Lee, Allen Timothy Chang
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Patent number: 8084360Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first film containing boron (B) on a member to be etched, the member being a semiconductor substrate, or a film formed on the semiconductor substrate, and forming a second film formed of a silicon oxide film on the first film. The method further includes pressing an original plate having a pattern formed in an uneven shape onto the second film to transfer the pattern to the second film, and etching the first film by using the second film where the pattern is transferred as a mask, with an etching gas that contains fluoromethane (CH3F) and oxygen (O2) and has an oxygen concentration of 50 to 90 at. %, to transfer the pattern to the first film. The method further includes etching the member by using the first film where the pattern is transferred as a mask, to form a concave portion having the pattern in the member.Type: GrantFiled: December 9, 2010Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yusuke Kasahara, Hisataka Hayashi
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Patent number: 8030222Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.Type: GrantFiled: July 31, 2006Date of Patent: October 4, 2011Assignee: Round Rock Research, LLCInventors: Luan Tran, Bill Stanton
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Patent number: 7947589Abstract: A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer (19) that is isolated from an underlying first single crystal semiconductor layer (17) by a buried insulator layer (18); patterning and etching the second single crystal semiconductor layer (19) to form a single crystal mandrel (42) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers (52) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel (42) while substantially retaining the oxide spacers (52); and selectively etching the first single crystal semiconductor layer (17) using the oxide spacers (52) to form one or more FinFET channel regions (92).Type: GrantFiled: September 2, 2009Date of Patent: May 24, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Ramachandran Muralidhar, Marwan H. Khater
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Patent number: 7928005Abstract: A method of forming multiple conductive structures in a semiconductor device includes forming spacers adjacent side surfaces of a mask, where the mask and the spacers are formed on a conductive layer. The method also includes etching at least one trench in a portion of the conductive layer not covered by the spacers or the mask. The method may further include depositing a material over the semiconductor device, removing the mask and etching the conductive layer to remove portions of the conductive layer not covered by the spacers or the material, where remaining portions of the conductive layer form the conductive structures.Type: GrantFiled: September 27, 2005Date of Patent: April 19, 2011Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: Michael Brennan, Scott Bell
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Patent number: 7927991Abstract: In a manufacturing process of a semiconductor device, a manufacturing technique for reducing the number of lithography processes that use a photoresist and simplifying the process is provided, which improves throughput. An etching mask for forming a pattern of a layer to be processed such as a conductive layer or a semiconductor layer is manufactured without using a lithography technique that uses a photoresist. The etching mask is formed of a light absorption layer including a material which absorbs a laser beam. The mask is formed by irradiating the light absorption layer with a laser beam through a photomask and utilizing laser ablation by energy of the laser beam absorbed by the light absorption layer.Type: GrantFiled: August 15, 2007Date of Patent: April 19, 2011Assignee: Semiconductor Energy laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Yasuhiro Jinbo, Eiji Higa, Shunpei Yamazaki
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Patent number: 7927901Abstract: A method for fabricating a light emitting diode chip is provided. In the method, a half-tone mask process, a gray-tone mask process or a multi-tone mask process is applied and combined with a lift-off process to further reduce process steps of the light emitting diode chip. In the present invention, some components may also be simultaneously formed by an identical process to reduce the process steps of the light emitting diode chip. Consequently, the fabricating method of the light emitting diode provided in the present invention reduces the cost and time for the fabrication of the light emitting diode.Type: GrantFiled: October 16, 2008Date of Patent: April 19, 2011Assignee: Lextar Electronics Corp.Inventors: Kuo-Lung Fang, Chien-Sen Weng, Chih-Wei Chao