Abstract: An exemplary method for forming spacer stacks with metallic compound layers is provided. The method includes forming magnetic tunnel junction (MTJ) structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method also includes disposing a second spacer layer—which includes a metallic compound—over the first spacer material, the MTJ structures, and the interconnect layer so that the second spacer layer is thinner than the first spacer layer. The method further includes depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.

Abstract: A method includes providing a substrate; forming mandrel patterns over the substrate; and forming spacers on sidewalls of the mandrel patterns. The method further includes removing the mandrel patterns, thereby forming trenches that are at least partially surrounded by the spacers. The method further includes depositing a copolymer material in the trenches, wherein the copolymer material is directed self-assembling; and inducing microphase separation within the copolymer material, thereby defining a first constituent polymer surrounded by a second constituent polymer. The mandrel patterns have restricted sizes and a restricted configuration. The first constituent polymer includes cylinders arranged in a rectangular or square array.

Abstract: A method for forming a titanium oxide film on a substrate to be processed, which has a silicon portion on a surface thereof, the method including: forming a first titanium oxide film on the surface of the substrate to be processed, which includes the silicon portion, by means of thermal ALD by alternately supplying a titanium-containing gas and a gas containing hydrogen and oxygen serving as an oxidizing agent in a first stage; and forming a second titanium oxide film on the first titanium oxide film by means of plasma ALD by alternately supplying a titanium-containing gas and plasma of an oxygen-containing gas as an oxidizing agent in a second stage.

Abstract: In the method, a sidewall pattern is formed in a side wall of a first resist pattern that is formed on a second hard mask layer of a base material in which first and second hard mask layers are laminated in the order of description, a second hard mask pattern is formed by etching the second hard mask layer by using the sidewall pattern as a mask, a first hard mask pattern is formed by etching the first hard mask layer by using, as a mask, the second hard mask pattern and a second resist pattern that is formed on the first hard mask layer of the base material, and the first and second fine patterns are formed by etching the base material by using the first hard mask pattern as a mask.

Abstract: Methodology enabling a generation of fins having a variable fin pitch less than 40 nm, and the resulting device are disclosed. Embodiments include: forming a hardmask on a substrate; providing first and second mandrels on the hardmask; providing a first spacer on each side of each of the first and second mandrels; removing the first and second mandrels; providing, after removal of the first and second mandrels, a second spacer on each side of each of the first spacers; and removing the first spacers.

Abstract: A target space ratio of a monitor pattern on a substrate for inspection is determined to be different from a ratio of 1:1. A range of space ratios in a library is determined to include the target space ratio and not include a space ratio of 1:1. The monitor pattern is formed on a film to be processed by performing predetermined processes on the substrate for inspection. Sizes of the monitor pattern are measured. The sizes of the monitor pattern are converted into sizes of a pattern of the film to be processed having a space ratio of 1:1, and processing conditions of the predetermined processes are compensated for based on the sizes of the converted pattern of the film to be processed. After that, the predetermined processes are performed on a wafer under the compensated conditions to form a pattern having a space ratio of 1:1 on the film to be processed.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of second core films, the second core film having a first array portion, and a second array portion which is arranged so as to be spaced at a larger second space than the first space in the first direction from the first array portion, the second space being positioned above the loop portion. The method includes processing the second film to be processed below the first array portion into a second line and space pattern which includes a second line pattern extending in the second direction, and removing the second film to be processed below the second space and the loop portion of the first film to be processed, by an etching using the second spacer film as a mask.

Abstract: The present invention relates to lithographic apparatuses and processes, and more particularly to multiple patterning lithography for printing target patterns beyond the limits of resolution of the lithographic apparatus. Self-aligned assist pattern (SAP) is derived from original design layout in an automated manner using geometric Boolean operations based on some predefined design rules, and are included in the mask layout for efficient self-alignment of various sub-layouts of the target pattern during a multiple patterning lithography process. SAP can be of any shape and size, and can have continuous features (e.g., a ring), or discontinuous (e.g., bars not connected to each other) features. An end-to-end multiple patterning lithography using spacer and SAP may use positive tone lithography, and/or negative tone lithography for line and/or space printing.

Abstract: A method for sidewall spacer line doubling uses thermal atomic layer deposition (ALD) of a titanium oxide (TiOx) spacer layer. A hardmask layer is deposited on a suitable substrate. A mandrel layer of diamond-like carbon (DLC) is deposited on the hardmask layer and patterned into stripes with tops and sidewalls. A layer of TiOx is deposited, by thermal ALD without the assistance of plasma or ozone, on the tops and sidewalls of the mandrel stripes. Thermal ALD of the TiO2, without energy assistance by plasma or ozone, has been found to cause no damage to the DLC mandrel stripes. After removal of the TiOx from the tops of the mandrel stripes and removal of the mandrel stripes, stripes of TiO2 are left on the hardmask layer and may be used as an etch mask to transfer the pattern into the hardmask layer.

Abstract: A method includes making a target feature of an integrated circuit by providing a main layer over a substrate, depositing a first mask layer over the main layer, patterning the first mask layer, forming sidewall spacers with a width (w) in adjoining sidewalls of the patterned first mask layer and exposing a top area of the patterned first mask layer, selectively removing the first mask layer and exposing a portion of the main layer between the sidewall spacers, depositing a second mask layer over the main layer between the sidewall spacers, selectively removing the sidewall spacers to form an opening and exposing another portion of the main layer in the opening, etching the main layer through the opening to form the target feature.

Abstract: A method for realizing a nanometric circuit architecture includes: realizing plural active areas on a semiconductor substrate; realizing on the substrate a seed layer of a first material; realizing a mask-spacer of a second material on the seed layer in a region comprised between the active areas; realizing a mask overlapping the mask-spacer and extending in a substantially perpendicular direction thereto; selectively removing the seed layer exposed on the substrate; selectively removing the mask and the mask-spacer obtaining a seed-spacer comprising a linear portion extending in that region and a portion substantially orthogonal thereto; realizing by MSPT from the seed-spacer an insulating spacer reproducing at least part of the profile of the seed-spacer; realizing by MSPT a nano-wire of conductive material from the seed-spacer or insulating spacer, the nano-wire comprising a first portion at least partially extending in the region and a second portion contacting a respective active area.

Abstract: Methods for producing self-aligned, self-assembled sub-ground-rule features without the need to use additional lithographic patterning. Specifically, the present disclosure allows for the creation of assist features that are localized and self-aligned to a given structure. These assist features can either have the same tone or different tone to the given feature.

Abstract: Semiconductor device with a first structure comprising a plurality of at least in part parallel linear structures, a second structure comprising a plurality of pad structures, forming at least in part one of the group of linear structure, curved structure, piecewise linear structure and piecewise curved structure which is positioned at an angle to the first structure, and the plurality of pad structures are intersecting at least one of the linear structures in the first structure. An electronic device with at least one semiconductor device, methods for manufacturing a semiconductor device and a mask system are also covered.

Abstract: A method and apparatus involve providing a substrate having a dielectric layer formed thereon, forming a photoresist mask over the dielectric layer, the photoresist mask defining an opening, etching the dielectric layer through the at least one opening in the photoresist mask, treating a portion of the photoresist mask with an etching species, and removing the treated photoresist mask with a supercritical fluid. The etching, treating, and removing can be performed in one chamber.

Abstract: A method of fabricating a semiconductor device forms a micro-sized gate, and mitigates short channel effects. The method includes a pull-back process to form the gate on a substrate. The method also includes forming inner and outer spacers on the gate that are asymmetric to one another with respect to the gate, and using the spacers in forming junction regions in the substrate on opposite sides of the gate. In particular, the inner and outer spacers are formed on opposite sides of the gate so as to have different thicknesses at the bottom of the gate. The inner and outer junction regions are formed by doping the substrate before and after the spacers are formed. Thus, the inner and outer junction regions have extension regions under the inner and outer spacers, respectively, and the extension regions have different lengths.

Abstract: A method of forming a pattern on a wafer is provided. The method includes applying a photoresist on the wafer and exposing the wafer to define a first pattern on the photoresist. The method also includes exposing the wafer to define a second pattern on the photoresist, wherein each of the first and second patterns comprises unexposed portions of the photoresist and developing the wafer to form the first and second patterns on the photoresist, wherein the first and second patterns are formed by removing the unexposed portions of the photoresist.

Abstract: A patterning method with a filling material with a T-shaped cross section is used as a mask during patterning to produce structures having sublithographic dimensions, such as a double-fin field effect transistor.

Abstract: A method of etching a substrate is provided. The method of etching a substrate includes transferring a pattern into the substrate using a double patterned amorphous carbon layer on the substrate as a hardmask. Optionally, a non-carbon based layer is deposited on the amorphous carbon layer as a capping layer before the pattern is transferred into the substrate.

Abstract: A method for manufacturing a semiconductor device includes forming a gate conductive layer, a first mask layer, a second mask layer, and a third mask layer over a semiconductor substrate that includes a cell region and a peripheral region. The method also includes forming a second mask pattern and a third mask pattern using a gate mask. The method further includes trimming the second mask pattern in the peripheral region to form a fourth mask pattern having a size smaller than that of the second mask pattern. Still further, the method includes removing the third mask pattern, and patterning the first mask layer and the gate conductive layer using the fourth mask pattern as a mask.

Abstract: Example embodiments may provide fine patterns for semiconductor devices and methods of forming fine patterns for semiconductor devices. Example methods may include forming a spacer pattern on a substrate and/or an insulating layer pattern adjacent to sides of the spacer pattern and/or disposed at the same level as the spacer pattern, forming a pair of recesses exposing sides of the spacer pattern by removing a portion of the insulating layer pattern, and/or filling a conductive material in the recesses.

Abstract: A method for forming a pattern of a semiconductor device comprises forming a spacer with an oxide film in a SPT process, and removing the spacer formed to have a horn shape before etching an underlying layer, so that the horn shape is transcribed in a lower portion, thereby facilitating control of critical dimension in etching the underlying layer so as to improve a characteristic of the device. A method for forming a pattern of a semiconductor device of the present invention comprises: forming an underlying layer and a hard mask layer over a semiconductor substrate; forming a sacrificial pattern over the hard mask layer; forming a spacer at both sides of the sacrificial pattern; removing the sacrificial pattern to remain the spacer; etching the hard mask layer with the spacer as a mask to form a hard mask pattern; removing the spacer; and etching the underlying layer with the hard mask pattern as a mask.

Abstract: A patterning method comprising (a) providing a substrate having a sacrificial layer made of a first material, partially or totally formed on the substrate, (b) forming pattern grooves, which are free from the first material and have a line width of a first resolution or lower, on the sacrificial layer by using a first means, by which the sacrificial layer is directly processed to form a line, (c) filling the pattern grooves with a second material to a second resolution by using a second means, to form a pattern of the second material on the substrate. This method provides a high-resolution pattern with little or no waste of the second material, thereby reducing production costs. The method uses first high resolution means, such as focused energy beams of laser, combined with a low resolution means, such as ink-jet, to efficiently provide a high-resolution pattern.

Abstract: A method for forming a fine pattern of a semiconductor device comprises: forming a first hard mask film and an etch barrier film over a semiconductor substrate; forming a sacrificial pattern over the etch barrier film; forming a spacer on sidewalls of the sacrificial pattern; removing the sacrificial pattern; etching the etch barrier film and the hard mask film with the spacer as an etch mask to form an etch barrier pattern and a hard mask pattern; and removing the spacer and the etch barrier pattern, thereby improving yield and reliability of the device.

Abstract: In a method of forming micro patterns, an etch target layer, a hard mask layer, a silicon-containing bottom anti-reflective coating (BARC) layer, and first auxiliary patterns are formed over a semiconductor substrate. The silicon-containing BARC layer is etched to form silicon-containing BARC patterns. Insulating layers are formed on a surface of the silicon-containing BARC patterns and the first auxiliary patterns. A second auxiliary layer is formed on the hard mask layer and the insulating layers. An etch process is performed such that the second auxiliary layer remains on the hard mask layer between the silicon-containing BARC patterns thereby forming second auxiliary patterns. The insulating layers on the first auxiliary patterns and between the silicon-containing BARC patterns and the second auxiliary patterns are removed. The hard mask layer is etched thereby forming hard mask patterns. The etch target layer is etched using the hard mask patterns as an etch mask.

Abstract: A FinFET includes a plurality of semiconductor fins. Over a semiconductor layer, patterned features (e.g. of minimum photolithographic size and spacing) are formed. In one example of fin formation, a first set of sidewall spacers are formed adjacent to the sides of these patterned features. A second set of sidewall spacers of a different material are formed adjacent to the sides of the first set of sidewall spacers. The first set of sidewall spacers are removed leaving the second set of sidewall spacers spaced from the patterned features. Both the second set of sidewall spacers and the patterned features are used as a mask to an etch that leaves semiconductor fins patterned as per the second set of sidewall spacers and the patterned features. These resulting semiconductor fins, which have sub-lithographic spacings, are then used for channels of a FinFET transistor.

Abstract: According to various embodiments, the present teachings include various methods for forming a semiconductor device, computer readable medium for forming a semiconductor device, mask sets for forming a semiconductor device, and a semiconductor device made according to various methods. For example, a method can comprise forming a first feature and a second feature on a substrate by exposing a first mask to a first beam, wherein the second feature is disposed adjacent to the first feature, exposing a second mask to a second beam, and removing the second feature from the substrate.