Doping Insulating Layer (epo) Patents (Class 257/E21.247)
  • Publication number: 20080299774
    Abstract: Self-assembling materials, such as block copolymers, are used as mandrels for pitch multiplication. The copolymers are deposited over a substrate and directed to self-assemble into a desired pattern. One of the blocks forming the block copolymers is selectively removed. The remaining blocks are used as mandrels for pitch multiplication. Spacer material is blanket deposited over the blocks. The spacer material is subjected to a spacer etch to form spacers on sidewalls of the mandrels. The mandrels are selectively removed to leave free-standing spacers. The spacers may be used as pitch-multiplied mask features to define a pattern in an underlying substrate.
    Type: Application
    Filed: June 4, 2007
    Publication date: December 4, 2008
    Applicant: Micron Technology, Inc.
    Inventor: Gurtej Sandhu
  • Publication number: 20080293248
    Abstract: The present invention relates to a method of forming an amorphous carbon film and a method of manufacturing a semiconductor device using the method. An amorphous carbon film is formed on a substrate by vaporizing a liquid hydrocarbon compound, which has chain structure and one double bond, and supplying the compound to a chamber, and ionizing the compound. The amorphous carbon film is used as a hard mask film. It is possible to easily control characteristics of the amorphous carbon film, such as a deposition rate, an etching selectivity, a refractive index (n), a light absorption coefficient (k) and stress, so as to satisfy user's requirements. In particular, it is possible to lower the refractive index (n) and the light absorption coefficient (k). As a result, it is possible to perform a photolithography process without an antireflection film that prevents the diffuse reflection of a lower material layer.
    Type: Application
    Filed: August 15, 2007
    Publication date: November 27, 2008
    Applicant: TES CO., LTD.
    Inventors: Keun Oh Park, Byoung Dae An, Seung Jun Lee
  • Patent number: 7456042
    Abstract: Many inventions are disclosed. Some aspects are directed to MEMS, and/or methods for use with and/or for fabricating MEMS, that supply, store, and/or trap charge on a mechanical structure disposed in a chamber. Various structures may be disposed in the chamber and employed in supplying, storing and/or trapping charge on the mechanical structure. In some aspects, a breakable link, a thermionic electron source and/or a movable mechanical structure are employed. The breakable link may comprise a fuse. In one embodiment, the movable mechanical structure is driven to resonate. In some aspects, the electrical charge enables a transducer to convert vibrational energy to electrical energy, which may be used to power circuit(s), device(s) and/or other purpose(s). In some aspects, the electrical charge is employed in changing the resonant frequency of a mechanical structure and/or generating an electrostatic force, which may be repulsive.
    Type: Grant
    Filed: June 4, 2006
    Date of Patent: November 25, 2008
    Assignee: Robert Bosch GmbH
    Inventors: Brian H. Stark, Markus Lutz, Aaron Partridge
  • Publication number: 20080233738
    Abstract: A method is provided for fabricating a semiconductor device which includes a first contact point and a second contact point located above the first contact point. A first material layer is conformally deposited over the contact points, and a second material layer is deposited. A photoresist layer is applied and patterned to leave remaining portions. The remaining portions are trimmed to produce trimmed remaining portions which overlie eventual contact holes to the contact points. Using the trimmed remaining portions as an etch mask, exposed portions the second material layer are etched away to leave sacrificial plugs. The sacrificial plugs are etched away to form contact holes that reach portions the first material layers. Another etching step is performed to extend the contact holes to produce final contact holes that extend to the contact points.
    Type: Application
    Filed: March 22, 2007
    Publication date: September 25, 2008
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Sven BEYER, Kamatchi SUBRAMANIAN
  • Patent number: 7411237
    Abstract: Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is arranged as a structure of one or more monolayers, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: August 12, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Publication number: 20080178932
    Abstract: This invention relates to a photovoltaic device including an electrode such as a front electrode/contact. In certain example embodiments, the front electrode of the photovoltaic device includes a multi-layered transparent conductive coating which is sputter-deposited on a textured surface of a patterned glass substrate. In certain example embodiments, a maximum transmission area of the substantially transparent conductive front electrode is located under a peak area of a quantum efficiency (QE) and/or QEx (photon flux of solar radiation) curve of the photovoltaic device and a light source spectrum used to power the photovoltaic device. In certain example embodiments, the front electrode includes a transparent conductive layer of or including one or more of (i) titanium zinc oxide doped with aluminum and/or niobium, and/or (ii) titanium niobium oxide.
    Type: Application
    Filed: December 3, 2007
    Publication date: July 31, 2008
    Applicant: Guardian Industries Corp.
    Inventors: Willem Den Boer, Yiwei Lu
  • Publication number: 20080176406
    Abstract: Methods for fabricating semiconductor structures are provided. A first layer may be deposited onto a substrate followed by the deposition of a second layer onto the first layer. A plurality of line structures may be etched in the second layer. A third layer, deposited onto the plurality of line structures of the second layer, may subsequently be etched to expose the plurality of line structures in the second layer. The plurality of line structures in the second layer may be removed, leaving an etched third layer. The etched third layer may be used as a mask to etch the first layer to form a semiconductor structure in the first layer. In some respects, the methods may include steps for etching the substrate using the etched first layer. The methods may also provide annealing the etched substrate to form a corrugate substrate surface.
    Type: Application
    Filed: January 22, 2007
    Publication date: July 24, 2008
    Inventors: Shuji Ikeda, Jeff Wetzel, James Beach, Charles Stager, Michael Gotskowski, Andrew Collin Campbell
  • Publication number: 20080076255
    Abstract: A mask pattern for semiconductor device fabrication comprises a resist pattern formed on a semiconductor substrate, and an interpolymer complex film formed on the resist pattern, wherein the interpolymer complex film includes a network formed by a hydrogen bond between a proton donor polymer and a proton acceptor polymer.
    Type: Application
    Filed: December 3, 2007
    Publication date: March 27, 2008
    Inventors: Mitsuhiro Hata, Jung-Hwan Hah, Hyun-Woo Kim, Sang-Gyun Woo
  • Publication number: 20080064219
    Abstract: A method of removing a photoresist in a semiconductor manufacturing process including at least one of the following steps: sequentially depositing an oxide film and a metal film over a semiconductor substrate. Depositing an anti-reflection film and a photoresist over the metal film. Patterning the photoresist to form a photoresist pattern. Prompting a surface reaction of the semiconductor substrate using a chuck to remove a polymer film formed on the surface of the photoresist pattern. Removing the photoresist pattern by a plasma etching process while spraying a photoresist removal gas containing fluorine to cause a reaction between aluminum and fluorine.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 13, 2008
    Inventor: Chung-Kyung Jung
  • Publication number: 20080057718
    Abstract: A technique for increasing productivity by simplified steps in a manufacturing process of TFTs, electronic circuits using TFTs, and semiconductor devices formed of TFTs is provided. A method for manufacturing a semiconductor device includes forming a light absorbing layer, forming a light-transmitting layer on the light absorbing layer emitting a linear laser beam with a homogenized energy onto a mask and thereby splitting the linear laser beam into a plurality of laser beams and emitting the plurality of laser beams onto the light-transmitting layer on the light absorbing layer, and thereby forming a plurality of openings in the light-transmitting layer and the light absorbing layer.
    Type: Application
    Filed: August 14, 2007
    Publication date: March 6, 2008
    Inventors: Takatsugu Omata, Koichiro Tanaka
  • Publication number: 20080001191
    Abstract: By modifying the dielectric liner for a spacer structure so as to exhibit an enhanced diffusion blocking characteristic, for instance by incorporating nitrogen, the out-diffusion of P-dopants, such as boron, into the dielectric material may be significantly reduced. Consequently, transistor performance, especially of P-type transistors, may be significantly enhanced while nevertheless a high degree of compatibility with conventional techniques may be maintained.
    Type: Application
    Filed: February 13, 2007
    Publication date: January 3, 2008
    Inventors: Ekkehard Pruefer, Ralf Van Bentum, Klaus Hempel, Stephan Kruegel
  • Patent number: 7312127
    Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.
    Type: Grant
    Filed: March 23, 2006
    Date of Patent: December 25, 2007
    Assignee: LSI Corporation
    Inventors: Wai Lo, Verne Hornback, Wilbur G. Catabay, Wei-Jen Hsia, Sey-Shing Sun
  • Publication number: 20070259526
    Abstract: A method for treating a film of material, which can be defined on a substrate, e.g., silicon. The method includes providing a substrate comprising a cleaved surface, which is characterized by a predetermined surface roughness value. The substrate also has a distribution of hydrogen bearing particles defined from the cleaved surface to a region underlying said cleaved surface. The method also includes increasing a temperature of the cleaved surface to greater than about 1,000 Degrees Celsius while maintaining the cleaved surface in an etchant bearing environment to reduce the predetermined surface roughness value by about fifty percent and greater. Preferably, the value can be reduced by about eighty or ninety percent and greater, depending upon the embodiment.
    Type: Application
    Filed: July 11, 2007
    Publication date: November 8, 2007
    Applicant: Silicon Genesis Corporation
    Inventors: Sien Kang, Igor Malik
  • Patent number: 7287328
    Abstract: Methods for injecting charge include providing a target comprising a first layer on a second layer, coupling a conductive base to the second layer, and providing a medium which is in contact with at least a portion of the first layer. An electrode is positioned to face and is spaced from the first layer and is at least partially in contact with the medium. An electric field is provided across the first and second layers to inject charge to an interface between the first layer and the second layer.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: October 30, 2007
    Assignee: Rochester Institute of Technology
    Inventor: Michael D. Potter
  • Patent number: 7244647
    Abstract: An embedded capacitor structure in a circuit board and a method for fabricating the same are proposed. The circuit board is formed with a first circuit layer on at least one surface thereof, wherein the first circuit layer has at least one first electrode plate for the capacitor structure. Then, a dielectric layer is formed on the first circuit layer and made flush with the first circuit layer. The dielectric layer has a relatively low dielectric constant and good fluidity to effectively fill the spaces between patterned traces of the first circuit later. A capacitive material is deposited on the dielectric layer and the first circuit layer. Finally, a second circuit layer is formed on the capacitive material and has at least one second electrode plate corresponding to the first electrode plate, together with the capacitive material disposed in-between, to form the capacitor structure.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: July 17, 2007
    Assignee: Phoenix Precision Technology Corporation
    Inventor: Ruei-Chih Chang
  • Publication number: 20070049003
    Abstract: The invention includes methods of forming layers conformally over undulating surface topographies associated with semiconductor substrates. The undulating surface topographies can first be exposed to one or more of titanium oxide, neodymium oxide, yttrium oxide, zirconium oxide and vanadium oxide to treat the surfaces, and can be subsequently exposed to a material that forms a layer conformally along the treated surfaces. The material can, for example, comprise one or both of aluminum silane and aluminum silazane. The invention also includes semiconductor constructions having conformal layers formed over liners containing one or more of titanium oxide, yttrium oxide, zirconium oxide and vanadium oxide.
    Type: Application
    Filed: September 1, 2005
    Publication date: March 1, 2007
    Inventor: John Smythe