Abstract: An organic field-effect transistor and a fabrication method therefor, including: providing a gate; depositing polymer material onto the gate to form a dielectric layer; performing supercritical fluids treatment on the gate having the dielectric layer deposited; depositing organic semiconductor layer material on the dielectric layer having been processed, to form an organic semiconductor layer; depositing electrode layer material on the organic semiconductor layer and forming an electrode layer. The dielectric properties of the dielectric layer after adopting the supercritical fluids treatment have been significantly improved. While the hysteresis effect of the dielectric layers in the OFET devices has been basically eliminated, the sub-threshold slope of the OFET is also significantly reduced, the carrier mobility is effectively improved. Additionally, an OFET switching rate after being processed is improved, and, by connecting the LEDs in series, the switching rate of the LED is increased.

Abstract: A substrate processing method for removing an organic film on a substrate includes a) carrying out introduction of ozone-containing gas into a substrate processing chamber to fill at least a space above the substrate in the substrate processing chamber with ozone-containing gas, b) starting spraying through the space a heated chemical liquid containing sulfuric acid onto the substrate after the a), c) continuing the spraying started in the b), and d) stopping the spraying continued in the c).

Abstract: A cleaning agent composition for use in removal of a polysiloxane adhesive remaining on a substrate, the composition containing a tetrahydrocarbylammonium fluoride and an organic solvent, wherein the organic solvent contains an alkylene glycol dialkyl ether and a lactam compound represented by formula (1). (in formula (1), R101 represents a C1 to C6 alkyl group, and R102 represents a C1 to C6 alkylene group.

Abstract: Various embodiments include a display panel with an integrated micro-lens array. The display panel typically includes an array of mesas which includes an array of pixel light sources (e.g., LEDs) electrically coupled to corresponding pixel driver circuits (e.g., FETs). The array of micro-lenses is aligned to the mesas including the pixel light sources, and positioned to reduce the divergence of light produced by the pixel light sources. In some embodiments, the array of micro-lenses formed from a micro-lens material layer is formed directly on top of the mesas. The display panel may also include an integrated optical spacer formed from the same micro-lens material layer to maintain the positioning between the micro-lenses and pixel driver circuits.

Abstract: A semiconductor device includes a first dielectric layer over a device base layer, the first dielectric layer having a first opening with a first sidewall; a first interconnect segment extending through the first opening; and a cap layer over a top surface of the first interconnect segment, wherein the cap layer comprises a first metal, carbon, and nitrogen.

Abstract: A PCB for wireless power transfer includes an antenna and the antenna includes a coil. A method for manufacturing the PCB includes providing a prefabricated PCB, the prefabricated PCB including a PCB design and a first area and providing a first sheet of a conductive metal for the first area. The method includes applying an etch resistant coating on a coil area within the first area and laser cutting the first sheet within the coil area, based on a laser cutting path for a first plurality of turns for a first layer of the coil, the first geometry configured wireless power transfer. The method further includes substantially exposing the first sheet to an etching solution, the etching solution substantially removing first portions of the conductive metal from the substrate to define, at least, first turn gaps between at least two of the first plurality of turns.

Abstract: A PCB for wireless power transfer includes an antenna and the antenna includes a coil. A method for manufacturing the PCB includes providing a prefabricated PCB, the prefabricated PCB including a PCB design and a first area and providing a first sheet of a conductive metal for the first area. The method includes applying an etch resistant coating on a coil area within the first area and laser cutting the first sheet within the coil area, based on a laser cutting path for a first plurality of turns for a first layer of the coil, the first geometry configured wireless power transfer. The method further includes substantially exposing the first sheet to an etching solution, the etching solution substantially removing first portions of the conductive metal from the substrate to define, at least, first turn gaps between at least two of the first plurality of turns.

Abstract: This disclosure relates to a cleaning composition that contains 1) at least one redox agent; 2) at least one first chelating agent, the first chelating agent being a polyaminopolycarboxylic acid; 3) at least one metal corrosion inhibitor, the metal corrosion inhibitor being a substituted or unsubstituted benzotriazole; 4) at least one pH adjusting agent, the pH adjusting agent being a base free of a metal ion; and 5) water. This disclosure also relates to a method of using the above composition for cleaning a semiconductor substrate.

Abstract: This disclosure relates to a cleaning composition that contains 1) at least one redox agent; 2) at least one first chelating agent, the first chelating agent being a polyaminopolycarboxylic acid; 3) at least one metal corrosion inhibitor, the metal corrosion inhibitor being a substituted or unsubstituted benzotriazole; 4) at least one pH adjusting agent, the pH adjusting agent being a base free of a metal ion; and 5) water. This disclosure also relates to a method of using the above composition for cleaning a semiconductor substrate.

Abstract: Disclosed are an apparatus and a method for cleaning a component of a substrate dry processing apparatus. The method for cleaning a component of a substrate dry processing apparatus includes dipping the component in a cleaning solution received in a cleaning bath, generating radicals from the cleaning solution, and cleaning the component with the radicals. The component is cleaned with hydrogen radicals (H2*) and hydroxyl radicals (OH*) generated from ozone water. Accordingly, it is possible to rapidly remove carbon (C) and fluorine (F) deposited on the component.

Abstract: Methods for performing a photolithographic process are disclosed. The methods facilitate the removal of photosensitive from a wafer after the photosensitive has been used as an etch mask. The photosensitive may be a negative tone photosensitive that undergoes a cross-linking process on exposure to electromagnetic energy. By limiting the cross-linking through a reduced post-exposure bake temperature and/or through reduced cross-linker loading, the photoresist, or at least a portion thereof, may have a reduced solvent strip resistance. Because of the reduced solvent strip resistance, a portion of the photosensitive may be removed using a solvent strip. After the solvent strip, a dry etch may be performed to remove remaining portions of the photoresist.

Abstract: A semiconductor device is provided that includes a gate structure present on a substrate. The gate structure includes a gate conductor with an undercut region in sidewalls of a first portion of the gate conductor, wherein a second portion of the gate conductor is present over the first portion of the gate conductor and includes a protruding portion over the undercut region. A spacer is adjacent to sidewalls of the gate structure, wherein the spacer includes an extending portion filling the undercut region. A raised source region and a raised drain region is present adjacent to the spacers. The raised source region and the raised drain region are separated from the gate conductor by the extending portion of the spacers.

Abstract: A high-k metal gate stack and structures for CMOS devices and a method for forming the devices. The gate stack includes a germanium (Ge) material layer formed on the semiconductor substrate, a diffusion barrier layer formed on the Ge material layer, a high-k dielectric having a high dielectric constant greater than approximately 3.9 formed over the diffusion barrier layer, and a conductive electrode layer formed above the high-k dielectric layer.

Abstract: A method for forming an electronic device having a semiconducting active layer comprising a polymer, the method comprising aligning the chains of the polymer parallel to each other by bringing the polymer into a liquid-crystalline phase.

Abstract: A method of manufacturing an organic electroluminescent device includes a step of forming a masking layer and an intermediate layer on a first organic compound layer such that the masking layer and the intermediate layer have a predetermined pattern, a step of patterning the first organic compound layer using the masking layer and the intermediate layer, a step of forming a second organic compound layer, and a step of removing the intermediate layer and the second organic compound layer formed thereon in such a manner that the intermediate layer is contacted with a dissolving liquid for dissolving the intermediate layer. In the method, the first and second organic compound layers are protected by covering the first and second organic compound layers with a sacrificial layer until the patterning of the first and second organic compound layers is completed.

Abstract: A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.

Abstract: A method for forming small dimension openings in the organic masking layer of tri-layer lithography. The method includes forming an organic polymer layer over a semiconductor substrate; forming a silicon containing antireflective coating on the organic polymer layer; forming a patterned photoresist layer on the antireflective coating, the patterned photoresist layer having an opening therein; performing a first reactive ion etch to transfer the pattern of the opening into the antireflective coating to form a trench in the antireflective coating, the organic polymer layer exposed in a bottom of the trench; and performing a second reactive ion etch to extend the trench into the organic polymer layer, the second reactive ion etch forming a polymer layer on sidewalls of the trench, the second reactive ion etch containing a species derived from a gaseous hydrocarbon.

Abstract: A biphenyl derivative having formula (1) is provided wherein Ar1 and Ar2 denote a benzene or naphthalene ring, and x and z each are 0 or 1. A material comprising the biphenyl derivative or a polymer comprising recurring units of the biphenyl derivative is spin coated and heat treated to form a resist bottom layer having improved properties, optimum values of n and k, step coverage, etch resistance, heat resistance, solvent resistance, and minimized outgassing.

Abstract: The invention relates to an edge bead remover composition for an organic film disposed on a substrate surface, comprising an organic solvent and at least one polymer having a contact angle with water greater than 70°. The invention also relates to a process for using the composition as an edge bead remover for an organic film.

Abstract: A first oxide film and a second oxide film 16 are formed in a first region 13a and a second region 13b, respectively, on the surface of the semiconductor substrate 10, via thermal oxidization method, and the first oxide film is removed while the second oxide film 16 is covered with the resist layer 18 formed thereon, and then the resist layer 18 is removed with a chemical solution containing an organic solvent such as isopropyl alcohol as a main component. Subsequently, a third oxide film 22 having different thickness than the second oxide film 16 is formed in the first region 13a.

Abstract: A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.

Abstract: Provided are an electronic device including a bank structure and a method of manufacturing the same. The method of manufacturing the electronic device requires a fewer number of processes and comprises a direct patterning of insulating layers, such as fluorinated organic polymer layers, is possible using cost-efficient techniques such as inkjet printing.

Abstract: A photoresist trimming gas compound is provided which will selectively remove a resist foot or scum from the lower portions of sidewalls of a photoresist. Additionally, the trimmer compound hardens or toughens an upper surface of the photoresist thereby strengthening the photoresist. The trimmer compound includes O2 and at least one other gaseous oxide and is typically utilized in a dry etching process after a trench has been formed in a photoresist. The other oxide gases, in addition to the O2 may include CO2, SO2 and NO2.

Abstract: A method is described for use in a system that removes an implant crust that is formed as an outermost layer of photoresist in a photoresist pattern that is supported by a workpiece. The photoresist pattern defines apertures which lead to an active device region. The active device region is formed by an ion implantation which produces the implant crust. A filler material is applied such that the filler material reaches a fill depth in each aperture. The workpiece and the filler material are exposed to a treatment environment to remove the implant crust on the laterally extending surface of the photoresist as the filler material protects the active device region. Thereafter, a remaining portion of the photoresist layer is removed. An associated intermediate assembly, including the workpiece, is described.

Abstract: A non-volatile ferroelectric memory device is proposed which comprises a combination of an organic ferroelectric polymer with an organic ambipolar semiconductor. The devices of the present invention are compatible with—and fully exploit the benefits of polymers, i.e. solution processing, low-cost, low temperature layer deposition and compatibility with flexible substrates.

Abstract: A method is provided of making a gated semiconductor device. Such method can include patterning a single-crystal semiconductor region of a substrate to extend in a lateral direction parallel to a major surface of a substrate and to extend in a direction at least substantially vertical and at least substantially perpendicular to the major surface, the semiconductor region having a first side and a second side opposite, e.g., remote from the first side. A first gate may be formed overlying the first side, the first gate having a first gate length in the lateral direction. A second gate may be formed overlying the second side, the second gate having a second gate length in the lateral direction which is different from the first gate length. In one embodiment, the second gate length may be shorter than the first gate length. In one embodiment, the first gate may consist essentially of polycrystalline silicon germanium and the second gate may consist essentially of polysilicon.

Abstract: A method for manufacturing a semiconductor device including a first conductive type impurity region formed by introducing a first conductive type impurities in a first region of a semiconductor region and heating the first region, a second conductive type impurity region formed by introducing a second conductive type impurities in a second region of the semiconductor region and heating the second region, the method including covering the second region with a mask and then introducing the first conductive type impurities in a surface of the first region, removing the mask by a process using gas including oxygen while forming an oxide film on the surface of the first region by the processing using the gas including the oxygen, and introducing the second conductive type impurities in a surface of the second region by using the oxide film as a mask.

Abstract: A method of fabricating a semiconductor device. The method comprises subjecting a substrate having formed thereon photoresist layer to a plasma hydrogen, the substrate further having formed thereon a sacrificial layer; contacting the photoresist layer with a photoresist removal solution; subjecting the sacrificial layer to a plasma hydrogen; and contacting the sacrificial material layer with an etchant solution.

Abstract: A method of forming a dual damascene semiconductor interconnection and an etchant composition specially adapted for stripping a sacrificial layer in a dual damascene fabrication process without profile damage to a dual damascene pattern are provided. The method includes sequentially forming a first etch stop layer, a first intermetal dielectric, a second intermetal dielectric, and a capping layer on a surface of a semiconductor substrate on which a lower metal wiring is formed; etching the first intermetal dielectric, the second intermetal dielectric, and the capping layer to form a via; forming a sacrificial layer within the via; etching the sacrificial layer, the second intermetal dielectric, and the capping layer to form a trench; removing the sacrificial layer remaining around the via using an etchant composition including NH4F, HF, H2O and a surfactant; and forming an upper metal wiring within the thus formed dual damascene pattern including the via and the trench.

Abstract: A method for forming an integrated circuit including at least two interconnected electronic switching devices, the method comprising forming at least part of the electronic switching devices by ink-jet printing.

Abstract: A method of fabricating a semiconductor device. The method comprises subjecting a substrate having formed thereon photoresist layer to a plasma hydrogen, the substrate further having formed thereon a sacrificial layer; contacting the photoresist layer with a photoresist removal solution; subjecting the sacrificial layer to a plasma hydrogen; and contacting the sacrificial material layer with an etchant solution.

Abstract: Simple but practical methods to dice a CMOS-MEMS multi-project wafer are proposed. On this wafer, micromachined microstructures have been fabricated and released. In a method, a photoresist is spun on the full wafer surface, and this photoresist is thick enough to cover all cavities and structures on the wafer, such that the photoresist will protect the released structures free from the chipping, vibrations, and damages in the diamond blade dicing process. In another method, a laser dicing system is utilized to scribe the multi-project wafer placed on a platform, and by precisely controlling the platform moving-track, the dicing path can be programmed to any required shape and region, even it is not straight. In addition, the wafer backside is mounted on a blue-tape at the beginning to enhance the process reliability.

Abstract: An integrated circuit including an array of memory cells having dual gate transistors with curved current flow, and method for operation and fabrication is disclosed. In one embodiment, in a substrate an array of transistors is formed for selecting one of a plurality of memory cells by selecting a pair of adjacent word lines and a bit line. For minimizing the area of a memory cell and reducing complexity in production an array of dual gate transistors having a curved current flow is disclosed, wherein a small portion of a current is allowed to flow through adjacent memory cells.

Abstract: A fabricating method for a flat panel display device having a thin film pattern over a substrate is disclosed. The fabricating method includes depositing a hydrophilic resin over a substrate and patterning the hydrophilic resin to form hydrophilic resin patterns over areas outside where thin film patterns are to be formed over the substrate. The fabricating method also includes depositing a hydrophobic nano powder thin film material over the substrate and between the hydrophilic resin patterns and removing the hydrophilic resin patterns to form hydrophobic nano powder thin film patterns over the substrate. Moreover, the fabricating method includes treating the hydrophobic nano powder thin film patterns to form the thin film pattern.

Abstract: In a method of manufacturing a semiconductor device, a flexible tube connects at least part of a path extending from a reaction chamber to a detoxification device through a vacuum pump. The flexible tube has a tube body made of hard material, the tube body having projected parts and depressed parts and a cover provided over an outer surface of the tube body, the cover being made of elastic material, the cover being in contact with around the projected parts of the tube body and formed over the depressed parts of the tube body so that a vacant space is formed between the tube body and the cover. Then, a semiconductor substrate is disposed within the reaction chamber. The vacuum pump is activated to bring the reaction chamber into a pressure-reduced state. A reaction gas is supplied to the reaction chamber. Finally, the reaction gas causes to react to thereby deposit a reactant on the semiconductor substrate.

Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in (216) a fixed position relative to the layer of the first material. The method also forms at least one void (220) through the layer of the first material in response to the photoresist layer. Further, the method subjects (106) the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen so as to remove the photoresist layer.

Abstract: A passivation layer pattern having an opening is formed on a substrate having a metal wiring pattern formed thereon. The opening partially exposes an upper surface of the metal wiring pattern. A photoresist pattern is formed on the passivation layer pattern. The photoresist pattern has an opening that exposes the opening of the passivation layer pattern, and metal is electroplated in the openings to form a bump electrode. The photoresist pattern is removed using a composition including monoethanolamine and dimethylacetamide.

Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in (216) a fixed position relative to the layer of the first material. The method also forms at least one void (220) through the layer of the first material in response to the photoresist layer. Further, the method subjects (106) the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen so as to remove the photoresist layer.

Abstract: The present invention discloses a multi-passivation layer structure for organic thin-film transistors and a method for fabricating the same by spin coating, inject printing, screen printing and micro-contact on organic thin-film transistors. The multi-passivation layer structure for organic thin-film transistors, comprising: a substrate; a gate layer formed on the substrate; an insulator layer formed on the substrate and the gate layer; an electrode layer formed on the insulator layer; a semiconductor layer formed on the insulator layer and the electrode layer; and a passivation layer formed on the semiconductor layer and the electrode layer, thereby forming a multi-passivation layer structure for organic thin-film transistors.

Abstract: A method of patterning organic semiconductor layers of electronic devices utilizing reverse printing.