Layer Comprising Silazane Compounds (epo) Patents (Class 257/E21.263)
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Patent number: 10475739Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.Type: GrantFiled: December 13, 2017Date of Patent: November 12, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Kyung You, Eui Bok Lee, Jong Min Baek, Su Hyun Bark, Jang Ho Lee, Sang Hoon Ahn, Hyeok Sang Oh
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Publication number: 20120156893Abstract: The present invention provides a method for forming a siliceous film. According to the method, a siliceous film having a hydrophilic surface can be formed from a polysilazane compound at a low temperature. In the method, a composition containing a polysilazane compound and a silica-conversion reaction accelerator is applied on a substrate surface to form a polysilazane film, and then a polysilazane film-treatment solution is applied thereon so that the polysilazane compound can be converted into a siliceous film at 300° C. or less. The polysilazane film-treatment solution contains a solvent, hydrogen peroxide and an alcohol.Type: ApplicationFiled: September 2, 2010Publication date: June 21, 2012Inventors: Yuki Ozaki, Masanobu Hayashi
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Patent number: 7902642Abstract: A resin composition for sealing a light-emitting device of the present invention includes a silsesquioxane resin including two or more oxetanyl groups, an aliphatic hydrocarbon including one or more epoxy groups and a cationic polymerization initiator. Furthermore, a lamp of the present invention includes a package equipped with a cup-shaped sealing member, an electrode exposed in the bottom portion of the sealing member, and a light-emitting device arranged on the bottom portion and electrically connected with the electrode, wherein the light-emitting device is sealed with the above-described resin composition for sealing a light-emitting device filled in the sealing member.Type: GrantFiled: December 27, 2007Date of Patent: March 8, 2011Assignee: Showa Denko K.K.Inventors: Tomoyuki Takei, Yuko Sakata
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Patent number: 7803721Abstract: A semiconductor device includes a deposited-type insulating film disposed on a substrate; a coating-type insulating film disposed on a surface of the deposited-type insulating film and having a film density which is lower than a film density of the deposited-type insulating film; and an intermediate insulating film disposed between the deposited-type insulating film and the coating-type insulating film and having a film density which is intermediate between the film density of the deposited-type insulating film and the film density of the coating-type insulating film.Type: GrantFiled: March 14, 2007Date of Patent: September 28, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Kazuaki Iwasawa
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Publication number: 20100105189Abstract: A method of fabricating a semiconductor device includes applying a coating oxide film to a surface of a substrate including a semiconductor substrate so that a recess formed in the surface is filled with the coating oxide film, applying a steam oxidation treatment to the substrate at a first temperature, soaking the substrate in heated water while applying a megasonic wave to the substrate in the heated water, and applying a steam oxidation treatment to the substrate at a second temperature higher than the first temperature.Type: ApplicationFiled: December 29, 2009Publication date: April 29, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Hiroshi KAWAMOTO, Naoki Kai, Koichi Matsuno, Minori Kajimoto
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Patent number: 7651924Abstract: A method of fabricating a semiconductor device includes applying a coating oxide film to a surface of a substrate including a semiconductor substrate so that a recess formed in the surface is filled with the coating oxide film, applying a steam oxidation treatment to the substrate at a first temperature, soaking the substrate in heated water while applying a megasonic wave to the substrate in the heated water, and applying a steam oxidation treatment to the substrate at a second temperature higher than the first temperature.Type: GrantFiled: September 18, 2008Date of Patent: January 26, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Kawamoto, Naoki Kai, Koichi Matsuno, Minori Kajimoto
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Patent number: 7582555Abstract: The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.Type: GrantFiled: December 29, 2005Date of Patent: September 1, 2009Assignee: Novellus Systems, Inc.Inventors: Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
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Patent number: 7501355Abstract: Methods for forming silicon nitride hard masks are provided. The silicon nitride hard masks include carbon-doped silicon nitride layers and undoped silicon nitride layers. Carbon-doped silicon nitride layers that are deposited from a mixture comprising a carbon source compound, a silicon source compound, and a nitrogen source in the presence of RF power are provided. Also provided are methods of UV post-treating silicon nitride layers to provide silicon nitride hard masks. The carbon-doped silicon nitride layers and UV post-treated silicon nitride layers have desirable wet etch rates and dry etch rates for hard mask layers.Type: GrantFiled: June 29, 2006Date of Patent: March 10, 2009Assignee: Applied Materials, Inc.Inventors: Ritwik Bhatia, Li-Qun Xia, Chad Peterson, Hichem M'Saad
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Patent number: 7329591Abstract: A method for forming a silicon-containing film is described. A substrate is placed in a reaction chamber, and then a silicon-containing gas is introduced into the reaction chamber to conduct a CVD process and deposit a silicon-containing film on the substrate. During the CVD process, the temperature of at least the top inner surface of the reaction chamber is controlled below 50° C.Type: GrantFiled: February 21, 2006Date of Patent: February 12, 2008Assignee: United Microelectronics Corp.Inventors: Che-Hung Liu, Po-Lun Cheng, Hwei-Lin Chuang, Chun-An Lin
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Patent number: 7323378Abstract: This invention provides a CMOS image sensor having a pinned photodiode. A P substrate is provided having thereon a P well. The P well is adjacent to a light-sensing region of the CMOS image sensor. A gate electrode of a transfer transistor of the CMOS image sensor is formed on the P well. A self-aligned implantation is performed to form N-type diode diffusion within the light-sensing region. An oblique ion implantation process is then performed to form N-type pocket diffusion directly under the gate electrode. Spacers are formed on sidewalls of the gate electrode. A surface P+ pinning diffusion region is then formed in the diode diffusion region.Type: GrantFiled: October 20, 2005Date of Patent: January 29, 2008Assignee: PixArt Imaging Inc.Inventors: Ching-Wei Chen, Chih-Cheng Hsieh, Chien-Chang Huang
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Publication number: 20070281498Abstract: A spin-on glass (SOG) composition and a method of forming a silicon oxide layer utilizing the SOG composition are disclosed. The method includes coating on a semiconductor substrate having a surface discontinuity, an SOG composition containing polysilazane having a compound of the formula —(SiH2NH)n— wherein n represents a positive integer, a weight average molecular weight within the range of about 3,300 to 3,700 to form a planar SOG layer. The SOG layer is converted to a silicon oxide layer with a planar surface by curing the SOG layer. Also disclosed is a semiconductor device made by the method.Type: ApplicationFiled: August 9, 2007Publication date: December 6, 2007Inventors: Jung-Ho Lee, Jun-Hyun Cho, Jung-Sik Choi, Dong-Jun Lee
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Publication number: 20070262449Abstract: The present invention concerns a methods and compositions for preparing a multi layer composite device, such as a semiconductor device. Said method comprises (A) forming a dielectric layer on the surface of a composite material by bringing said surface into contact: a) either with a solution, comprising the diazonium salt of aniline, a diazonium salt bearing at least one functional group or an amine compound of formula H2N-A-X-Z as defined in claim 1: b) or with a first solution containing an aryl diazonium salt and successively a second solution containing a compound bearing at least one functional group and bearing at least one functional group capable of reacting with the aryl radical grafted on the surface of the composite material thanks to the aryl diazonium salt; (B) forming an overlayer on said surface of said composite material obtained in step (A), said overlayer consisting of a Si-containing dielectric Cu-Etch Stop Layer and/or copper diffusion barrier.Type: ApplicationFiled: March 5, 2007Publication date: November 15, 2007Applicant: ALCHIMERInventors: Isabelle Bispo, Nathalie Thieriet, Paolo Mangiagalli
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Patent number: 7256146Abstract: The present invention comprises an interconnect structure including a metal, interlayer dielectric and a ceramic diffusion barrier formed therebetween, where the ceramic diffusion barrier has a composition SivNwCxOyHz, where 0.1?v?0.9, 0?w?0.5, 0.01?x?0.9, 0?y?0.7, 0.01?z?0.8 for v+w+x+y+z=1. The ceramic diffusion barrier acts as a diffusion barrier to metals, i.e., copper. The present invention also comprises a method for forming the inventive ceramic diffusion barrier including the steps depositing a polymeric preceramic having a composition SivNwCxOyHz, where 0.1<v<0.8, 0<w<0.8, 0.05<x<0.8, 0<y<0.3, 0.05<z<0.8 for v+w+x+y+z=1 and then converting the polymeric preceramic layer into a ceramic diffusion barrier by thermal methods.Type: GrantFiled: May 13, 2005Date of Patent: August 14, 2007Assignee: International Business Machines CorporationInventors: Stephan A. Cohen, Stephen McConnell Gates, Jeffrey C. Hedrick, Elbert E. Huang, Dirk Pfeiffer
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Patent number: 7186604Abstract: After forming a silicon oxide film 9 on the surface of a region A of a semiconductor substrate 1, a high dielectric constant insulating film 10, a silicon film, a silicon oxide film 14 are successively deposited over the semiconductor substrate 1, and they are patterned to leave the silicon oxide film 14 in regions for forming gate electrodes. Then, after fabricating silicon films 13n and 13p by using the patterned silicon oxide film 14 as a mask, when removing the silicon oxide film 14, etching is performed under the condition where the etching selectivity of the silicon oxide film 14 to the high dielectric constant insulating film 10 becomes large, thereby leaving the high dielectric constant insulating film 10 also to portions below the end of the gate electrodes (13n, 13p). Thus, it is possible to ensure the voltage withstanding thereof and improve the characteristics of MISFET.Type: GrantFiled: August 15, 2002Date of Patent: March 6, 2007Assignee: Renesas Technology Corp.Inventors: Satoshi Sakai, Satoshi Yamamoto, Atsushi Hiraiwa, Ryoichi Furukawa