Deposition Of Porous Oxide Or Porous Glassy Oxide Or Oxide Based Porous Glass (epo) Patents (Class 257/E21.273)
  • Patent number: 11798824
    Abstract: The present invention is related to a heating device for heating an object material using a laser beam, the heating device comprising a stage on which the object material is placed; a laser module for generating and outputting a laser beam; an optical module for controlling a path of the laser beam; a polygon mirror rotating around an axis of rotation and having a plurality of reflecting surfaces which reflect the laser beam; and a beam guide module for controlling an incidence range within which the laser beam reflected by the polygon mirror is incident on the object material, and an indirect heating method using a laser beam in a heating device.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: October 24, 2023
    Assignee: RNR LAB INC
    Inventor: Jeong Do Ryu
  • Patent number: 11555689
    Abstract: Methods and systems disclosed herein can measure thin film stacks, such as film on grating and bandgap on grating in semiconductors. For example, the thin film stack may be a 1D film stack, a 2D film on grating, or a 3D film on grating. One or more effective medium dispersion models are created for the film stack. Each effective medium dispersion model can substitute for one or more layers. A thickness of one or more layers can be determined using the effective medium dispersion based scatterometry model. In an instance, three effective medium dispersion based scatterometry models are developed and used to determine thickness of three layers in a film stack.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: January 17, 2023
    Assignee: KLA-Tencor Corporation
    Inventors: Houssam Chouaib, Zhengquan Tan
  • Patent number: 10770344
    Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 8, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yuping Ren, Haigou Huang, Ravi Prakash Srivastava, Zhiguo Sun, Qiang Fang, Cheng Xu, Guoxiang Ning
  • Patent number: 10597495
    Abstract: An aged polymeric silsesquioxane comprising a product of heating a cured polymeric silsesquioxane of formula (I) (see specification) at a temperature of from 460° to 700° C., a formulation comprising the aged polymeric silsesquioxane and at least one additional constituent, methods of making and using the aged polymeric silsesquioxane, and manufactured articles and devices containing the aged polymeric silsesquioxane.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: March 24, 2020
    Assignee: Dow Silicones Corporation
    Inventors: Peng-Fei Fu, Byung K. Hwang
  • Patent number: 10438892
    Abstract: A semiconductor device according to present embodiment has first wirings provided in a first area and made of a first metal. A first gap is provided between the first wirings adjacent to each other. Second wirings or contact plugs are provided in a second area in which the first wirings are not provided. The second wirings or contact plugs are made of a second metal. A first insulation film is provided between the second wirings or contact plugs adjacent to each other. The first insulation film has second gaps. A second insulation film is provided on the first wirings, the first gap, and the second gaps.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: October 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshiyuki Morita
  • Patent number: 10163691
    Abstract: A method of fabricating a semiconductor device includes forming a low-k dielectric layer over a substrate and depositing a cap layer over the low-k dielectric layer. A treatment process is performed to the cap layer. After the treatment process to the cap layer is performed, the low-k dielectric layer is etched to form a plurality of trenches using the cap layer as an etching mask.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Cheng Shih, Chia Cheng Chou, Chung-Chi Ko
  • Patent number: 10134634
    Abstract: An embodiment of a method for metal-assisted chemical etching of a semiconductive substrate comprises forming a patterned coating on a top surface of a substrate layer of a silicon wafer; applying a noble metal layer over the patterned coating such that a portion of the noble metal layer is in contact with the top surface of the substrate layer; and immersing the silicon wafer in a wet etching solution to form a trench under the portion of the noble metal layer that is contact with the top surface of the substrate layer. Further, the trench may be filled with copper material to form a through silicon via structure. Such embodiments provide etching techniques that enable etched formations that are deep (e.g., high-aspect-ratio) and uniform as opposed to shallow etchings (i.e., low-aspect-ratio) or non-uniform deep etchings.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: November 20, 2018
    Assignee: GEORGIA TECH RESEARCH CORPORATION
    Inventors: Liyi Li, Ching Ping Wong, Jack K. Moon, Xueying Zhao
  • Patent number: 10115971
    Abstract: The invention concerns a method for manufacturing of an electrocatalyst comprising a porous carbon support material, a catalytic material in the form of at least one type of metal, and macrocyclic compounds chemically bound to the carbon support and capable of forming complexes with single metal ions of said metal or metals, said method comprising the steps of: i) providing a template capable of acting as pore structure directing agent during formation of a highly porous electrically conducting templated carbon substrate, ii) mixing the template with one or several precursor substances of the catalytic material, the macrocyclic compounds and carbon, iii) exposing the mixture of the template and the precursor substances to a carbonization process during which the precursors react and transform the mixture into a carbonized template composite in which the carbon part of the composite is chemically bound to macrocyclic compounds present in complexes with the metal or metals.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: October 30, 2018
    Assignee: APPEM Ltd.
    Inventors: Anders Palmqvist, Kjell Fossum
  • Patent number: 10010864
    Abstract: The present invention relates to the process of obtaining adsorbent materials based upon supported metal species on porous silicates, and their use for reducing the amount of sulfur and nitrogen contaminants in petroleum fractions and products derived of, i.e., light and heavy gas oils, FCC gasoline and fuels, where FCC stands for Fluid Catalytic Cracking process. Therefore, the invention comprises the selection, preparation, modification and adsorptive properties of the abovementioned porous materials, which are based on porous silicates with metal species intercalated and/or impregnated, such as Ti(O,OH), Mg(O,OH)—, Zr(O,OH)—, Fe(O,OH), Al(O,OH). Also, additional options were considered, for example those comprising metals from the 1st and 2nd transition series, such as Cu+, Ni2+, Zn2+, Fe2+, Ag+, Co2+, Ti4+, V2+,5+, Cr3+ and Mn2+.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: July 3, 2018
    Assignee: Instituto Mexicano Del Petroleo
    Inventors: Patricia Flores Sanchez, Jose Manuel Dominguez Esquivel, Jorge Arturo Aburto Anell
  • Patent number: 9994481
    Abstract: Certain example embodiments relate to a coated article including a coating formed from a sol that has hydrophobic surface properties. The sol may include a mixture of at least two alkylsiloxane chemicals, with the sol potentially being aged for a certain comparatively short amount of time before being wet-applied to a major substrate surface. The application process may also undergo a certain comparatively short curing process to help provide hydrophobic surface properties. The hydrophobic surface properties help provide anti-soiling functions that are advantageous in a variety of applications including, for example, solar mirror applications.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: June 12, 2018
    Assignee: Guardian Glass, LLC
    Inventor: Liang Liang
  • Patent number: 9935002
    Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Sean King, Hui Jae Yoo, Sreenivas Kosaraju, Timothy Glassman
  • Patent number: 9831307
    Abstract: The present disclosure relates to an integrated chip having gate electrodes separated from an epitaxial source/drain region by gaps filled with a flowable dielectric material. In some embodiments, the integrated chip has an epitaxial source/drain region protruding outward from a substrate. A first gate structure, having a conductive gate electrode, is separated from the epitaxial source/drain region by a gap. A flowable dielectric material is disposed within the gap, and a pre-metal dielectric (PMD) layer is arranged above the flowable dielectric material. The PMD layer continuously extends between a sidewall of the first gate structure and a sidewall of a second gate structure, and has an upper surface that is substantially aligned with an upper surface of the conductive gate electrode. A metal contact is electrically coupled to the conductive gate electrode and is disposed within an inter-level dielectric layer over the PMD layer and the first gate structure.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Chang Chen, Po-Hsiung Leu, Ding-I Liu
  • Patent number: 9768061
    Abstract: A method of fabricating a semiconductor device includes forming a low-k dielectric layer over a substrate and depositing a cap layer over the low-k dielectric layer. A treatment process is performed to the cap layer. After the treatment process to the cap layer is performed, the low-k dielectric layer is etched to form a plurality of trenches using the cap layer as an etching mask.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Cheng Shih, Chia Cheng Chou, Chung-Chi Ko
  • Patent number: 9754821
    Abstract: Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a dielectric layer, such as a metal oxide, which can be deposited by atomic layer deposition (ALD) techniques with a conformality and density greater than can be achieved in a conventional silicon dioxide-based film deposited by a PECVD process for a thinner contiguous hermetic diffusion barrier. In further embodiments, the diffusion barrier is a multi-layered film including a high-k dielectric layer and a low-k or intermediate-k dielectric layer (e.g., a bi-layer) to reduce the dielectric constant of the diffusion barrier. In other embodiments a silicate of a high-k dielectric layer (e.g., a metal silicate) is formed to lower the k-value of the diffusion barrier by adjusting the silicon content of the silicate while maintaining high film conformality and density.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: September 5, 2017
    Assignee: Intel Corporation
    Inventors: Sean King, Hui Jae Yoo, Sreenivas Kosaraju, Timothy Glassman
  • Patent number: 9666478
    Abstract: In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern filling the opening is formed on the pore sealing layer.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: May 30, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Thomas Oszinda, Tae-Jin Yim, Sang-Hoon Ahn, Nae-In Lee
  • Patent number: 9653400
    Abstract: A semiconductor device is provided. The semiconductor device includes a first porous interlayer insulating film having a low dielectric constant and including a first region and a second region, a second interlayer insulating film formed on the first interlayer insulating film in the first region, a plurality of first conductive patterns formed in the second interlayer insulating film such that the plurality of first conductive patterns are spaced apart from each other, at least one second conductive pattern formed in the first interlayer insulating film in the second region and air gaps disposed at lateral sides of the plurality of first conductive patterns.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: May 16, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-Jin Yim, Woo-Kyung You, Jong-Min Baek, Sang-Hoon Ahn, Thomas Oszinda, Kee-Young Jun
  • Patent number: 9514929
    Abstract: A method includes applying a filling material to a surface of a first layer overlying a substrate. The first layer includes a dielectric material with a plurality of pores. The filling material includes a polymer and an ionic compound. The method includes heating the structure to enable the filling material to at least partially fill the plurality of pores throughout the first layer, and removing the residual filling material from the surface of the first layer, while leaving substantially all of the polymer in the pores of the first layer.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: December 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: Geraud J. Dubois, Krystelle Lionti, Willi Volksen
  • Patent number: 9460964
    Abstract: A method for fabricating a semiconductor device includes forming a buried gate electrode in a semiconductor substrate. An insulating layer is formed over the buried gate electrode and is etched to form a contact hole exposing the semiconductor substrate. A sacrificial spacer is formed on sidewalls of the insulating layer defining the contact hole. A polysilicon layer pattern is formed in the contact hole. The sacrificial spacer is removed to form an air gap around the polysilicon layer pattern. A thermal process is performed to remove a seam existing in the polysilicon layer pattern.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: October 4, 2016
    Assignee: SK Hynix Inc.
    Inventor: Hyung-Kyun Kim
  • Patent number: 8951342
    Abstract: A chemical vapor deposition method for producing a porous organosilica glass film comprising: introducing into a vacuum chamber gaseous reagents including at least one precursor selected from the group consisting of an organosilane and an organosiloxane, and a porogen that is distinct from the precursor; applying energy to the gaseous reagents in the vacuum chamber to induce reaction of the gaseous reagents to deposit a preliminary film on the substrate, wherein the preliminary film contains the porogen; and removing from the preliminary film substantially all of the porogen to provide the porous film with pores and a dielectric constant less than 2.6.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: February 10, 2015
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Raymond Nicholas Vrtis, Mark Leonard O'Neill, Jean Louise Vincent, Aaron Scott Lukas, Mary Kathryn Haas
  • Patent number: 8921235
    Abstract: A method of forming and controlling air gaps between adjacent raised features on a substrate includes forming a silicon-containing film in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming carbon-containing material on top of the silicon-containing film and forming a second film over the carbon-containing material using a flowable deposition process. The second film fills an upper region between the adjacent raised features. The method also includes curing the materials at an elevated temperature for a period of time to form the air gaps between the adjacent raised features. The thickness and number layers of films can be used to control the thickness, vertical position and number of air gaps.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kiran V. Thadani, Jingjing Xu, Abhijit Basu Mallick, Joe Griffith Cruz, Nitin K. Ingle, Pravin K. Narwankar
  • Patent number: 8853677
    Abstract: Metal ink compositions, methods of forming such compositions, and methods of forming conductive layers are disclosed. The ink composition includes a bulk metal, a transition metal source, and an organic solvent. The transition metal source may be a transition metal capable of forming a silicide, in an amount providing from 0.01 to 50 at. % of the transition metal relative to the bulk metal. Conductive structures may be made using such ink compositions by forming a silicon-containing layer on a substrate, printing a metal ink composition on the silicon-containing layer, and curing the composition. The metal inks of the present invention have high conductivity and form low resistivity contacts with silicon, and reduce the number of inks and printing steps needed to fabricate integrated circuits.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: October 7, 2014
    Assignee: Thin Film Electronics ASA
    Inventors: Joerg Rockenberger, Yu Chen, Fabio Zürcher, Scott Haubrich
  • Patent number: 8778771
    Abstract: A method of manufacturing a semiconductor device includes steps of providing a substrate including a semiconductor portion, a non-porous semiconductor layer, and a porous semiconductor layer arranged between the semiconductor portion and the non-porous semiconductor layer, forming a porous oxide layer by oxidizing the porous semiconductor layer, forming a bonded substrate by bonding a supporting substrate to a surface, on a side of the non-porous semiconductor layer, of the substrate on which the porous oxide layer is formed, and separating the semiconductor portion from the bonded substrate by utilizing the porous oxide layer.
    Type: Grant
    Filed: June 17, 2011
    Date of Patent: July 15, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuo Kokumai
  • Patent number: 8772182
    Abstract: A semiconductor device manufacture method has the steps of: (a) coating a low dielectric constant low-level insulating film above a semiconductor substrate formed with a plurality of semiconductor elements; (b) processing the low-level insulating film to increase a mechanical strength of the low-level insulating film; (c) coating a low dielectric constant high-level insulating film above the low-level insulating film; and (d) forming a buried wiring including a wiring pattern in the high-level insulating film and a via conductor in the low-level insulating film. The low-level insulating film and high-level insulating film are made from the same material. The process of increasing the mechanical strength includes an ultraviolet ray irradiation process or a hydrogen plasma applying process.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: July 8, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Yoshiyuki Ohkura
  • Patent number: 8736014
    Abstract: A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: May 27, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Jiun Lin, Ching-Yu Lo, Hai-Ching Chen, Tien-I Bao, Chen-Hua Yu
  • Patent number: 8703625
    Abstract: Described herein are methods of forming dielectric films comprising silicon, oxide, and optionally nitrogen, carbon, hydrogen, and boron. Also disclosed herein are the methods to form dielectric films or coatings on an object to be processed, such as, for example, a semiconductor wafer.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: April 22, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Liu Yang, Manchao Xiao, Bing Han, Kirk S. Cuthill, Mark L. O'Neill
  • Patent number: 8628994
    Abstract: A method of making a semiconductor light-emitting device including (A) a light-emitting portion by laminating in sequence a first compound semiconductor layer, an active layer, and a second compound semiconductor layer; (B) a first electrode electrically connected to the first compound semiconductor layer; (C) a transparent conductive material layer on the second compound semiconductor layer; (D) an insulating layer on a transparent conductive material layer; and (E) a second reflective electrode that on the transparent conductive material layer and on the insulating layer in a continuous manner, wherein, that the areas of the active layer, the transparent conductive material layer, the insulating layer, and the second electrode S1, S2, S3, and S4, respectively are related as S1?S2<S3 and S2<S4.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: January 14, 2014
    Assignee: Sony Corporation
    Inventor: Katsuhiro Tomoda
  • Publication number: 20130072031
    Abstract: Methods and apparatus for a low k dielectric layer of porous SiCOH. A method includes placing a semiconductor substrate into a vapor deposition chamber; introducing reactive gases into the vapor deposition chamber to form a dielectric film comprising SiCOH and a decomposable porogen; depositing the dielectric film to have a ratio of Si—CH3 to SiOnetwork bonds of less than or equal to 0.25; and performing a cure for a cure time to remove substantially all of the porogen from the dielectric film. In one embodiment the porogen comprises a cyclic hydrocarbon. The porogen may be UV curable. In embodiments, different lowered Si—CH3 to SiOnetwork ratios for the deposition of the dielectric film are disclosed. An apparatus of a semiconductor device including the low k dielectric layers is disclosed.
    Type: Application
    Filed: September 16, 2011
    Publication date: March 21, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Yun Peng, Keng-Chu Lin, Joung-Wei Liou, Hui-Chun Yang
  • Patent number: 8399365
    Abstract: A dielectric containing a titanium silicon oxide film and a method of fabricating such a dielectric provide a dielectric for use in a variety of electronic devices. Embodiments may include a dielectric containing a titanium silicon oxide film arranged as one or more monolayers. Embodiments may include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium silicon oxide film, and methods for forming such structures.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: March 19, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8293662
    Abstract: A method of manufacturing a semiconductor device includes steps of: generating positively or negatively charged fine bubbles having substantially zero buoyancy in a coating solution as an insulating film forming material; coating the coating solution including the bubbles on a substrate to form a coating film; and baking the coating film by heating the substrate before the bubbles are removed to obtain a porous low dielectric constant insulating film.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: October 23, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Sumie Nagaseki
  • Patent number: 8288771
    Abstract: A thin film transistor array panel is provided, which includes a substrate, a plurality of gate line formed on the substrate, a plurality of common electrodes having a transparent conductive layer on the substrate, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer and the gate insulating layer, a plurality of drain electrodes formed on the semiconductor layer and the gate insulating layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: October 16, 2012
    Assignee: Samsung Electonics Co., Ltd.
    Inventors: Je-Hun Lee, Sung-Jin Kim, Hee-Joon Kim, Chang-Oh Jeong
  • Patent number: 8222659
    Abstract: A semiconductor light-emitting device includes (A) a light-emitting portion obtained by laminating in sequence a first compound semiconductor layer, an active layer, and a second compound semiconductor layer; (B) a first electrode electrically connected to the first compound semiconductor layer; (C) a transparent conductive material layer formed on the second compound semiconductor layer; (D) an insulating layer composed of a transparent insulating material and having an opening, the insulating layer being formed on the transparent conductive material layer; and (E) a second electrode that reflects light from the light-emitting portion, the second electrode being formed on the transparent conductive material layer and on the insulating layer in a continuous manner, wherein, assuming that areas of the active layer, the transparent conductive material layer, the insulating layer, and the second electrode are respectively S1, S2, S3, and S4, S1?S2<S3 and S2<S4 are satisfied.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: July 17, 2012
    Assignee: Sony Corporation
    Inventor: Katsuhiro Tomoda
  • Patent number: 8207059
    Abstract: A layer of a porous insulating film precursor is formed on or over a substrate, a layer of a specific silicon compound is then formed, this silicon compound layer is pre-cured as necessary, and the porous insulating film precursor is exposed to UV through the silicon compound layer or pre-cured layer.
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: June 26, 2012
    Assignee: Fujitsu Limited
    Inventors: Shirou Ozaki, Yoshihiro Nakata, Ei Yano
  • Publication number: 20120100727
    Abstract: A method of manufacturing a semiconductor device includes steps of: generating positively or negatively charged fine bubbles having substantially zero buoyancy in a coating solution as an insulating film forming material; coating the coating solution including the bubbles on a substrate to form a coating film; and baking the coating film by heating the substrate before the bubbles are removed to obtain a porous low dielectric constant insulating film.
    Type: Application
    Filed: August 5, 2008
    Publication date: April 26, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Sumie Nagaseki
  • Patent number: 8129269
    Abstract: In a BEOL process, UV radiation is used in a curing process of ultra low-k (ULK) dielectrics. This radiation penetrates through the ULK material and reaches the cap film underneath it. The interaction between the UV light and the film leads to a change the properties of the cap film. Of particular concern is the change in the stress state of the cap from compressive to tensile stress. This leads to a weaker dielectric-cap interface and mechanical failure of the ULK film. A layer of nanoparticles is inserted between the cap and the ULK film. The nanoparticles absorb the UV light before it can damage the cap film, thus maintaining the mechanical integrity of the ULK dielectric.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: March 6, 2012
    Assignee: International Business Machines Corporation
    Inventors: Junjing Bao, Tien-Jen J. Cheng, Naftali Lustig
  • Patent number: 8101958
    Abstract: Embodiments relate to a semiconductor light-emitting device. The semiconductor light-emitting device comprises a plurality of compound semiconductor layers including a first 5 conductive semiconductor layer; an active layer on the first conductive semiconductor layer; and a second conductive semiconductor layer on the active layer; an electrode under the plurality of compound semiconductor layers; an electrode portion on the plurality of compound semiconductor layers; and a bending i0 prevention member comprising a pattern on the plurality of compound semiconductor layers.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: January 24, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventor: Hwan Hee Jeong
  • Patent number: 8097932
    Abstract: A method for fabricating a SiCOH dielectric material comprising Si, C, O and H atoms from a single organosilicon precursor with a built-in organic porogen is provided. The single organosilicon precursor with a built-in organic porogen is selected from silane (SiH4) derivatives having the molecular formula SiRR1R2R3, disiloxane derivatives having the molecular formula R4R5R6—Si—O—Si—R7R8R9, and trisiloxane derivatives having the molecular formula R10R11R12—Si—O—Si—R13R14—O—Si—R15R16R17 where R and R1-17 may or may not be identical and are selected from H, alkyl, alkoxy, epoxy, phenyl, vinyl, allyl, alkenyl or alkynyl groups that may be linear, branched, cyclic, polycyclic and may be functionalized with oxygen, nitrogen or fluorine containing substituents. In addition to the method, the present application also provides SiCOH dielectrics made from the inventive method as well as electronic structures that contain the same.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: January 17, 2012
    Assignee: International Business Machines Corporation
    Inventors: Son Van Nguyen, Stephen McConnell Gates, Deborah A. Neumayer, Alfred Grill
  • Patent number: 8080483
    Abstract: A method of forming a nanoporous film is disclosed. The method comprises forming a coating solution including clusters, surfactant molecules, a solvent, and one of an acid catalyst and a base catalyst. The clusters comprise inorganic groups. The method further comprises aging the coating solution for a time period to select a predetermined phase that will self-assemble and applying the coating solution on a substrate. The method further comprises evaporating the solvent from the coating solution and removing the surfactant molecules to yield the nanoporous film.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: December 20, 2011
    Assignee: Purdue Research Foundation
    Inventors: Hugh W. Hillhouse, Vikrant N. Urade, Ta-Chen Wei, Michael P. Tate
  • Patent number: 7977240
    Abstract: Metal ink compositions, methods of forming such compositions, and methods of forming conductive layers are disclosed. The ink composition includes a bulk metal, a transition metal source, and an organic solvent. The transition metal source may be a transition metal capable of forming a silicide, in an amount providing from 0.01 to 50 at. % of the transition metal relative to the bulk metal. Conductive structures may be made using such ink compositions by forming a silicon-containing layer on a substrate, printing a metal ink composition on the silicon-containing layer, and curing the composition. The metal inks of the present invention have high conductivity and form low resistivity contacts with silicon, and reduce the number of inks and printing steps needed to fabricate integrated circuits.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: July 12, 2011
    Assignee: Kovio, Inc.
    Inventors: Joerg Rockenberger, Yu Chen, Fabio Zürcher, Scott Haubrich
  • Patent number: 7968471
    Abstract: The present invention provides a process of producing a porous insulating film effective as an insulating film constituting a semiconductor device and a process of producing a porous insulating film having high adhesion to a semiconductor material, which is in contact with the upper and lower interfaces of the insulating film. Gas containing molecule vapor of at least one or more organic silica compounds, which have a cyclic silica skeleton in its molecule and have at least one or more unsaturated hydrocarbon groups bound with the cyclic silica skeleton is introduced into plasma to grow a porous insulating film on a semiconductor substrate.
    Type: Grant
    Filed: November 29, 2004
    Date of Patent: June 28, 2011
    Assignee: NEC Corporation
    Inventors: Yoshimichi Harada, Yoshihiro Hayashi, Fuminori Itoh, Kenichiro Hijioka, Tsuneo Takeuchi
  • Patent number: 7947611
    Abstract: A method for depositing a low dielectric constant film by flowing a oxidizing gas into a processing chamber, flowing an organosilicon compound from a bulk storage container through a digital liquid flow meter at an organosilicon flow rate to a vaporization injection valve, vaporizing the organosilicon compound and flowing the organosilicon compound and a carrier gas into the processing chamber, maintaining the organosilicon flow rate to deposit an initiation layer, flowing a porogen compound from a bulk storage container through a digital liquid flow meter at a porogen flow rate to a vaporization injection valve, vaporizing the porogen compound and flowing the porogen compound and a carrier gas into the processing chamber, increasing the organosilicon flow rate and the porogen flow rate while depositing a transition layer, and maintaining a second organosilicon flow rate and a second porogen flow rate to deposit a porogen containing organosilicate dielectric layer.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: May 24, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Dustin W. Ho, Juan Carlos Rocha-Alvarez, Alexandros T. Demos, Kelvin Chan, Nagarajan Rajagopalan, Visweswaren Sivaramakrishnan
  • Patent number: 7935643
    Abstract: The formation of a gap-filling silicon oxide layer with reduced tendency towards cracking is described. The deposition involves the formation of a flowable silicon-containing layer which facilitates the filling of trenches. Subsequent processing at high substrate temperature causes less cracking in the dielectric film than flowable films formed in accordance with methods in the prior art. A compressive liner layer deposited prior to the formation of the gap-filling silicon oxide layer is described and reduces the tendency for the subsequently deposited film to crack. A compressive capping layer deposited after a flowable silicon-containing layer has also been determined to reduce cracking. Compressive liner layers and compressive capping layers can be used alone or in combination to reduce and often eliminate cracking. Compressive capping layers in disclosed embodiments have additionally been determined to enable an underlying layer of silicon nitride to be transformed into a silicon oxide layer.
    Type: Grant
    Filed: October 22, 2009
    Date of Patent: May 3, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Anjana M. Patel, Nitin K. Ingle, Shankar Venkataraman
  • Patent number: 7923384
    Abstract: In a formation method of a porous insulating film by supplying at least organosiloxane and an inert gas to a reaction chamber and forming an insulating film by a plasma vapor deposition method, a partial pressure of the organosiloxane in the reaction chamber is changed by varying a volume ratio of the organosiloxane and the inert gas to be supplied during deposition. Thus, the dielectric constant of the insulating film in the semiconductor device is reduced while the adhesion of the insulating film with other materials is improved. It is desirable that the organosiloxane be cyclic organosiloxane including at least silicon, oxygen, carbon, and hydrogen, and that the total pressure of the reaction chamber be constant during deposition.
    Type: Grant
    Filed: November 24, 2006
    Date of Patent: April 12, 2011
    Assignee: NEC Corporation
    Inventors: Munehiro Tada, Naoya Furutake, Tsuneo Takeuchi, Yoshihiro Hayashi
  • Patent number: 7923820
    Abstract: A porous dielectric element is produced by forming a first dielectric and a second dielectric. The second dielectric is dispersed in the first dielectric. The second dielectric is then removed from the second dielectric by using a chemical dissolution. The removal of the second dielectric from the first dielectric leaves pores in the first dielectric. The pores, which are filled with air, improve the overall dielectric constant of the resulting dielectric element.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: April 12, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Simon Jeannot, Laurent Favennec
  • Patent number: 7871835
    Abstract: Disclosed is a method for packaging an LED by a thermoplastic copolymer. The copolymer is polymerized by 100 parts by weight of an acrylic ester, 0.1 to 30 parts by weight of a hydrogen bond monomer, and 0.1 to 70 parts by weight of a bulky monomer. The copolymer has transparency greater than 90%, thermal resistance greater than 130° C., and moisture absorption less than 0.5 wt %, such that the copolymer may be applied as packaging material for a light emitting device.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: January 18, 2011
    Assignees: Industrial Technology Research Institute, Topco Technologies Corp.
    Inventors: Shu-Ling Yeh, Ya-Lan Chuang, Pei-Jung Tsai, Chih-Hsiang Lin, Hsin-Ching Kao, Feng-Chih Chang, Tang-Jung Wu
  • Patent number: 7867922
    Abstract: The present invention is a film forming method for an SiOCH film, comprising a unit-film-forming step including: a deposition step of depositing an SiOCH film element by using an organic silicon compound as a raw material and by using a plasma CVD method; and a hydrogen plasma processing step of providing a hydrogen plasma process to the deposited SiOCH film element, wherein the unit-film-forming step is repeated several times so as to form an SiOCH film on a substrate.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: January 11, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Shinji Ide, Yasuhiro Oshima, Yusaku Kashiwagi
  • Patent number: 7867331
    Abstract: A sacrificial coating material includes: at least one inorganic compound, and at least one material modification agent, wherein the sacrificial coating material is dissolvable in an alkaline-based chemistry or a fluorine-based chemistry. A method of producing a sacrificial coating material includes: providing at least one inorganic compound, providing at least one material modification agent, combining the at least one inorganic compound with the at least one material modification agent to form the sacrificial coating material, wherein the sacrificial coating material is dissolvable in an alkaline-based chemistry or a fluorine-based chemistry, but not organic casting solvents commonly used in organic BARC materials.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: January 11, 2011
    Assignee: Honeywell International Inc.
    Inventors: Joseph Kennedy, Jason Stuck
  • Patent number: 7842518
    Abstract: A method for fabricating a semiconductor device, includes forming a porous dielectric film above a substrate using a porous insulating material, forming an opening in the porous dielectric film, repairing film quality of the porous dielectric film on a surface of the opening by feeding a predetermined gas replacing a Si—OH group to the opening, and performing pore sealing of the surface of the opening using the same predetermined gas as that used for film quality repairs after repairing the film quality.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: November 30, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hideshi Miyajima
  • Patent number: 7732349
    Abstract: The invention provides a manufacturing method of an insulating film having a plurality of pores, as well as a manufacturing method of a highly integrated semiconductor device with high yield. According to the invention, a porous insulating film is formed by forming a plurality of pores in an interlayer insulating film using a laser beam, which results in lower dielectric constant of the interlayer insulating film. In addition, a composition containing conductive particles is discharged onto the porous insulating film by a droplet discharge method typified by an ink jet printing method, and then baked to form a wire. As the laser beam, an ultrashort pulse laser beam is preferably used.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: June 8, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiroko Yamamoto
  • Patent number: 7709371
    Abstract: A method for restoring hydrophobicity to the surfaces of organosilicate glass dielectric films which have been subjected to an etchant or ashing treatment. These films are used as insulating materials in the manufacture of integrated circuits to ensure low and stable dielectric properties in these films. The method deters the formation of stress-induced voids in these films. An organosilicate glass dielectric film is patterned to form vias and trenches by subjecting it to an etchant or ashing reagent in such a way as to remove at least a portion of previously existing carbon containing moieties and reduce hydrophobicity of said organosilicate glass dielectric film. The vias and trenches are thereafter filled with a metal and subjected to an annealing treatment.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: May 4, 2010
    Assignee: Honeywell International Inc.
    Inventors: Anil S. Bhanap, Teresa A. Ramos, Nancy Iwamoto, Roger Y. Leung, Ananth Naman
  • Patent number: 7687409
    Abstract: A dielectric layer containing an atomic layer deposited titanium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric layer provide a dielectric layer for use in a variety of electronic devices. Embodiments include forming titanium silicates and/or mixtures of titanium oxide and silicon oxides as dielectric layers in devices in an integrated circuit. In an embodiment, a titanium silicon oxide film is formed by depositing titanium oxide by atomic layer deposition and silicon oxide by atomic layer deposition onto a substrate surface. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing an atomic layer deposited titanium silicon oxide film, and methods for forming such structures.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: March 30, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes