On A Silicon Body (epo) Patents (Class 257/E21.281)
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Patent number: 8455360Abstract: A method for fabricating a storage node of a semiconductor device includes forming a sacrificial dielectric pattern with a storage node hole on a substrate, forming a support layer on the sacrificial dielectric pattern, forming a storage node, supported by the support layer, in the storage node hole, performing a full dip-out process to expose the outer wall of the storage node, and performing a cleaning process for removing or reducing a bridge-causing material formed on the surface of the support layer.Type: GrantFiled: March 28, 2011Date of Patent: June 4, 2013Assignee: SK Hynix Inc.Inventors: Hyo Geun Yoon, Ji Yong Park, Sun Jin Lee
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Patent number: 8202806Abstract: A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.Type: GrantFiled: October 3, 2005Date of Patent: June 19, 2012Assignee: Micron Technology, Inc.Inventors: Randhir P.S. Thakur, Ravi Iyer, Howard Rhodes
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Patent number: 7902099Abstract: A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process.Type: GrantFiled: March 17, 2010Date of Patent: March 8, 2011Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Patent number: 7759718Abstract: A method of forming a dielectric layer in a capacitor adapted for use in a semiconductor device is disclosed. The method includes forming a first ZrO2 layer, forming an interfacial layer using a plasma treatment on the first ZrO2 layer, and forming a second ZrO2 layer on the interfacial layer.Type: GrantFiled: October 2, 2007Date of Patent: July 20, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-yeol Kang, Jong-cheol Lee, Ki-vin Im, Jae-hyun Yeo, Hoon-sang Choi, Eun-ae Chung
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Patent number: 7683001Abstract: A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process.Type: GrantFiled: December 29, 2008Date of Patent: March 23, 2010Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Publication number: 20090186467Abstract: A substrate treatment apparatus includes a reaction tube and a heater heating a silicon wafer. Trimethyl aluminum (TMA) and ozone (O3) are alternately fed into the reaction tubeto generate Al2O3 film on the surface of the wafer. The apparatus also includes supply tubes and for flowing the ozone and TMA and a nozzle supplying gas into the reaction tube. The two supply tubes are connected to the nozzle disposed inside the heater in a zone inside the reaction tube where a temperature is lower than a temperature near the wafer, and the ozone and TMA are supplied into the reaction tube through the nozzle.Type: ApplicationFiled: March 30, 2009Publication date: July 23, 2009Inventors: Masanori SAKAI, Toru Kagaya
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Patent number: 7538001Abstract: A transistor gate forming method includes forming a first and a second transistor gate. Each of the two gates includes a lower metal layer and an upper metal layer. The lower metal layer of the first gate originates from an as-deposited material exhibiting a work function the same as exhibited in an as-deposited material from which the lower metal layer of the second gate originates. However, the first gate's lower metal layer exhibits a modified work function different from a work function exhibited by the second gate's lower metal layer. The first gate's lower metal layer may contain less oxygen and/or carbon in comparison to the second gate's lower metal layer. The first gate's lower metal layer may contain more nitrogen in comparison to the second gate's lower metal layer. The first gate may be a n-channel gate and the second gate may be a p-channel gate.Type: GrantFiled: September 1, 2005Date of Patent: May 26, 2009Assignee: Micron Technology, Inc.Inventors: D. V. Nirmal Ramaswamy, Ravi Iyer
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Patent number: 7531468Abstract: A method of forming a dielectric stack on a pre-treated surface. The method comprises pre-cleaning a semiconductor wafer to remove native oxide, such as by applying hydrofluoric acid to form an HF-last surface, pre-treating the HF-last surface with ozonated deionized water, forming a dielectric stack on the pre-treated surface and providing a flow of NH3 in a process zone surrounding the wafer. Alternately, the method includes pre-treating the HF-last surface with NH3, forming the stack after the pre-treating, and providing a flow of N2 in a process zone surrounding the wafer after the forming. The method also includes pre-treating the HF-last surface using an in-situ steam generation process, forming the stack on the pre-treated surface, and annealing the wafer after the forming.Type: GrantFiled: October 30, 2007Date of Patent: May 12, 2009Assignee: Applied Materials, Inc.Inventors: Craig R. Metzner, Shreyas S. Kher, Shixue Han
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Patent number: 7473662Abstract: A method of forming (and an apparatus for forming) a metal-doped aluminum oxide layer on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process.Type: GrantFiled: May 17, 2005Date of Patent: January 6, 2009Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Patent number: 7312163Abstract: The invention includes methods in which at least two different precursors are flowed into a reaction chamber at different and substantially non-overlapping times relative to one another to form a material over at least a portion of a substrate, and in which at least one of the precursors is asymmetric with respect to a physical property. A field influencing the asymmetric physical property is oriented within the reaction chamber, and is utilized to affect alignment of the precursor having the asymmetric property as the material is formed. The asymmetric physical property can, for example, be an anisotropic charge distribution associated with the precursor, and in such aspect, the field utilized to influence the asymmetric physical property can be an electric field provided within the reaction chamber and/or a magnetic field provided within the reaction chamber. The methodology of the present invention can be utilized in atomic layer deposition processes.Type: GrantFiled: September 24, 2003Date of Patent: December 25, 2007Assignee: Micron Technology, Inc.Inventors: Garo J. Derderian, Gurtej S. Sandhu
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Patent number: 7304004Abstract: A method of forming a dielectric stack on a pre-treated surface. The method comprises pre-cleaning a semiconductor wafer to remove native oxide, such as by applying hydroflouric acid to form an HF-last surface, pre-treating the HF-last surface with ozonated deionized water, forming a dielectric stack on the pre-treated surface and providing a flow of NH3 in a process zone surrounding the wafer. Alternately, the method includes pre-treating the HF-last surface with NH3, forming the stack after the pre-treating, and providing a flow of N2 in a process zone surrounding the wafer after the forming. The method also includes pre-treating the HF-last surface using an in-situ steam generation process, forming the stack on the pre-treated surface, and annealing the wafer after the forming.Type: GrantFiled: August 6, 2004Date of Patent: December 4, 2007Assignee: Applied Materials, Inc.Inventors: Craig R. Metzner, Shreyas S. Kher, Shixue Han