Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a plurality of Si-based pattern portions above a semiconductor substrate, the plurality of Si-based pattern portions being adjacent in a direction substantially parallel to a surface of the semiconductor substrate via insulating films; forming a metal film above the plurality of Si-based pattern portions and the insulating films so as to contact with the plurality of Si-based pattern portions; processing whole areas or upper portions of the plurality of Si-based pattern portions into a plurality of silicide layers by a silicidation reaction between the plurality of Si-based pattern portions and the metal film by heat treatment; and removing the plurality of silicide layers formed above the insulating films by applying planarizing treatment to the plurality of silicide layers.

Abstract: Provided is a method of fabricating a semiconductor device including a dual suicide process. The method may include sequentially siliciding and stressing a first MOS region, and sequentially siliciding and stressing a second MOS region after siliciding and stressing the first MOS region, the second MOS region being a different type than the first MOS region.

Abstract: An insulation layer may be formed on an object having a contact region. The insulation layer may be partially etched to form an opening exposing the contact region. A material layer including silicon and oxygen may be formed on the exposed contact region. A metal layer may be formed on the material layer including silicon and oxygen. The material layer including silicon and oxygen may be reacted with the metal layer to form a metal oxide silicide layer at least on the contact region. A conductive layer may be formed on the metal oxide silicide layer to fill up the opening.

Abstract: A method and apparatus for processing a substrate is provided. The method of processing a substrate includes providing a substrate comprising a conductive material, performing a pre-treatment process on the conductive material, flowing a silicon based compound on the conductive material to form a silicide layer, performing a post treatment process on the silicide layer, and depositing a barrier dielectric layer on the substrate.

Abstract: A solid-state imaging device is provided. The solid-state imaging device includes a pixel section, a peripheral circuit section, a silicide blocking layer formed in the pixel section except for part or whole of an area above an isolation portion in the pixel section, and a metal-silicided transistor formed in the peripheral circuit section.

Abstract: The present invention in one embodiment provides a method of producing a device including providing a semiconducting device including a gate structure including a silicon containing gate conductor atop a substrate; forming a metal layer on at least the silicon containing gate conductor; and directing chemically inert ions to impact the metal layer, wherein momentum transfer from of the chemically inert ions force metal atoms from the metal layer into the silicon containing gate conductor to provide a silicide gate conductor.

Abstract: Method for manufacturing a semiconductor device, includes: forming a layer of dicobalt monosilicide (Co2Si) or of cobalt (Co) on a device-forming surface of a silicon substrate in a sputter apparatus, by utilizing a predetermined temperature profile; elevating a temperature of the silicon substrate to a predetermined temperature T2, which is equal to or higher than 600° C., conducted after forming the layer of Co or Co2Si; and forming a layer of monocobalt monosilicide (CoSi) on the device-forming surface of the silicon substrate at a temperature equal to or higher than T2, conducted after heating the silicon substrate to T2, wherein, the silicon substrate is elevated to a temperature between a highest reachable temperature T1 of the silicon substrate during forming the layer of Co or Co2Si and the temperature T2 at a temperature ramp rate of equal to or higher than 50° C./sec.

Abstract: Element characteristics disadvantageously fluctuate because the composition of the resultant silicide varies according to the change of the gate length when a full silicide gate electrode is formed by sintering a metal/poly-Si structure. The element characteristics also fluctuate due to element-to-element non-uniformity of the resultant silicide composition. By first forming full silicide having a metal-rich composition, depositing a Si layer thereon, and sintering the combined structure, the metal in the metal-rich silicide diffuses into the Si layer, so that the Si layer is converted into silicide. The entire structure thus is converted into full silicide having a smaller metal composition ratio.

Abstract: A semiconductor device includes a semiconductive channel region and a gate region. The gate region has at least one buried part extending under the channel region. The buried part of the gate region is formed by forming a cavity under the channel region. That cavity is at least partial filled with silicon and a metal. An annealing step is performed so as to form a silicide of said metal in the cavity. The result is a totally silicided buried gate for the semiconductor device.

Abstract: A method of fabricating a dual gate oxide of a semiconductor device includes forming a first gate insulation layer over an entire surface of a substrate, removing a portion of the first gate insulation layer to selectively expose a first region of the substrate using a first mask and performing an ion implantation on the selectively exposed first region of the substrate using the first mask, and forming a second gate insulation layer on the first gate insulation layer and the exposed first region of the substrate to form a resultant gate insulation layer having a first thickness over the first region of the substrate and a second thickness over a remaining region of the substrate, the first thickness and the second thickness being different.

Abstract: A method for depositing metals on surfaces is provided which comprises (a) providing a substrate (103) having a horizontal surface (107) and a vertical surface (105); (b) depositing a first metal layer (109) over the horizontal and vertical surfaces; (c) depositing a layer of polysilicon (111) over the horizontal and vertical surfaces; (d) treating the layer of polysilicon with a plasma such that a residue (113) remaining from the treatment is preferentially formed over the horizontal surfaces rather than the vertical surfaces, and wherein the residue is resistant to a first metal etch; and (e) exposing the substrate to the first metal etch.

Abstract: Highly thermally stable metal silicides and methods utilizing the metal silicides in semiconductor processing are provided. The metal silicides are preferably nickel silicides formed by the reaction of nickel with substitutionally carbon-doped single crystalline silicon which has about 2 atomic % or more substitutional carbon. Unexpectedly, the metal silicides are stable to temperatures of about 900° C. and higher and their sheet resistances are substantially unaffected by exposure to high temperatures. The metal silicides are compatible with subsequent high temperature processing steps, including reflow anneals of BPSG.

Abstract: Structures and related methods including fully silicided regions are disclosed. In one embodiment, a structure includes a substrate; a partially silicided region located in an active region of an integrated circuit formed on the substrate; a fully silicided region located in a non-active region of the integrated circuit, and wherein the partially and fully silicided regions are formed from a common semiconductor layer.

Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.

Abstract: A semiconductor device includes a MIS transistor having a gate electrode which is fully silicided with metal. The edge parts of the gate electrode are lower in height than the other part thereof. Sidewall spacers are formed to cover the side and top surfaces of the edge parts of the gate electrode.

Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.

Abstract: A method for fabricating a flash memory device includes providing a semi-finished substrate including a first polysilicon layer electrically isolated by an isolation structure. Recesses are formed in the isolation structure to partially expose sidewalls of the first polysilicon layer. A second polysilicon layer is formed over the exposed first polysilicon layer. Recesses are formed in a portion of the isolation structure not covered by the second polysilicon layer. A dielectric structure is formed over a resultant surface profile obtained after the recesses are formed in the isolation structure. A control gate is formed over the dielectric structure.

Abstract: A semiconductor device manufacturing method, includes a step of forming refractory metal silicide layers 13a to 13c in a partial area of a semiconductor substrate 10, a step of forming an interlayer insulating film 21 on the refractory metal silicide layers 13a to 13c, a step of forming a first conductive film 31, a ferroelectric film 32, and a second conductive film 33 in sequence on the interlayer insulating film 21, a step of forming a capacitor Q consisting of a lower electrode 31a, a capacitor dielectric film 32a, and an upper electrode 33a by patterning the first conductive film 33, the ferroelectric film 32, and the second conductive film 31, and a step of performing an annealing for an annealing time to suppress a agglomeration area of the refractory metal silicide layers 13a to 13c within an upper limit area.

Abstract: In a semiconductor device using a polysilicon contact, such as a poly plug between a transistor and a capacitor in a container cell, an interface is provided where the poly plug would otherwise contact the bottom plate of the capacitor. The interface bars silicon from the plug from diffusing into the capacitor's dielectric. The interface can also include an oxygen barrier to prevent the poly plug from oxidizing during processing. Below the interface is a silicide layer to help enhance electrical contact with the poly plug. In a preferred method, the interface is created by selectively depositing a layer of titanium over a recessed poly plug to the exclusion of the surrounding oxide. The deposition process allows for silicidation of the titanium. The top half of the titanium silicide is then nitridized. A conformal ruthenium or ruthenium oxide layer is subsequently deposited, covering the titanium nitride and lining the sides and bottom of the container cell.

Abstract: Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.

Abstract: A semiconductor device comprises a semiconductor substrate, an N-channel MISFET and a P-channel MISFET provided on the semiconductor substrate, each of the N- and P-channel MISFETs being isolated by an isolation region and having a gate insulating film, a first gate electrode film provided on the gate insulating film of the N-channel MISFET and composed of a first metal silicide, a second gate electrode film provided on the gate insulating film of the P-channel MISFET and composed of a second metal silicide made of a second metal material different from a first metal material composing the first metal silicide, and a work function of the first gate electrode film being lower than that of the second gate electrode film.

Abstract: A method inhibits metal silicide encroachment in channel regions in a transistor that uses metal silicide as an electrical contact to its terminals. A metal layer is deposited overlying the transistor. A first anneal that is a low temperature anneal forms metal silicide regions to source, gate and drain terminals of the transistor. The low temperature inhibits lateral encroachment. Unsilicided portions of the metal are removed and followed by an ion implant of an element, such as nitrogen, that diffuses into the metal silicide regions. A second anneal at a higher temperature than the first anneal is completed wherein the implanted nitrogen ions prevent lateral encroachment of metal silicide.

Abstract: A method used to form a cobalt metal layer on a silicon surface using an atomic layer deposition (ALD) process comprises a treatment of the silicon surface prior to cobalt formation. Treatment includes serial exposure to one or more cycles comprising a titanium nitride precursor or a tantalum nitride precursor, followed by an optional exposure to ammonia. After this treatment, the silicon surface is exposed to a metal organic cobalt such as cyclopentadienylcobalt dicarbonyl to form a cobalt precursor on the silicon surface, which is then exposed to hydrogen or ammonia to reduce the precursor to an ALD cobalt metal layer. Once this initial metal layer is formed, additional cobalt ALD layers may be completed to form a cobalt metal layer of a desired thickness.