Deposition Of Conductive Or Semi-conductive Organic Layer (epo) Patents (Class 257/E21.299)
  • Patent number: 11592714
    Abstract: A method of coating a polyimide film and a method of fabricating a display panel are provided by the embodiments of the present invention. The method of coating a polyimide film includes providing a glass substrate and at least one nozzle; forming a nanomaterial filled graphic letterpress on the glass substrate, wherein the nanomaterial filled graphic letterpress is formed with a plurality of protrusions; and spraying a polyimide liquid on the nanomaterial filled graphic letterpress by the at least one nozzle to form a polyimide film.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: February 28, 2023
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Haiyang Shen
  • Patent number: 9006019
    Abstract: A method for manufacturing a light-emitting device includes a step of forming an etching resistant protection layer on a substrate provided with an organic planarizing layer, a step of forming a plurality of electrodes on the etching resistant protection layer, a step of forming an organic compound layer on the substrate provided with the plurality of electrodes, a step of forming a resist layer on the organic compound layer formed on parts of electrodes among the plurality of electrodes using a photolithographic method, and a step of removing the organic compound layer in a region not covered with the resist layer by dry etching, wherein an entire surface of the organic planarizing layer on the substrate on which steps up to the step of forming the plurality of electrodes have been performed is covered with at least one of the etching resistant protection layer and the electrode.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 14, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Manabu Otsuka, Tomoyuki Hiroki
  • Patent number: 8796067
    Abstract: A method for forming an organic material layer on a substrate in an in-line deposition system is disclosed. In one aspect, the organic material is deposited with a predetermined non-constant deposition rate profile, which includes a first predetermined deposition rate range provided to deposit at least a first monolayer of the organic material layer with a first predetermined average deposition rate and a second predetermined deposition rate range provided to deposit at least a second monolayer of the organic material layer with a second predetermined average deposition rate. The injection of organic material through the openings of the injector is controlled for realizing the predetermined deposition rate profile.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: August 5, 2014
    Assignees: IMEC, Nederlandse Organisatie voor Toegepast-Natuurwe tenschappelijk Onderzoek (TNO), UniversitéCatholique de Louvain (UCL)
    Inventors: Cedric Rolin, Jan Genoe
  • Patent number: 8697485
    Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: April 15, 2014
    Assignees: Vorbeck Materials Corporation, The Trustees of Princeton University
    Inventors: John M. Crain, John S. Lettow, Ilhan A. Aksay, Sibel A. Korkut, Katherine S. Chiang, Chuan-Hua Chen, Robert K. Prud'Homme
  • Patent number: 8673702
    Abstract: A display device and method for fabricating includes patterning a field shield dielectric layer to expose conductors and form a cavity over the conductors. InkJet printing a semiconductor material fills a portion of the cavity in contact with the conductors. An insulation material is deposited on the semiconductor material. A pixel pad is formed over the insulation material and the field shield dielectric layer. A pixel is formed which includes a thin film transistor with an ink jet printed semiconductor layer.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: March 18, 2014
    Assignee: Creator Technology B.V.
    Inventors: Fredericus Johannes Touwslager, Gerwin Hermanus Gelinck
  • Patent number: 8664023
    Abstract: A vapor deposition method of the present invention includes the steps of (i) preparing a mask unit including a shadow mask (81) and a vapor deposition source (85) fixed in position relative to each other, (ii) while moving at least one of the mask unit and the film formation substrate (200) relative to the other, depositing a vapor deposition flow, emitted from the vapor deposition source (85), onto a vapor deposition region (210), and (iii) adjusting the position of a second shutter (111) so that the second shutter (111) blocks a vapor deposition flow traveling toward the vapor deposition unnecessary region (210).
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 4, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Sonoda, Shinichi Kawato, Satoshi Inoue, Satoshi Hashimoto
  • Patent number: 8530901
    Abstract: A method for fabricating a thin film transistor and a thin film transistor includes a polycrystalline silicon layer formed by irradiating an amorphous silicon layer with a laser beam through an organic layer formed on the amorphous silicon layer and removing the organic layer.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: September 10, 2013
    Assignee: LG Display Co., Ltd.
    Inventor: Jae Bum Park
  • Patent number: 8507897
    Abstract: An organic EL element includes a functional layer disposed between an anode and a cathode on a substrate and including laminated different organic thin films including a light-emitting layer, and a partition wall which defines the functional layer. Each of the organic thin films is formed by applying a liquid containing a functional layer-forming material on a film-forming region defined by the partition wall and then drying the liquid. The partition wall has at least one step portion provided in the side wall thereof in the thickness direction, and liquid repellency is imparted to the uppermost surface of the partition wall and the upper surface of the step portion. The surface of the side wall excluding the step portion has lyophilicity in comparison with the upper surface of the step portion.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: August 13, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Hirokazu Yanagihara
  • Patent number: 8482422
    Abstract: A thin film deposition apparatus to remove static electricity generated between a substrate and a mask, and a method of manufacturing an organic light-emitting display device using the thin film deposition apparatus.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: July 9, 2013
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chang-Soon Ji, Tae-Seung Kim, Jong-Woo Lee, Chengguo An
  • Patent number: 8470720
    Abstract: A wall surface of a film forming container is heated to or above a vaporization temperature of a material monomer, which is used to form an organic film, by using an external heater formed along the wall surface of the film forming container, substrates are heated to a thermal polymerization reaction temperature by using an internal heater that is disposed apart from the external heater and near a substrate-supporting container in which the substrates are received, and the organic film is formed through thermal polymerization occurring on the substrates by supplying the material monomer into the film forming container.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: June 25, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Ken Nakao, Muneo Harada
  • Patent number: 8435816
    Abstract: One embodiment of the present invention provides a method for fabricating an InGaAlN light-emitting semiconductor structure. During the fabrication process, at least one single-crystal sacrificial layer is deposited on the surface of a base substrate to form a combined substrate, wherein the single-crystal sacrificial layer is lattice-matched with InGaAlN, and wherein the single crystal layer forms a sacrificial layer. Next, the InGaAlN light-emitting semiconductor structure is fabricated on the combined substrate. The InGaAlN structure fabricated on the combined substrate is then transferred to a support substrate, thereby facilitating a vertical electrode configuration. Transferring the InGaAlN structure involves etching the single-crystal sacrificial layer with a chemical etchant. Furthermore, the InGaAlN and the base substrate are resistant to the chemical etchant. The base substrate can be reused after the InGaAlN structure is transferred.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: May 7, 2013
    Assignee: Lattice Power (Jiangxi) Corporation
    Inventors: Chuanbing Xiong, Fengyi Jiang, Li Wang, Shaohua Zhang, Guping Wang, Guangxu Wang
  • Patent number: 8329532
    Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: December 11, 2012
    Assignee: Infineon Technologies AG
    Inventors: Herbert Schaefer, Martin Franosch, Thomas Meister, Josef Boeck
  • Patent number: 8318593
    Abstract: The invention relates to a method for electron beam induced deposition of electrically conductive material from a metal carbonyl with the method steps of providing at least one electron beam at a position of a substrate, storing at least one metal carbonyl at a first temperature, and heating the at least one metal carbonyl to at least one second temperature prior to the provision at the position at which the at least one electron beam impacts on the substrate.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: November 27, 2012
    Assignee: Carl Zeiss SMS GmbH
    Inventors: Nicole Auth, Petra Spies, Rainer Becker, Thorsten Hofmann, Klaus Edinger
  • Patent number: 8278135
    Abstract: There is provided a film formation apparatus which is capable of forming an EL layer using an EL material with high purity. The EL material is purified by sublimation immediately before film formation in the film formation apparatus, to thereby remove oxygen, water, and another impurity, which are included in the EL material. Also, when film formation is performed using the EL material (high purity EL material) obtained by purifying with sublimation as an evaporation source, a high purity EL layer can be formed.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: October 2, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toshimitsu Konuma, Takeshi Nishi
  • Patent number: 8222141
    Abstract: A method for producing an organometallic layer includes providing a substrate having at least a layer with atoms of an oxidizable metal on its surface. The surface is exposed to a fluid that includes organic molecules having at least two functional groups that contain elements of main group VI such that the atoms of the oxidizable metal form a bond with the organic molecules. By consumption of the atoms of oxidizable metal and of the organic molecules, the organometallic layer is formed on the substrate at locations on the surface of the substrate where the atoms of oxizable are disposed, the atoms of oxizable metal being incorporated into the organometallic layer. A thickness of the organometallic layer is determined by a duration of the exposing, a thickness of the layer including the atoms of the oxidizable metal, and the number of organic molecules in the fluid.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: July 17, 2012
    Assignee: Forschungzentrum Karlsruhe GmbH
    Inventors: Stefan Walheim, Thomas Schimmel, Matthias Barczewski, Marcel Mayor, Alfred Blaszczyk
  • Patent number: 8207055
    Abstract: A method for generating an electrode layer pattern in an organic functional device (101; 201) comprising a first transparent electrode layer (103; 203), a second electrode layer (104; 204) and an organic functional layer (102; 202) sandwiched between said first and second electrode layers (103, 104; 203, 204). The method comprises the steps of arranging (601) a laser (704; 804) to irradiate said organic functional device (701; 801) through said first transparent electrode layer (103; 203), selecting (602) a set of laser parameters in order to enable said laser (704; 804) to locally modify an electric conductivity of said second electrode layer (104; 204), and locally modifying, by said laser (704; 804) in accordance with said set of laser parameters, the electric conductivity of said second electrode layer (104; 204), thereby generating said electrode layer pattern.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: June 26, 2012
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Michael Büchel, Ivar Jacco Boerefijn, Edward Willem Albert Young, Adrianus Sempel
  • Patent number: 8202756
    Abstract: According to one embodiment, a method of manufacturing an organic EL device includes providing a structure including a substrate and an electrode positioned above the substrate, and forming an organic layer including a mixture of first and second organic materials above the electrode. The first organic material has a first sublimation point. The second organic material has a second sublimation point higher than the first sublimation point. The formation of the organic layer includes heating an evaporation material including a mixture of the first and second organic materials to an evaporation temperature so as to sublimate the first and second organic materials, and delivering the sublimed first and second organic materials toward the electrode to deposit a mixture including the first and second organic materials above the electrode. The evaporation temperature is, for example, a temperature higher than the second sublimation temperature by 50° C. or more.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: June 19, 2012
    Assignee: Toshiba Mobile Display Co., Ltd.
    Inventors: Kazuki Kitamura, Tetsuo Ishida
  • Patent number: 8202771
    Abstract: A manufacturing method of an organic semiconductor device including an organic semiconductor transistor formation process, wherein the process includes: an organic semiconductor layer formation step of using a substrate to form an organic semiconductor layer made of an organic semiconductor material on the substrate; a passivation layer formation step of forming pattern-wise on the organic semiconductor layer a passivation layer having an ability of shielding vacuum ultraviolet light and an organic semiconductor layer patterning step of irradiating vacuum ultraviolet light to the passivation layer and to the organic semiconductor layer to etch the organic semiconductor layer corresponding to a part where the passivation layer is not formed.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: June 19, 2012
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Mitsutaka Nagae, Hironori Kobayashi, Masanao Matsuoka, Hiroyuki Honda
  • Patent number: 8173481
    Abstract: A thin film deposition apparatus to remove static electricity generated between a substrate and a mask, and a method of manufacturing an organic light-emitting display device using the thin film deposition apparatus.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: May 8, 2012
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Chang-Soon Ji, Tae-Seung Kim, Jong-Woo Lee, Chengguo An
  • Patent number: 8158447
    Abstract: An organic electroluminescent device includes: a switching element and a driving element connected to each other on a substrate including a pixel region; a planarization layer on the switching element and the driving element, the planarization layer having a substantially flat top surface; a cathode on the planarization layer, the cathode connected to the driving element; an emitting layer on the cathode; and an anode on the emitting layer.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: April 17, 2012
    Assignee: LG Display Co., Ltd.
    Inventors: Jae-Hee Park, Kyung-Min Park, Seok-Jong Lee
  • Patent number: 8114703
    Abstract: According to one embodiment, a method of manufacturing an organic EL device includes providing a structure including a substrate and an electrode positioned above the substrate, and forming an organic layer including a mixture of first and second organic materials above the electrode. The first organic material has a first sublimation point. The second organic material has a second sublimation point higher than the first sublimation point. The formation of the organic layer includes heating an evaporation material including a mixture of the first and second organic materials to an evaporation temperature so as to sublimate the first and second organic materials, and delivering the sublimed first and second organic materials toward the electrode to deposit a mixture including the first and second organic materials above the electrode. The evaporation temperature is, for example, a temperature higher than the second sublimation temperature by 50° C. or more.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: February 14, 2012
    Assignee: Toshiba Mobile Display Co., Ltd.
    Inventors: Kazuki Kitamura, Tetsuo Ishida
  • Patent number: 8102052
    Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: January 24, 2012
    Assignee: Infineon Technologies AG
    Inventors: Herbert Schäfer, Martin Franosch, Thomas Meister, Josef Böck
  • Patent number: 8080436
    Abstract: A method of manufacturing a light emitting device includes: a first step of forming on a supporting substrate made of a stainless steel, a plurality of conductive members each including a first region containing Au and a second region containing a metallic member having a diffusion coefficient with respect to a metal in the stainless steel smaller than a diffusion coefficient of Au with respect to the metal in the stainless steel, a second step of forming a base member made of a light-blocking resin on the supporting substrate between the conductive members, a third step of bonding a light emitting element on an upper surface of a conductive member through an adhesive member, a fourth step of covering the light emitting element with an optically transmissive sealing member, and a fifth step of removing the supporting substrate and individually separating the light emitting devices.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: December 20, 2011
    Assignee: Nichia Corporation
    Inventor: Takafumi Sugiyama
  • Patent number: 8071432
    Abstract: A method of manufacturing an organic transistor active substrate is disclosed. The organic transistor active substrate includes an organic transistor in which a first electrode is formed on a substrate, a first insulating film is formed on the first electrode, a pair of second electrodes is formed on the first insulating film, and an active layer made of an organic semiconductor material is formed on the pair of second electrodes. The organic transistor is laminated with a second insulating film, and the second insulating film is laminated with a third electrode which is electrically coupled to one of the second electrodes via a through-hole provided through the second insulating film. The first electrode is formed by inkjet ejection; the first insulating film is formed by coating; the pair of second electrodes is formed by inkjet ejection; the active layer is formed by inkjet ejection; the second insulating film is formed by screen printing; and the third electrode is formed by screen printing.
    Type: Grant
    Filed: September 7, 2006
    Date of Patent: December 6, 2011
    Assignee: Ricoh Company, Ltd.
    Inventors: Yoshikazu Akiyama, Takumi Yamaga, Takanori Tano, Hidenori Tomono, Akishige Murakami, Hitoshi Arita, Mayuka Araumi
  • Patent number: 8067316
    Abstract: A conductive paste including conductive particles each of which has a size of greater than or equal to 0.1 ?m and less than or equal to 10 ?m, a resin, and a solvent is placed over a first conductor and the solvent is vaporized. In this manner, a second conductor having the conductive particles and a memory layer including the resin between the first conductor and the conductive particles is formed.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: November 29, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Takaaki Nagata
  • Patent number: 8063487
    Abstract: A first conducting layer is formed on a side of a main surface on which an electrode terminal of a semiconductor device is provided in a semiconductor substrate. The first conducting layer is electrically connected to the electrode terminal of the semiconductor device. A mask layer that has an opening at a predetermined position is formed on the first conducting layer. A second conducting layer is formed inside the opening of the mask layer. The mask layer is removed. A relocation wiring that includes the first conducting layer and electrically draws out the electrode terminal is formed by performing anisotropic etching for the first conducting layer using the second conducting layer as a mask. Finally, a bump is formed on the relocation wiring by causing the second conducting layer to reflow.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: November 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Migita, Hirokazu Ezawa, Tadashi Iijima, Takashi Togasaki
  • Patent number: 8053877
    Abstract: A semiconductor package includes a chip base material; a capacitor formed on the base material; and a cover formed over the base material to cover the capacitor, and having a side portion and an upper portion. The base material is provided with a bonding pattern connecting the base material and the cover to cover the capacitor. The bonding pattern includes a region A having a substantially uniform pattern width A, and at least one region B having a pattern width B which is larger than the width pattern width A.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: November 8, 2011
    Assignee: Panasonic Corporation
    Inventors: Ryo Fukasawa, Tatsuhiro Sawada
  • Patent number: 8048699
    Abstract: An organic electroluminescent device includes: a switching element and a driving element connected to each other on a substrate including a pixel region; a planarization layer on the switching element and the driving element, the planarization layer having a substantially flat top surface; a cathode on the planarization layer, the cathode connected to the driving element; an emitting layer on the cathode; and an anode on the emitting layer.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: November 1, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Jae-Hee Park, Kyung-Min Park, Seok-Jong Lee
  • Publication number: 20110183517
    Abstract: The invention relates to a method for electron beam induced deposition of electrically conductive material from a metal carbonyl with the method steps of providing at least one electron beam at a position of a substrate (90), storing at least one metal carbonyl at a first temperature, and heating the at least one metal carbonyl to at least one second temperature prior to the provision at the position at which the at least one electron beam impacts on the substrate (90).
    Type: Application
    Filed: August 7, 2009
    Publication date: July 28, 2011
    Applicant: CARL ZEISS SMS GMBH
    Inventors: Nicole Auth, Petra Spies, Rainer Becker, Thorsten Hofmann, Klaus Edinger
  • Patent number: 7977149
    Abstract: The invention provides a process for production of a transistor and an organic semiconductor element which allows satisfactory formation of active layers on desired surfaces, even if the active layers are organic semiconductor compound-containing active layers imparted with prescribed properties beforehand. A preferred mode of the process for production of a transistor is a process for production of a transistor provided with a source electrode and drain electrode, an active layer containing an organic semiconductor compound as a current channel between the electrodes, a gate electrode that controls the current flowing through the current channel and an insulating layer disposed between the active layer and gate electrode, wherein the process includes a pasting step in which a working liquid is situated between the active layer and insulating layer and the active layer and insulating layer are attached together.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: July 12, 2011
    Assignee: Sumitomo Chemical Company, Limited
    Inventor: Shinichi Yamate
  • Publication number: 20110155963
    Abstract: Water-soluble electrically conductive polymers and a composition comprising such polymers are provided. Also, an electrically conductive layer or film formed from the composition, and articles comprising the electrically conductive layer or film are provided. The electrically conductive polymers according to the present disclosure have one or more hydrophilic side chains. Hydrophilic side chains are covalently bonded to the conductive polymers, which allow the polymer to be stable at high temperature. Thus, the stability of electrical conductivity is prolonged. Depending on the concentration of hydrophilic side chains, the conductivity may be changed. The hydrophilic side chains provide a successful way to fabricate a ductile film exhibiting tunable conductivity. Furthermore, high levels of surface-resistance uniformity can be achieved in the field of coating technology that uses eco-friendly water-based solvents to uniformly and quickly coat the conductive polymer on to plastic film surfaces.
    Type: Application
    Filed: December 30, 2009
    Publication date: June 30, 2011
    Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventor: Dong Hoon CHOI
  • Patent number: 7960295
    Abstract: A method for fabricating a thin film transistor and a thin film transistor includes a polycrystalline silicon layer formed by irradiating an amorphous silicon layer with a laser beam through an organic layer formed on the amorphous silicon layer and removing the organic layer.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: June 14, 2011
    Assignee: LG Display Co., Ltd.
    Inventor: Jae Bum Park
  • Patent number: 7947552
    Abstract: One embodiment of the present invention relates to method for the concurrent deposition of multiple different crystalline structures on a semiconductor body utilizing in-situ differential epitaxy. In one embodiment of the present invention a preparation surface is formed, resulting in two distinct crystalline regions, a monocrystalline silicon substrate region and an isolating layer region. A monocrystalline silicon layer and an amorphous silicon layer are concurrently formed directly onto the preparation surface in the monocrystalline silicon substrate region and the isolating layer region, respectively. Deposition comprises the formation of two or more sub-layers. The process parameters can be varied for each individual sub-layer to optimize deposition characteristics.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: May 24, 2011
    Assignee: Infineon Technologies AG
    Inventors: Herbert Schäfer, Martin Franosch, Thomas Meister, Josef Böck
  • Patent number: 7902086
    Abstract: Improving memory retention properties of a polymer memory cell are disclosed. The methods include providing a semiconducting polymer layer containing at least one organic semiconductor and at least one of a carrier ion oxidation preventer and an electrode oxidation preventer. The oxidation preventers may contain at least one of 1) an oxygen scavenger, 2) a polymer with oxidizable side-chain groups which can be preferentially oxidized over the carrier ions/electrodes, and 3) an oxidizable molecule that can be preferentially oxidized over the carrier ions/electrodes.
    Type: Grant
    Filed: December 8, 2006
    Date of Patent: March 8, 2011
    Assignee: Spansion LLC
    Inventors: Swaroop Kaza, David Gaun, Michael A. Van Buskirk
  • Patent number: 7829474
    Abstract: A method for arraying nano material includes preparing a substrate coated with a dispersion solution where nano materials are dispersed and arraying the nano materials in the dispersion solution, in a uniform direction using a charged body.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: November 9, 2010
    Assignee: LG. Display Co., Ltd.
    Inventor: Gee Sung Chae
  • Publication number: 20100273328
    Abstract: A method for producing an organometallic layer includes providing a substrate having at least a layer with atoms of an oxidizable metal on its surface. The surface is exposed to a fluid that includes organic molecules having at least two functional groups that contain elements of main group VI such that the atoms of the oxidizable metal form a bond with the organic molecules. By consumption of the atoms of oxidizable metal and of the organic molecules, the organometallic layer is formed on the substrate at locations on the surface of the substrate where the atoms of oxizable are disposed, the atoms of oxizable metal being incorporated into the organometallic layer. A thickness of the organometallic layer is determined by a duration of the exposing, a thickness of the layer including the atoms of the oxidizable metal, and the number of organic molecules in the fluid.
    Type: Application
    Filed: May 18, 2006
    Publication date: October 28, 2010
    Applicant: Forschungszentrum Karlsruhe GmbH
    Inventors: Stefan Walheim, Thomas Schimmel, Matthias Barczewski, Marcel Mayor, Alfred Blaszczyk
  • Patent number: 7811852
    Abstract: An organic semiconductor device with a vertical structure having both functions of an organic thin film transistor and light-emitting element, where the electrical characteristics as both the organic thin film transistor and light-emitting element can be controlled in the case of forming a gate electrode with an organic conductive film, and a manufacturing method thereof. The above organic semiconductor device has such a structure that organic semiconductor films are sandwiched between a pair of electrodes functioning as a source electrode and drain electrode of an organic thin film transistor and also functioning as an anode and cathode of a light-emitting element, a thin organic conductive film functioning as a gate electrode is sandwiched between the organic semiconductor films, and a part of the organic conductive film is electrically connected to an auxiliary electrode, thereby the electrical characteristics as both the organic thin film transistor and light-emitting element can be controlled.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: October 12, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Yamamoto, Takahito Oyamada, Chihaya Adachi
  • Patent number: 7763936
    Abstract: A lateral MOS device is formed in a body having a surface and is formed by a semiconductor layer of a first conductivity type; a drain region of a second conductivity type, formed in the semiconductor layer and facing the surface; a source region of the second conductivity type, formed in the semiconductor layer and facing the surface; a channel of the first conductivity type, formed in the semiconductor layer between the drain region and the source region and facing the surface; and an insulated gate region, formed on top of the surface over the channel region. In order to improve the dynamic performance, a conductive region extends only on one side of the insulated gate region, on top of the drain region but not on top of the insulated gate region.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: July 27, 2010
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Antonello Santangelo, Salvatore Cascino, Leonardo Gervasi
  • Patent number: 7759205
    Abstract: Methods for producing a semiconductor device are provided. In one embodiment, a method includes the steps of: (i) fabricating a partially-completed semiconductor device including a substrate, a source/drain region in the substrate, a gate stack overlaying the substrate, and a sidewall spacer adjacent the gate stack; (ii) utilizing an anisotropic etch to remove an upper portion of the sidewall spacer while leaving intact a lower portion of the sidewall spacer overlaying the substrate; (iii) implanting ions in the source/drain region; and (iv) annealing the semiconductor device to activate the implanted ions. The step of annealing is performed with the lower portion of the sidewall spacer intact to deter the ingress of oxygen into the substrate and minimize under-oxide regrowth proximate the gate stack.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: July 20, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kingsuk Maitra, John Iacoponi
  • Patent number: 7759180
    Abstract: In a manufacturing method of a display substrate according to one or more embodiments, a plurality of thin films are patterned by using a photoresist film pattern having different thicknesses in each area on a substrate as etch masks. The photoresist film pattern may be etch-backed at least twice during the manufacturing process of the display substrate and may be used as the etch mask for patterns having shapes different from each other. Accordingly, the number of processes for manufacturing the mask patterns, which may be formed by a photolithography method in order to pattern the thin films formed on the substrate, may be reduced.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: July 20, 2010
    Inventors: Young-Min Kim, Tae-Young Choi
  • Publication number: 20100155954
    Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer dielectric (ILD) disposed on a substrate, wherein a source/drain contact area is exposed, forming a rare earth metal layer on the source/drain contact area, forming a transition metal layer on the rare earth metal layer; and annealing the rare earth metal layer and the transition metal layer to form a metal silicide stack structure.
    Type: Application
    Filed: December 18, 2008
    Publication date: June 24, 2010
    Inventors: Niloy Mukherjee, Matt Metz, Gilbert Dewey, Jack Kavalieros, Robert S. Chau
  • Patent number: 7718531
    Abstract: Preferred embodiments provide a method for forming at least one catalyst nanoparticle on at least one sidewall of a three-dimensional structure on a main surface of a substrate, the main surface lying in a plane and the sidewall of the three-dimensional structure lying in a plane substantially perpendicular to the plane of the main surface of the substrate. The method comprises obtaining a three-dimensional structure on the main surface, the three-dimensional structure comprising catalyst nanoparticles embedded in a non-catalytic matrix and selectively removing at least part of the non-catalytic matrix at the sidewalls of the three-dimensional structure to thereby expose at least one catalyst nanoparticle.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: May 18, 2010
    Assignee: IMEC
    Inventors: Aleksandar Radisic, Philippe M. Vereecken
  • Publication number: 20100090341
    Abstract: Patterned active layers formed by nano-imprint lithography for use in devices such as photovoltaic cells and hybrid solar cells. One such photovoltaic cell includes a first electrode and a first electrically conductive layer electrically coupled to the first electrode. The first conductive layer has a multiplicity of protrusions and recesses formed by a nano-imprint lithography process. A second electrically conductive layer substantially fills the recesses and covers the protrusions of the first conductive layer, and a second electrode is electrically coupled to the second conductive layer. A circuit electrically connects the first electrode and the second electrode.
    Type: Application
    Filed: October 13, 2009
    Publication date: April 15, 2010
    Applicants: MOLECULAR IMPRINTS, INC., BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM
    Inventors: Fen Wan, Frank Y. Xu, Sidlgata V. Sreenivasan, Shuqiang Yang
  • Patent number: 7687390
    Abstract: In one embodiment of a manufacturing method of a transparent conductive film of the present invention, a grid having a magnet is placed between a target and a substrate, and a pattern shaped transparent conductive film comprising the target material is formed over the substrate through a mask by a sputtering method. In other embodiment of a manufacturing method of a transparent conductive film of the present invention, a mask is placed on a substrate, a pattern shaped transparent conductive layer comprising a target material is formed on the substrate by a sputtering method, and a trap electrode having a magnet pin is installed between the target and the substrate.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: March 30, 2010
    Assignee: Toppan Printing Co., Ltd.
    Inventor: Yutaka Kuriya
  • Patent number: 7651957
    Abstract: The invention relates to a structure for a semiconductor arrangement. A resist structure for supporting deposition of a solution containing a semiconductor is directly or through intervening layers coupled to a substrate. The resist structure comprises a depression (301) for depositing of the solution containing the semiconductor (309) and a trough (305) aligning at least part of an edge of the depression (309) and separated from the depression (309) by a protrusion (307). The trough (305) preferably surrounds the depression (309). The trough provides a pinning effect on the solution containing the semiconductor thereby improving the wettability and accordingly allowing for increased volume of semiconductor to be applied to a given area.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: January 26, 2010
    Assignee: Polymer Vision Limited
    Inventors: Paulus Cornelis Duineveld, Gerwin Hermanus Gelinck
  • Publication number: 20080311751
    Abstract: A method for etching a layer that is to be removed on a substrate, in which a Si1-xGex layer is the layer to be removed, this layer being removed, at least in areas, in gas phase etching with the aid of an etching gas, in particular ClF3. The etching behavior of the Si1-xGex layer can be controlled via the Ge portion in the Si1-xGex layer. The etching method is particularly well-suited for manufacturing self-supporting structures in a micromechanical sensor and for manufacturing such self-supporting structures in a closed hollow space, because the Si1-xGex layer, as a sacrificial layer or filling layer, is etched highly selectively relative to silicon.
    Type: Application
    Filed: July 1, 2005
    Publication date: December 18, 2008
    Inventors: Franz Laermer, Silvia Kronmueller, Tino Fuchs, Christina Leinenbach
  • Publication number: 20080217769
    Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.
    Type: Application
    Filed: January 30, 2008
    Publication date: September 11, 2008
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Yasuyuki Yanase, Yoshio Okayama, Kiyoshi Shibata, Yasunori Inoue, Hideki Mizuhara, Ryosuke Usui, Tetsuya Yamamoto, Masurao Yoshii
  • Patent number: 7410900
    Abstract: This invention relates to photosensitive organometallic compounds which are used in the production of metal deposits. In particular, this invention relates to photosensitive organometallic compounds such as bis-(perfluoropropyl)-1,5-cyclooctadiene platinum (II) (i.e. (C3F7)2PtC8H12) which on exposure to UV radiation and then a reduction process forms a platinum metal deposit such as a substantially continuous thin ‘sheet-like’ film or a substantially narrow line which is capable of electrical conduction.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: August 12, 2008
    Assignee: Ceimig
    Inventor: James Thomson
  • Patent number: 7364939
    Abstract: In order to provide an active matrix display device in which a thick insulating film is preferably formed around an organic semiconductive film of a thin film luminescent device without damaging the thin film luminescent device, the active matrix display device is provided with a bank layer (bank) along a data line (sig) and a scanning line (gate) to suppress formation of parasitic capacitance in the data line (sig), in which the bank layer (bank) surrounds a region that forms the organic semiconductive film of the thin film luminescent device by an ink-jet process. The bank layer (bank) includes a lower insulating layer formed of a thick organic material and an upper insulating layer of an organic material which is deposited on the lower insulating layer and has a smaller thickness so as to avoid contact of the organic semiconductive film with the upper insulating layer.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: April 29, 2008
    Assignee: Seiko Epson Corporation
    Inventor: Ichio Yudasaka
  • Patent number: 7332369
    Abstract: A method for forming an organic electronic device, which method comprises the steps of: a) forming a negative image of a desired pattern on a substrate or device layer with a lift-off ink; b) coating a first device layer to be patterned on top of the negative image; c) coating one or more further device layers to be patterned on top of the first device layer to be patterned; and d) removing the lift-off ink and unwanted portions of the device layers above it, thereby leaving the desired pattern of device layers. The method allows the formation of a device structure wherein the device layers to be patterned are self-aligned. The method enables a multiplicity of layers to be patterned in a single set of printing and lift-off steps using one pattern which ensures the excellent vertical alignment of edges, which would be difficult to achieve by direct printing. Horizontal alignment can also be achieved. The size of the device features can be reduced below the actual printing resolution.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: February 19, 2008
    Assignee: Merck Patent GmbH
    Inventors: Janos Veres, Simon Dominic Ogier, Stephen George Yeates