Nitriding Of Silicon-containing Layer (epo) Patents (Class 257/E21.302)
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Patent number: 9018109Abstract: A thin film transistor in which deterioration at initial operation is not likely to be caused and a manufacturing method thereof. A transistor which includes a gate insulating layer at least whose uppermost surface is a silicon nitride layer, a semiconductor layer over the gate insulating layer, and a buffer layer over the semiconductor layer and in which the concentration of nitrogen in the vicinity of an interface between the semiconductor layer and the gate insulating layer, which is in the semiconductor layer is lower than that of the buffer layer and other parts of the semiconductor layer. Such a thin film transistor can be manufactured by exposing the gate insulating layer to an air atmosphere and performing plasma treatment on the gate insulating layer before the semiconductor layer is formed.Type: GrantFiled: March 2, 2010Date of Patent: April 28, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hidekazu Miyairi, Erika Kato, Kunihiko Suzuki
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Patent number: 8895455Abstract: To form an insulating film with extremely low concentration of impurities such as carbon, hydrogen, nitrogen, chlorine, etc in a film. There are provided the steps of forming a specific element-containing layer on a substrate by supplying source gas containing a specific element into a processing container in which the substrate is accommodated; changing the specific element-containing layer into a nitride layer, by activating and supplying gas containing nitrogen into the processing container; and changing the nitride layer into an oxide layer or an oxynitride layer, by activating and supplying gas containing oxygen into the processing container; with this cycle set as one cycle and performed for at least one or more times.Type: GrantFiled: November 7, 2013Date of Patent: November 25, 2014Assignee: Hitachi Kokusai Electric Inc.Inventors: Naonori Akae, Yoshiro Hirose
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Patent number: 8614152Abstract: A method for forming a gate structure includes the following steps. A substrate is provided. A silicon oxide layer is formed on the substrate. A decoupled plasma-nitridation process is applied to the silicon oxide layer so as to form a silicon oxynitride layer. A first polysilicon layer is formed on the silicon oxynitride layer. A thermal process is applied to the silicon oxynitride layer having the first polysilicon layer. After the thermal process, a second polysilicon layer is formed on the first polysilicon layer. The first polysilicon layer can protect the gate dielectric layer during the thermal process. The nitrogen atoms inside the gate dielectric layer do not lose out of the gate dielectric layer. Thus, the out-gassing phenomenon can be avoided, and a dielectric constant of the gate dielectric layer can not be changed, thereby increasing the reliability of the gate structure.Type: GrantFiled: May 25, 2011Date of Patent: December 24, 2013Assignee: United Microelectronics Corp.Inventors: Chien-Liang Lin, Gin-Chen Huang, Ying-Wei Yen, Yu-Ren Wang
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Patent number: 8609551Abstract: To form an insulating film with extremely low concentration of impurities such as carbon, hydrogen, nitrogen, chlorine, etc in a film. There are provided the steps of forming a specific element-containing layer on a substrate by supplying source gas containing a specific element into a processing container in which the substrate is accommodated; changing the specific element-containing layer into a nitride layer, by activating and supplying gas containing nitrogen into the processing container; and changing the nitride layer into an oxide layer or an oxynitride layer, by activating and supplying gas containing oxygen into the processing container; with this cycle set as one cycle and performed for at least one or more times.Type: GrantFiled: December 22, 2008Date of Patent: December 17, 2013Assignee: Hitachi Kokusai Electric Inc.Inventors: Naonori Akae, Yoshiro Hirose
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Patent number: 8471994Abstract: A liquid crystal display device including first and second substrates, with a liquid crystal layer sealed therebetween; and first and second electrodes formed, respectively, on the first and second substrates. A first molecule orientation film is formed on the first substrate so as to cover the first electrode and a second molecule orientation film formed on the second substrate so as to cover the second electrode. A polarizer with a light absorption axis P is provided outside of the first substrate, and an analyzer with a light absorption axis A is provided outside of the second substrate. The light absorption axis A crosses the light absorption axis P. A plurality of micro structures are associated with at least one of the first and second electrodes, wherein the micro structures are obliquely arranged with respect to the light absorption axis P and the light absorption axis A.Type: GrantFiled: March 18, 2011Date of Patent: June 25, 2013Assignee: Sharp Kabushiki KaishaInventors: Shingo Kataoka, Arihiro Takeda, Takahiro Sasaki, Tsutomu Seino, Yoshio Koike, Hidefumi Yoshida, Yuichi Inoue, Kazutaka Hanaoka, Seiji Tanuma, Takatoshi Mayama, Kimiaki Nakamura, Hideo Chida, Seiji Doi, Tetsuya Fujikawa, Takashi Takagi, Hiroyasu Inoue
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Patent number: 8440526Abstract: A method of fabricating a memory is provided. A substrate including a memory region and a periphery region is provided. A plurality of first gates is formed in the memory region and a plurality of first openings is formed between the first gates. A nitride layer is formed on the substrate in the memory region, and the nitride layer covers the first gates and the first openings. An oxide layer is formed on the substrate in the periphery region. A nitridization process is performed to nitridize the oxide layer into a nitridized oxide layer. A conductive layer is formed on the substrate, and the conductive layer includes a cover layer disposed on the substrate in the memory region and a plurality of second gates disposed on the substrate in the periphery region. The cover layer covers the nitride layer and fills the first openings.Type: GrantFiled: September 23, 2011Date of Patent: May 14, 2013Assignee: Winbound Electronics Corp.Inventors: Hsiu-Han Liao, Lu-Ping Chiang
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Patent number: 8362596Abstract: A dielectric capping layer having a dielectric constant of less than 4.2 is provided that exhibits a higher mechanical and electrical stability to UV and/or E-Beam radiation as compared to conventional dielectric capping layers. Also, the dielectric capping layer maintains a consistent compressive stress upon post-deposition treatments. The dielectric capping layer includes a tri-layered dielectric material in which at least one of the layers has good oxidation resistance, is resistance to conductive metal diffusion, and exhibits high mechanical stability under at least UV curing. The low k dielectric capping layer also includes nitrogen content layers that contain electron donors and double bond electrons. The low k dielectric capping layer also exhibits a high compressive stress and high modulus and is stable under post-deposition curing treatments, which leads to less film and device cracking and improved device reliability.Type: GrantFiled: July 14, 2009Date of Patent: January 29, 2013Assignee: International Business Machines CorporationInventors: Stephan A. Cohen, Alfred Grill, Thomas J. Haigh, Jr., Xiao H. Liu, Son V. Nguyen, Thomas M. Shaw, Hosadurga Shobha
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Patent number: 8334220Abstract: A method for selectively forming a dielectric layer. An embodiment includes forming a dielectric layer, such as an oxide layer, on a semiconductor substrate, depositing a silicon layer on the dielectric layer, and treating the silicon layer with nitrogen, thereby converting the silicon layer into a silicon nitride layer. This method allows for a protective silicon nitride layer to be formed, while also preventing and/or reducing the nitrogen itself from penetrating far enough to contaminate the substrate. In another embodiment the treating with nitrogen is continued to form not only a silicon nitride, but to also diffuse a small portion of nitrogen into the dielectric layer to nitridized a portion of the dielectric layer. Optionally, an anneal could be performed to repair any damage that has been done by the treatment process.Type: GrantFiled: March 21, 2007Date of Patent: December 18, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chen-Hua Yu
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Patent number: 8304352Abstract: According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.Type: GrantFiled: March 18, 2011Date of Patent: November 6, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Tanaka, Kazuhiro Matsuo, Yoshio Ozawa
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Patent number: 8247331Abstract: A method for forming an insulating film includes a step of preparing a substrate, which is to be processed and has silicon exposed on the surface; a step of performing first nitriding to the silicon exposed on the surface of the substrate, and forming a silicon nitride film having a thickness of 0.2 nm but not more than 1 nm on the surface of the substrate; and a step of performing first heat treatment to the silicon nitride film in N2O atmosphere and forming a silicon nitride film. This method may further include a step of performing second nitriding to the silicon oxynitride film, and furthermore, may include a step of performing second heat treatment to the silicon oxynitride film after the second nitriding.Type: GrantFiled: December 20, 2007Date of Patent: August 21, 2012Assignee: Tokyo Electron LimitedInventors: Minoru Honda, Yoshihiro Sato, Toshio Nakanishi
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Patent number: 8110490Abstract: A method of manufacturing a semiconductor device comprising forming a gate oxide layer over a substrate subjecting the gate oxide layer to a first nitridation process, subjecting the gate oxide layer to a first anneal process after the first nitridation process, subjecting the gate oxide layer to a second nitridation process after the first anneal process, subjecting the gate oxide layer to a second anneal process after the second nitridation process, and forming a gate electrode over the gate oxide.Type: GrantFiled: August 15, 2007Date of Patent: February 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Matt Yeh, Da-Yuan Lee, Chi-Chun Chen, Hun-Jan Tao
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Patent number: 8105959Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a SiO2 layer on a silicon substrate; forming on the SiO2 layer an SiN film having a N/Si composition ratio smaller than the stoichiometric composition ratio of SiN by using the ALD technique; and performing a plasma-nitriding process on the SiN layer at a substrate temperature of 550 degrees C. or below.Type: GrantFiled: April 5, 2007Date of Patent: January 31, 2012Assignee: Elpida Memory, Inc.Inventor: Takuo Ohashi
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Patent number: 8030224Abstract: A method of manufacturing a semiconductor device including a semiconductor layer and a dielectric layer deposited on the semiconductor layer, including: forming the semiconductor layer; performing a surface treatment for removing a residual carbon compound, on a surface of the semiconductor layer formed; forming a dielectric film under a depositing condition corresponding to a surface state after the surface treatment, on at least a part of the surface of the semiconductor layer on which the surface treatment has been performed; and changing a crystalline state of at least a partial region of the semiconductor layer by performing a heat treatment on the semiconductor layer on which the dielectric film has been formed.Type: GrantFiled: May 21, 2010Date of Patent: October 4, 2011Assignee: Furukawa Electric Co., Ltd.Inventors: Hidehiro Taniguchi, Takeshi Namegaya, Etsuji Katayama
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Patent number: 8012777Abstract: A packaging process of a light emitting diode (LED) is provided. First, an LED chip is bonded with a carrier to electrically connect to each other. After that, the carrier is heated to raise the temperature thereof. Next, an encapsulant is formed on the heated carrier by a dispensing process to encapsulate the LED chip, wherein the viscosity of the encapsulant before contacting the carrier is lower than that of the encapsulant after contacting the carrier. Thereafter, the encapsulant is cured.Type: GrantFiled: July 2, 2009Date of Patent: September 6, 2011Assignee: Lextar Electronics Corp.Inventors: Wen-Sung Chang, Cheng-Ta Kuo
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Patent number: 7952675Abstract: A liquid crystal display device including 1st and 2nd substrates. A linearly extending scan electrode and a linearly extending signal electrode are formed on the 1st substrate, wherein the scan electrode extends in a direction crossing an extension direction of the signal electrode. A liquid crystal layer is between the 1st and 2nd substrates, and a pixel electrode is formed on the 1st substrate. The pixel electrode is electrically connected to both the scan and signal electrodes. The pixel electrode is divided into at least two regions such that at least two domains of different liquid crystal orientation directions are defined within a single pixel. A 1st and a 2nd of the at least two regions are not aligned in parallel with either the extension direction of the scan electrode or the extension direction of the signal electrode. The 1st and 2nd regions each include a micro-cutout pattern.Type: GrantFiled: November 11, 2008Date of Patent: May 31, 2011Assignee: Sharp Kabushiki KaishaInventors: Shingo Kataoka, Arihiro Takeda, Takahiro Sasaki, Tsutomu Seino, Yoshio Koike, Hidefumi Yoshida, Yuichi Inoue, Kazutaka Hanaoka, Seiji Tanuma, Takatoshi Mayama, Kimiaki Nakamura, Hideo Chida, Seiji Doi, Tetsuya Fujikawa, Takashi Takagi, Hiroyasu Inoue
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Patent number: 7923336Abstract: A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content.Type: GrantFiled: October 30, 2009Date of Patent: April 12, 2011Assignee: Infineon Technologies AGInventors: Kil-Ho Lee, Chan Lim
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Patent number: 7883981Abstract: Embodiments relate to a flash memory device and a method for manufacturing a flash memory device. According to embodiments, a method may include forming a gate on and/or over a semiconductor substrate on and/or over which a device isolation film may be formed, forming a first spacer including a first oxide pattern and a first nitride pattern on and/or over side walls of the gate, forming a source and drain area on and/or over the semiconductor substrate using the gate and spacer as masks, removing the first nitride pattern of the first spacer, and forming a second spacer including a second oxide film pattern and a second nitride film pattern on and/or over the side walls of the gate by performing an annealing process on and/or over the semiconductor substrate on and/or over which the first oxide film pattern is formed.Type: GrantFiled: December 17, 2008Date of Patent: February 8, 2011Assignee: Dongbu HiTek Co., Ltd.Inventor: Dong-Oog Kim
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Patent number: 7884003Abstract: An electrical device in which an interface layer is disposed between and in contact with a metal and a Si-based semiconductor, the interface layer being of a thickness effective to depin of the Fermi level of the semiconductor while still permitting current to flow between the metal and the semiconductor. The interface layer may include a layer of a passivating material (e.g., made from nitrogen, oxygen, oxynitride, arsenic, hydrogen and/or fluorine) and sometimes also includes a separation layer. In some cases, the interface layer may be a monolayer of a semiconductor passivating material. The interface layer thickness corresponds to a minimum specific contact resistance of less than or equal to 10 ?-?m2 or even less than or equal to 1 ?-?m2 for the electrical device.Type: GrantFiled: August 25, 2008Date of Patent: February 8, 2011Assignee: Acorn Technologies, Inc.Inventors: Daniel E. Grupp, Daniel J. Connelly
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Patent number: 7811945Abstract: A selective plasma processing method, within a processing chamber of a plasma processing apparatus, acts oxygen-containing plasma on a target object having silicon and a silicon nitride layer to selectively oxidize the silicon with respect to the silicon nitride layer and to form a silicon oxide film. Further, the ratio of a thickness of a silicon oxynitride film formed within the silicon nitride layer to a thickness of the silicon oxide film formed by the oxidization is equal to or smaller than 20%.Type: GrantFiled: March 21, 2008Date of Patent: October 12, 2010Assignee: Tokyo Electron LimitedInventor: Masaru Sasaki
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Patent number: 7799649Abstract: The present invention provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming a silicon oxide masking layer over a substrate in a first active region and a second active region of a semiconductor device, patterning the silicon oxide masking layer to expose the substrate in the first active region. The method further includes forming a layer of dielectric material over the substrate in the first active region, the patterned silicon oxide masking layer protecting the substrate from the layer of dielectric material in the second active region.Type: GrantFiled: April 13, 2006Date of Patent: September 21, 2010Assignee: Texas Instruments IncorporatedInventors: Hiroaki Niimi, Reima Tapani Laaksonen
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Patent number: 7749919Abstract: A semiconductor device includes: a semiconductor substrate; a source region and a drain region formed at a distance from each other in the semiconductor substrate; a first insulating film formed on a portion of the semiconductor substrate, the portion being located between the source region and the drain region; a charge storage film formed on the first insulating film; a second insulating film formed above the charge storage film and made of a high-permittivity material; a control gate electrode formed above the second insulating film; and a silicon nitride layer including nitrogen atoms having three-coordinate nitrogen bonds, at least one of second-nearest neighbor atoms of the nitrogen atoms being a nitrogen atom. At least one of the charge storage film and the control gate electrode contains silicon, the silicon nitride layer is located between the second insulating film and the at least one of the charge storage film and the control gate electrode.Type: GrantFiled: September 6, 2007Date of Patent: July 6, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kiwamu Sakuma, Daisuke Matsushita, Koichi Kato, Yasushi Nakasaki, Izumi Hirano, Kouichi Muraoka, Yuichiro Mitani, Shigeto Fukatsu, Toshihide Ito
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Patent number: 7723173Abstract: A method for preventing oxidation in a high-k dielectric/metal gate stack in the manufacture of an integrated circuit device is disclosed. In a detailed embodiment, a PMOS region stack has nitrided hafnium silicide, tungsten, tantalum nitride and polysilicon layers. An NMOS region stack has nitrided hafnium silicide, tungsten silicide, tantalum nitride and polysilicon layers. A thin polysilicon layer deposited over the stacks is converted to an oxide using a low temperature ultraviolet ozone oxidation process or a plasma nitridation using decoupled plasma nitridation or NH3 annealing. The oxide provides a coating over the top and sides of the stacks to protect metal and interfaces from oxidation.Type: GrantFiled: March 9, 2009Date of Patent: May 25, 2010Assignee: Texas Instruments IncorporatedInventors: Ajith Varghese, James J. Chambers
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Patent number: 7662730Abstract: A method for fabricating an ultra-high tensile-stressed nitride film is disclosed. A PECVD process is first performed to deposit a transitional silicon nitride film over a substrate. The transitional silicon nitride film has a first concentration of hydrogen atoms. The transitional silicon nitride film is subjected to UV curing process for reducing the first concentration of hydrogen atoms to a second concentration of hydrogen atoms.Type: GrantFiled: November 24, 2005Date of Patent: February 16, 2010Assignee: United Microelectronics Corp.Inventors: Neng-Kuo Chen, Teng-Chun Tsai, Chien-Chung Huang, Tsai-Fu Chen, Wen-Han Hung
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Patent number: 7638396Abstract: A method for fabricating a semiconductor device comprises providing a silicon-containing substrate with first, second, and third regions. First, second, and third gate stacks respectively overlie a portion of the silicon-containing substrate in the first, second, and third regions. A spacer is formed on opposing sidewalls of each of the first, second, and third gate stacks, the spacer overlying a portion of the silicon-containing substrate in the first, second, and third regions, respectively. A source/drain region is formed in a portion of the silicon-containing substrate in the first, second, and third regions, with the source/drain region adjacent to the first, second, and third gate stacks, respectively. The first, second, and third gate stacks have first, second, and third gate dielectric layers of various thicknesses and at least one thereof with a relatively thin thickness is treated by NH3-plasma, having a nitrogen-concentration of about 1013˜1021 atoms/cm2 therein.Type: GrantFiled: March 20, 2007Date of Patent: December 29, 2009Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Da-Yuan Lee, Chi-Chun Chen, Shih-Chang Chen
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Patent number: 7622402Abstract: The surface of an insulating film disposed on an electronic device substrate is irradiated with plasma based on a process gas comprising at least an oxygen atom-containing gas, to thereby form an underlying film at the interface between the insulating film and the electronic device substrate. A good underlying film is provided at the interface between the insulating film and the electronic device substrate, so that the thus formed underlying film can improve the property of the insulating film.Type: GrantFiled: March 31, 2003Date of Patent: November 24, 2009Assignee: Tokyo Electron LimitedInventors: Takuya Sugawara, Yoshihide Tada, Genji Nakamura, Shigenori Ozaki, Toshio Nakanishi, Masaru Sasaki, Seiji Matsuyama, Kazuhide Hasebe, Shigeru Nakajima, Tomonori Fujiwara
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Patent number: 7615500Abstract: A method for depositing a film includes: (a) processing a wafer, including forming a high dielectric constant film on a first wafer; and achieving nitridation of the high dielectric constant film formed on the first wafer; and (b) performing coating process including forming a high dielectric constant film on a second wafer; and achieving nitridation of the high dielectric constant film formed on the second wafer. The processing the wafer and the performing the coating process are carried out in the same reaction chamber. The coating process is carried out before the processing the wafer.Type: GrantFiled: March 9, 2007Date of Patent: November 10, 2009Assignees: NEC Electronics Corporation, NEC CorporationInventors: Kensuke Takano, Ichiro Yamamoto, Koji Watanabe
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Publication number: 20090269923Abstract: A method and apparatus for processing a substrate is provided. The method of processing a substrate includes providing a substrate comprising a conductive material, performing a pre-treatment process on the conductive material, flowing a silicon based compound on the conductive material to form a silicide layer, performing a post treatment process on the silicide layer, and depositing a barrier dielectric layer on the substrate.Type: ApplicationFiled: April 25, 2008Publication date: October 29, 2009Inventors: Sang M. Lee, Yong-Won Lee, Meiyee Shek, Li-Qun Xia, Derek R. Witty
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Patent number: 7605008Abstract: A method and apparatus for igniting a gas mixture into plasma using capacitive coupling techniques, shielding the plasma and other contents of the plasma reactor from the capacitively-coupled electric field, and maintaining the plasma using inductive coupling are provided. For some embodiments, the amount of capacitive coupling may be controlled after ignition of the plasma. Such techniques are employed in an effort to prevent damage to the surface of a substrate from excessive ion bombardment caused by the highly energized ions and electrons accelerated towards and perpendicular to the substrate surface by the electric field of capacitively-coupled plasma.Type: GrantFiled: April 2, 2007Date of Patent: October 20, 2009Assignee: Applied Materials, Inc.Inventors: Thai Cheng Chua, James P. Cruse, Cory Czarnik
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Patent number: 7560396Abstract: An electronic device material comprising at least an electronic device substrate and a silicon oxynitride film disposed on the substrate is provided. The silicon oxynitride film is characterized by containing nitrogen atoms in a large amount in the vicinity of the oxynitride film surface when the nitrogen content distribution in the thickness direction of the silicon oxynitride film is examined by SIMS (secondary ion mass spectrometry) analysis. By virtue of this constitution, an electronic device material comprising an oxynitride film having an excellent effect of preventing penetration of boron and having excellent gate leak properties can be obtained.Type: GrantFiled: March 31, 2003Date of Patent: July 14, 2009Assignee: Tokyo Electron LimitedInventors: Takuya Sugawara, Shigenori Ozaki, Masaru Sasaki
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Publication number: 20090149032Abstract: The present invention suppresses metallic contamination in a processing chamber and a breakage of a quartz member, while suppressing decrease in film formation rate in a thin film formation process immediately after dry cleaning of the inside of the processing chamber, and enhances the operation rate of a apparatus. The method according to the invention includes the steps of: removing the thin film on the inside of the processing chamber by supplying a fluorine gas solely or a fluorine gas diluted by an inert gas solely, as the cleaning gas, to the inside of the processing chamber heated to a first temperature; and removing an adhered material remaining on the inside of the processing chamber after removing the thin film by supplying a fluorine gas solely or a fluorine gas diluted by an inert gas solely, as the cleaning gas, to the inside of the processing chamber heated to a second temperature.Type: ApplicationFiled: December 2, 2008Publication date: June 11, 2009Applicant: HITACHI KOKUSAI ELECTRIC INC.Inventors: Kenji Kameda, Jie Wang, Yuji Urano
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Patent number: 7534732Abstract: Cu interconnects are formed with composite capping layers for reduced electromigration, improved adhesion between Cu and the capping layer, and reduced charge loss in associated non-volatile transistors. Embodiments include depositing a first relatively thin silicon nitride layer having a relatively high concentration of Si—H bonds on the upper surface of a layer of Cu for improved adhesion and reduced electromigration, and depositing a second relatively thick silicon nitride layer having a relatively low concentration of Si—H bonds on the first silicon nitride layer for reduced charge loss.Type: GrantFiled: February 17, 2006Date of Patent: May 19, 2009Assignees: Spansion LLC, Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Erik Wilson, Hieu Pham, Robert Huertas, Lu You, Hirokazu Tokuno, Alexander Nickel, Minh Tran
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Patent number: 7507652Abstract: Some methods that are provided form a composite dielectric structure on a substrate. A first dielectric layer that includes metal and oxygen is formed on a substrate. A preliminary dielectric layer that includes silicon is formed on the first dielectric layer. A plasma nitriding treatment is performed on the preliminary dielectric layer to change it into a second dielectric layer. The composite dielectric structure includes the second dielectric layer and the first dielectric layer. Other methods form a semiconductor device that includes the composite dielectric structure.Type: GrantFiled: July 7, 2005Date of Patent: March 24, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hag-Ju Cho, Yu-Gyun Shin
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Patent number: 7494935Abstract: A method for forming a fine pattern of a semiconductor device includes forming a first photoresist film pattern over a semiconductor substrate including an underlying layer, exposing the first photoresist film pattern to generate an acid from the first photoresist film pattern, bleaching the first photoresist film pattern, and forming a second photoresist film pattern between the first photoresist patterns.Type: GrantFiled: February 26, 2007Date of Patent: February 24, 2009Assignee: Hynix Semiconductor Inc.Inventors: Jae Chang Jung, Seung Chan Moon, Cheol Kyu Bok, Myoung Ja Min, Keun Do Ban, Hee Youl Lim
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Patent number: 7491652Abstract: A process for manufacturing semiconductor devices in an in-line processing includes the steps of: forming a silicon nitride film on a semiconductor wafer by nitrization in a reactor chamber having an inner pressure at a specific pressure; reducing the inner pressure from the specific pressure; raising the inner pressure up to the specific pressure; replacing the semiconductor wafer with another semiconductor wafer; and forming a nitride film on the another semiconductor wafer at the specific pressure.Type: GrantFiled: June 26, 2006Date of Patent: February 17, 2009Assignee: Elpida Memory, Inc.Inventors: Naonori Fujiwara, Hiroyuki Kitamura
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Patent number: 7486366Abstract: In a liquid crystal display device, liquid crystal molecules are oriented in a vertical direction to the first substrate and the second substrate by the first molecule orientation film and the second molecule orientation film, respectively, in a non-driving state. A structural pattern is formed so as to extend in a first direction parallel to a surface of the liquid crystal layer and so as to form, in a driving state, an electric field periodically changing in a second direction that is parallel to the liquid crystal layer and vertical to the first direction. The liquid crystal molecules substantially tilt in the first direction in the driving state.Type: GrantFiled: October 2, 2006Date of Patent: February 3, 2009Assignee: Sharp Kabushiki KaishaInventors: Shingo Kataoka, Arihiro Takeda, Takahiro Sasaki, Tsutomu Seino, Yoshio Koike, Hidefumi Yoshida, Yuichi Inoue, Kazutaka Hanaoka, Seiji Tanuma, Takatoshi Mayama, Kimiaki Nakamura, Hideo Chida
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Patent number: 7439121Abstract: In a film formation method of a semiconductor device including a plurality of silicon-based transistors or capacitors, there exist hydrogen at least in a part of the silicon surface in advance, and the film formation method removes the hydrogen by exposing the silicon surface to a first inert gas plasma. Thereafter a silicon compound layer is formed on the surface of the silicon gas by generating plasma while using a mixed gas of a second inert gas and one or more gaseous molecules, such that there is formed a silicon compound layer containing at least a pat of the elements constituting the gaseous molecules, on the surface of the silicon gas.Type: GrantFiled: December 27, 2001Date of Patent: October 21, 2008Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Masaki Hirayama, Yasuyuki Shirai
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Patent number: 7427572Abstract: A method for forming a silicon nitride film first deposits a silicon nitride film on a target substrate by CVD in a process field within a reaction container. This step is arranged to supply a first process gas containing a silane family gas and a second process gas containing a nitriding gas to the process field, and set the process field at a first temperature and a first pressure, for a first time period. The method then nitrides a surface of the silicon nitride film in the process field. This step is arranged to supply a surface-treatment gas containing a nitriding gas to the process field without supplying the first process gas, and set the process field at a second temperature and a second pressure, for a second time period shorter than the first time period.Type: GrantFiled: July 22, 2005Date of Patent: September 23, 2008Assignee: Tokyo Electron LimitedInventors: Kazuhide Hasebe, Mitsuhiro Okada
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Patent number: 7408225Abstract: A thin-film formation apparatus possesses a reaction chamber to be evacuated, a placing portion on which a substrate is placed inside the reaction chamber, a gas-dispersion guide installed over the placing portion for supplying a gas onto a substrate surface, a gas-supply port for introducing the gas into the gas-dispersion guide, a gas-dispersion plate disposed on the side of the substrate of the gas-dispersion guide and having multiple gas-discharge pores, a first exhaust port for exhausting, downstream of the gas-dispersion plate, the gas supplied onto the substrate surface from the gas-dispersion plate, and a second exhaust port for exhausting, upstream of the gas-dispersion plate, a gas inside the gas-dispersion guide via a space between the gas-dispersion guide and the gas-dispersion plate.Type: GrantFiled: October 7, 2004Date of Patent: August 5, 2008Assignee: ASM Japan K.K.Inventors: Hiroshi Shinriki, Baiei Kawano, Akira Shimizu
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Patent number: 7358612Abstract: A method of manufacturing a semiconductor device contact including forming an insulating layer over a substrate and forming an agglutinating layer over the insulating layer. The agglutinating layer is then exposed to a plasma treatment. A barrier layer is formed over the plasma-treated agglutinating layer, and a conductive layer is formed over the barrier layer.Type: GrantFiled: May 22, 2006Date of Patent: April 15, 2008Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Jian-Shin Tsai, Yu-Hua Chou, Tzo-Hung Luo, Chi-Chan Tseng, Wei Zhang, Jong-Chen Yang
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Patent number: 7348282Abstract: A method of forming a gate insulating layer and nitrogen density measuring method thereof, by which a transistor having enhanced electric characteristics can be fabricated without employing separate ion implantation in a manner of providing parameters for enhancing perfection of the transistor via nitridation measurement. The method includes forming a first oxide layer on a silicon substrate having first to fourth regions defined thereon, patterning the first oxide layer in the first and fourth regions to have a predetermined thickness, and forming a nitride layer on the oxide layer in the third and fourth regions.Type: GrantFiled: December 30, 2004Date of Patent: March 25, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Sang Yong Lee
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Patent number: 7303952Abstract: A method of fabricating polysilicon lines and polysilicon gates, the method of including: providing a substrate; forming a dielectric layer on a top surface of the substrate; forming a polysilicon layer on a top surface of the dielectric layer; implanting the polysilicon layer with N-dopant species, the N-dopant species about contained within the polysilicon layer; implanting the polysilicon layer with a nitrogen containing species, the nitrogen containing species essentially contained within the polysilicon layer.Type: GrantFiled: October 4, 2004Date of Patent: December 4, 2007Assignee: International Business Machines CorporationInventors: James W. Adkisson, John J. Ellis-Monaghan, Glenn C. MacDougall, Dale W. Martin, Kirk D. Peterson, Bruce W. Porth
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Patent number: 7291568Abstract: A method of fabricating a gate dielectric layer, including: providing a substrate; forming a silicon dioxide layer on a top surface of the substrate; performing a plasma nitridation in a reducing atmosphere to convert the silicon dioxide layer into a silicon oxynitride layer. The dielectric layer so formed may be used in the fabrication of MOSFETs.Type: GrantFiled: August 26, 2003Date of Patent: November 6, 2007Assignee: International Business Machines CorporationInventors: Jay S. Burnham, James S. Nakos, James J. Quinlivan, Bernie A. Roque, Jr., Steven M. Shank, Beth A. Ward
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Patent number: 7259071Abstract: A method for making a semiconductor device having a first active region and a second active region includes providing first and second isolation structures defining the first active region on a substrate. The first active region uses a first operational voltage, and the second active region uses a second operational voltage that is different from the first voltage. A nitride layer overlying the first and second active regions is formed. An oxide layer overlying the nitride layer is formed. A first portion of the oxide layer overlying the first active region is removed to expose a first portion of the nitride layer. The exposed first portion of the nitride layer is removed using a wet etch method while leaving a second portion of the nitride layer that is overlying the second active region intact.Type: GrantFiled: October 25, 2004Date of Patent: August 21, 2007Assignee: SilTerra Malaysia Sdn.Bhd.Inventors: Inki Kim, Sang Yeon Kim, Min Paek, Chiew Sin Ping, Wan Gie Lee, Choong Shiau Chien, Zadig Lam, Hitomi Watanabe, Naoto Inoue
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Patent number: 7253108Abstract: The process for forming a film of TiSiN includes the following sequence of steps: deposition of a TiN film at medium temperature, for example, 300-450° C., by thermal decomposition of a metallorganic precursor, for example TDMAT (Tetrakis Dimethylamino Titanium); exposition to a silicon releasing gas, such as silane (SiH4) and dichlorosilane (SiH2Cl2) at 10-90 sccm—standard cube centimeters per minute—for a quite long time, for example, longer than 10 s but less than 90 s, preferably about 40 s; exposition to a H2/N2 plasma at 200-800 sccm, for 10-90 s, preferably about 40 s.Type: GrantFiled: May 25, 2004Date of Patent: August 7, 2007Assignees: STMicroelectronics S.r.l., OVONYX, Inc.Inventor: Romina Zonca
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Patent number: 7214613Abstract: A semiconductor device includes a cross diffusion barrier layer sandwiched between a gate layer and an electrode layer. The gate layer has a first gate portion of doped polysilicon of first conductivity type adjacent to a second gate portion doped polysilicon of second conductivity type. The cross diffusion barrier layer includes a combination of silicon and nitrogen. The cross diffusion barrier layer adequately prevents cross diffusion between the first and second gate portions while causing no substantial increase in the resistance of the gate layer.Type: GrantFiled: August 31, 2004Date of Patent: May 8, 2007Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, Chih-Chen Cho, Robert Burke, Anuradha Iyengar, Eugene R. Gifford
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Publication number: 20070049048Abstract: A semiconductor manufacturing apparatus and process for forming a nitrided dielectric film includes generating a plasma source (44) over a wafer structure (46), where the plasma source (44) includes neutral species (such as nitrogen atoms) and charged species (such as nitrogen ions) that are formed in an inductively coupled plasma reactor. Before the charged species in the plasma (44) can penetrate the wafer structure (46), an electrically connected mesh structure (45, 47) between the plasma source (44) and wafer structure (46) blocks the charged species. In addition or in the alternative, a magnetic field (69) aligned in parallel with the surface of the wafer structure (66) is established in close proximity to the wafer structure (66) in order to trap the charged species. By removing charged species, an improved, narrower nitrogen concentration profile is obtained.Type: ApplicationFiled: August 31, 2005Publication date: March 1, 2007Inventors: Shahid Rauf, Peter Ventzek
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Patent number: 7183143Abstract: A method for forming a nitrided tunnel oxide layer is described. A silicon oxide layer as a tunnel oxide layer is formed on a semiconductor substrate, and a plasma nitridation process is performed to implant nitrogen atoms into the silicon oxide layer. A thermal drive-in process is then performed to diffuse the implanted nitrogen atoms across the silicon oxide layer.Type: GrantFiled: October 27, 2003Date of Patent: February 27, 2007Assignee: Macronix International Co., Ltd.Inventor: Tzu-Yu Wang
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Publication number: 20070004102Abstract: An object is to provide a method for manufacturing a semiconductor device which suppresses an influence on a semiconductor element due to entry of an impurity element, moisture, or the like from outside even in the case of thinning or removing a substrate after forming a semiconductor element over the substrate. A feature is to form an insulating film functioning as a protective film on at least one side of the substrate by performing surface treatment on the substrate, to form a semiconductor element such as a thin film transistor over the insulating film, and to thin the substrate. As the surface treatment, addition of an impurity element or plasma treatment is performed on the substrate. As a means for thinning the substrate, the substrate can be partially removed by performing grinding treatment, polishing treatment, or the like on the other side of the substrate.Type: ApplicationFiled: June 7, 2006Publication date: January 4, 2007Applicant: Semiconductor Energy Laboratory Co., Ltd.Inventors: Koji Dairiki, Naoto Kusumoto, Takuya Tsurume