Abstract: Semiconductors are textured with aqueous solutions containing non-volatile alkoxylated glycols, their ethers and ether acetate derivatives having molecular weights of 170 or greater and flash points of 75° C. or greater. The textured semiconductors can be used in the manufacture of photovoltaic devices.

Abstract: The use of an ammonium hydroxide spike to a hot tetra methyl ammonium hydroxide (TMAH) solution to form an insitu poly oxide decapping step in a polysilicon (poly) etch process, results in a single step rapid poly etch process having uniform etch initiation and a high etch selectivity, that may be used in manufacturing a variety of electronic devices such as integrated circuits (ICs) and micro electro-mechanical (MEM) devices. The etching solution is formed by adding 35% ammonium hydroxide solution to a hot 12.5% TMAH solution at about 70° C. at a rate of 1% by volume, every hour. Such an etch solution and method provides a simple, inexpensive, single step self initiating poly etch that has etch stop ratios of over 200 to 1 over underlying insulator layers and TiN layers.

Abstract: A method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor including wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface. A gate dielectric layer is formed on at least the topside semiconductor surface. A metal including gate electrode material including at least a first metal is deposited on the gate dielectric layer on the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and at least a portion of the backside semiconductor surface. The metal including gate electrode material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed to form substantially first metal free bevel and backside surfaces while protecting the metal gate electrode material on the topside semiconductor surface.

Abstract: A cleaning solution and methods of fabricating semiconductor devices using the same are provided. A cleaning solution used for cleaning a silicon surface and methods of fabricating a semiconductor device using the same are also provided. The cleaning solution may include 0.01 to 1 wt % of fluoric acid, 20 to 50 wt % of oxidizer and 50 to 80 wt % of water. The cleaning solution may further include 1 to 20 wt % of acetic acid. The cleaning solution may be used to clean a silicon surface exposed during fabrication processes of a semiconductor device. The cleaning solution may reduce damage of other material layers (e.g., a tungsten layer or a silicon oxide layer) and enable the silicon surface to be selectively etched.

Abstract: A non-volatile memory device (and method of manufacture) is disclosed and structured to enable a write operation using an ionization impact process in a first portion of the device and a read operation using a tunneling process in a second portion of the device. The non-volatile memory device (1) increases hot carrier injection efficiency, (2) decreases power consumption, and (3) enables voltage and device scaling in the non-volatile memory devices.

Abstract: A method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor including wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface. A gate dielectric layer is formed on at least the topside semiconductor surface. A metal including gate electrode material including at least a first metal is deposited on the gate dielectric layer on the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and at least a portion of the backside semiconductor surface. The metal including gate electrode material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed to form substantially first metal free bevel and backside surfaces while protecting the metal gate electrode material on the topside semiconductor surface.

Abstract: An apparatus for texturing two-sided wafers has a body capable of containing texturing chemistry (i.e., not necessarily containing the chemistry at this time), and a transport mechanism for transporting wafers through the texturing chemistry. The transport mechanism is configured to substantially wet no more than one side of wafers, transported through the body, with texturing chemistry.

Abstract: Interconnect structures including liner layers that are non-planar with at least the adjacent insulating layer and at least one capping layer on conductive features embedded in the insulating layer. The interconnect structure includes an insulating layer of a dielectric material having a top surface and a bottom surface between the top surface and a substrate. An opening, such as a trench, has sidewalls extending from the top surface of the insulating layer toward the bottom surface and is at least partially filled by a conductive feature. A capping layer is disposed on at least a top surface of the conductive feature. A conductive liner layer is disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer has sidewall portions projecting above the top surface of the insulating layer adjacent to the sidewalls of the opening.

Abstract: The invention includes an etchant composition containing isopropyl alcohol and one or more of HF, NH4F and tetramethyl ammonium fluoride (TMAF). The invention encompasses a method of processing a substrate. A substrate is provided which has a first material containing at least one of polysilicon, monocrystalline silicon and amorphous silicon, and a second material. The substrate is exposed to an etch composition which comprises isopropyl alcohol and at least one of HF, NH4F and TMAF. The invention includes a method of processing a semiconductor construction including providing a construction which has a capacitor electrode material and an oxide material along at least a portion of the capacitor electrode material. At least some of the oxide material is removed by isotropic etching utilizing an etchant composition comprising isopropyl alcohol.

Abstract: A method of making the circuitized substrate. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

Abstract: The removing solution containing a cerium (IV) nitrate salt, periodic acid or a hypochlorite can be applied to metals containing copper, silver or palladium and also to metals containing other metals having a relatively large oxidation-reduction potential.

Abstract: A composition for removing an insulation material and related methods of use are disclosed. The composition comprises about 1 to 50 percent by weight of an oxidizing agent, about 0.1 to 35 percent by weight of a fluorine-containing compound, and water. The insulation material comprises at least one of a low-k material and a protection material.

Abstract: A method of forming a metal interconnect for an integrated circuit includes depositing a barrier layer on a dielectric layer having a trench formed therein, depositing an adhesion layer on the barrier layer, depositing a metal layer on the adhesion layer, removing the metal layer using a CMP process until at least a portion of the adhesion layer is exposed, and removing portions of the adhesion layer and the barrier layer sited substantially outside of the trench using a dissolution process. The dissolution process applies an electrolyte solution to those portions of the adhesion layer and the barrier layer sited substantially outside of the trench to dissolve and remove them.

Abstract: A method for cleaning oxide from the interconnects of a semiconductor that are comprised of nickel (Ni) silicide or nickel-silicide alloys where nickel is the primary metallic component is disclosed. The cleaning comprises performing an SC1 cycle, exposing the wafer comprising a NiSi contact to an SC1 solution. This removes oxygen atoms from the silicon oxide of the nickel silicide. Next, a rinse cycle is performed on the wafer to remove the SC1 solution. Finally, an HCl cycle is performed. During this cycle, the wafer comprising an NiSi contact is introduced to an HCl solution, removing oxygen atoms from the nickel oxide of the NiSi. The method of the present invention provides for lower contact resistance of NiSi semiconductor devices, facilitating semiconductor devices that have the benefits of miniaturization allowed by the NiSi technology, and higher performance due to the reduced contact resistance.

Abstract: A method for forming a contact hole, a method for manufacturing a circuit board and a method for manufacturing an electro-optical device that increase the reliability of electrical coupling via a conductive part and prevent wire-breaking due to projections when forming a contact hole in an interlayer film by using a needle, and burying a conductive material in the contact hole is provided.

Abstract: The present invention relates to semiconductor devices, preferably dynamic random access memory (DRAM) cells, each of which contains at least one trench capacitor with a buried isolation collar. The trench capacitor is located in a trench in a semiconductor substrate, and it comprises inner and outer electrodes and a dielectric layer. The buried isolation collar is recessed into a sidewall of the trench and has a substantially uniform thickness. Such a buried isolation collar is preferably formed by oxygen implantation before trench etching.

Abstract: A dual-tank etch method which is suitable for the stripping of a silicon nitride layer from a pad oxide layer provided on a substrate, and etching of the pad oxide layer to a desired target thickness, is disclosed. The method includes providing a first processing tank containing a silicon nitride-stripping chemical; stripping the silicon nitride layer from the pad oxide layer by placing the substrate in the first processing tank; providing a second processing tank containing an oxide-etching chemical; and etching the pad oxide layer to the desired target thickness by placing the substrate in the second processing tank. By carrying out the pad oxide-etching step and the silicon nitride-stripping step in separate processing tanks, accumulation of silicon oxide precipitates in the second processing tank is avoided.

Abstract: A capacitance coupled, transmission line-fed, radio frequency MEMS switch and its fabrication process using photoresist and other low temperature processing steps are described. The achieved switch is disposed in a low cost dielectric housing free of undesired electrical effects on the switch and on the transmission line(s) coupling the switch to an electrical circuit. The dielectric housing is provided with an array of sealable apertures useful for wet, but hydrofluoric acid-free, removal of switch fabrication employed materials and also useful during processing for controlling the operating atmosphere surrounding the switch—e.g. at a pressure above the high vacuum level for enhanced switch damping during operation. Alternative arrangements for sealing an array of dielectric housing apertures are included. Processing details including plan and profile drawing views, specific equipment and materials identifications, temperatures and times are also disclosed.

Abstract: In etching a metal line formed as a dual layer of aluminum alloy and molybdenum, the metal line consisting of the dual layer of aluminum alloy and molybdenum is etched through one-time wet etching by applying the etchant including HNO3, HClO4, a Ferric compound (Fe3+), and a Flouro compound (F?), the process can be reduced and a metal line having a good profile can be formed.

Abstract: Described herein are methods of forming a thin silicon dioxide layer having a thickness of less than eight angstroms on a semiconductor substrate to form the bottom layer of a gate dielectric. A silicon dioxide layer having a thickness of less than eight angstroms may be formed by two different methods. In one method, a sulfuric acid solution is applied to a semiconductor substrate to grow a silicon dioxide layer of less than eight angstroms. The growth of the silicon dioxide layer by the sulfuric acid solution is self-limiting. In another method, a hydrogen peroxide containing solution is applied to a semiconductor substrate for a time sufficient to grow a silicon dioxide layer having a thickness of greater than eight angstroms and then applying an etching solution to etch the silicon dioxide layer down to a thickness of less than eight angstroms.

Abstract: The present invention provides a photoresist stripper including about 5 wt % to about 20 wt % alcohol amine, about 40 wt % to about 70 wt % glycol ether, about 20 wt % to about 40 wt % N-methyl pyrrolidone, and about 0.2 wt % to about 6 wt % chelating agent.

Abstract: A method of making a circuitized substrate. A conductive layer having a substantially planar upper surface is formed on and in direct mechanical contact with an upper surface of a substrate. A portion of the conductive layer is removed to form an interim side wall in the conductive layer. A layer of patternable material is formed on the substantially planar upper surface and on the interim side wall. A portion of the layer of patternable material on the conductive layer is removed to expose the interim side wall. A portion of the substantially planar upper surface is removed to form a side wall in the layer of patternable material. Portions of the interim side wall in the conductive layer are removed to form a second side wall and a bottom wall defined by the upper surface of the substrate. The second side wall is substantially perpendicular to the bottom wall.

Abstract: Systems and methods for molecular self-assembly are provided. The molecular self-assembly receives a substrate that includes one or more regions of dielectric material. A molecularly self-assembled layer is formed on an exposed surface of the dielectric material. The molecularly self-assembled layer includes material(s) having a molecular characteristic and/or a molecular type that includes one or more of a molecular characteristic and/or a molecular type of a head group of molecules of the material, a molecular characteristic and/or a molecular type of a terminal group of molecules of the material, and a molecular characteristic and/or a molecular type of a linking group of molecules of the material. The molecular characteristic(s) and molecular type(s) are selected according to at least one pre-specified property of the molecularly self-assembled layer.

Abstract: Device and method of fabricating device. The device includes a dual damascene line having a metal line and a via, and a redundant liner arranged to divide the metal line. The method includes forming a trench in a metal stripe of a dual damascene line, depositing a barrier layer in the trench, and filling a remainder of the trench with metal.

Abstract: A method is provided for fabricating integrated electronic components. According to the method, an initial structure is produced on the surface of a first substrate. This initial structure incorporates a defined pattern formed from volumes of differentiated materials. At least part of the initial substrate that includes the defined pattern is transferred onto a second substrate, preferably by inverting the first substrate against the second substrate and then removing the first substrate. An additional structure is then produced on the second substrate. This additional structure includes volumes of material placed in correspondence with some of the volumes of differentiated material of the defined pattern. The electronic components thus produced may have a suitable configuration in accordance with technological or geometrical constraints.

Abstract: A method for manufacturing a semiconductor device includes a step of forming a first groove in a first insulating film, forming a conductive film in the first groove, a step of selectively forming a second insulating film on the conductive film and the first insulating film, a step of forming a second groove by removing part of the conductive film using the second insulating film as a mask, the second groove being formed so as to form a connecting portion of the conductive film under the second insulating film and form a first wiring layer by forming the connecting portion with a bottom of the first groove integrally with each other as one unit.

Abstract: A circuitized substrate and a method of making the circuitized substrate is provided. The circuitized substrate includes a substrate having a substantially planar upper surface and a conductive layer positioned on the substantially planar upper surface. The conductive layer includes at least one side wall therein, defining an opening in the conductive layer. The conductive layer includes an end portion spaced from the opening, the end portion forming an acute angle with the substantially planar upper surface of the substrate. The at least one side wall is substantially perpendicular to the substantially planar upper surface of the substrate.

Abstract: The present invention is a method of producing semiconductor devices and an etching liquid with which the titanium nitride film can be removed without thinning of the CoSi layer. A hydrogen peroxide-water mixture is used for removal of the titanium nitride film in the method of producing semiconductor devices by cobalt salicide technology with titanium nitride as the cap film.

Abstract: A method for forming thoroughly deposited shallow trench isolation. A first oxide layer is formed conformally over the surface of a semiconductor substrate and on a trench thereon with an aspect ratio greater than 3. A liquid etching shield is filled in the trench by spin-spraying to cover the oxide layer in the trench. An etchant is then sprayed over the surface of the semiconductor substrate to remove the uncovered oxide layer and expose the surface of the semiconductor substrate. The density of the etchant is less than that of the liquid etching shield. A second oxide layer is deposited in the trench to form isolation without voids or seams.