Abstract: Provided is a method for manufacturing a silicon carbide semiconductor device, in order to obtain a smooth surface of silicon carbide while maintaining a high impurity activation rate, which includes a step of implanting an impurity into a surface layer of a silicon carbide substrate, a step of forming a carbon film on the surface of the silicon carbide substrate, a step of mounting the substrate on a sample stage of a susceptor disposed within the activation heat treatment furnace so that the carbon film and the susceptor are in contact with each other, and a step of performing an activation heat treatment on the silicon carbide substrate using the carbon film as a protective film.

Abstract: A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity in the SiC layer; applying a cap layer on the SiC layer; annealing the cap layer to be transformed a carbon layer; annealing the SiC layer to activate the impurity; and removing the carbon layer. The annealing the SiC layer includes: increasing a temperature of the SiC layer from a second temperature to a first temperature within a first time duration; and decreasing the temperature of the SiC layer from the first temperature to the second temperature within a second time duration. The first temperature is equal to or higher than 1800° C., and the second temperature is lower than 1800° C. The first and second time durations are small.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device comprises a gate electrode on a semiconductor substrate having a device isolation region, a first drain spacer on one side of the gate electrode, a second drain spacer next to the first drain spacer, a first source spacer on an opposite side of the gate electrode and a portion of the semiconductor substrate where a source region is to be formed, a second source spacer on side and top surfaces of the first source spacer, and LDDs adjacent to the first drain spacer and below the first source spacers, wherein the LDD below the first source spacer is thinner than the LDD adjacent to the first drain spacer.

Abstract: A method of fabricating a CMOS transistor includes forming strained channels by re-crystallized amorphous polysilicon with the tensile film or the compressive film during annealing. C or Ge ions are optionally used to form solid-phase epitaxy to amplify the stress in the strained channel. Therefore, the charge carrier mobility in a CMOS transistor is improved.

Abstract: A method is demonstrated to manufacture SOI substrates with high throughput while resources can be effectively used. The present invention is characterized by the feature in which the following process A and process B are repeated. The process A includes irradiation of a surface of a semiconductor wafer with cluster ions to form a separation layer in the semiconductor wafer. The semiconductor wafer and a substrate having an insulating surface are then overlapped with each other and bonded, which is followed by thermal treatment to separate the semiconductor wafer at or around the separation layer. A separation wafer and an SOT substrate which has a crystalline semiconductor layer over the substrate having the insulating surface are simultaneously obtained by the process A. The process B includes treatment of the separation wafer for reusing, which allows the separation wafer to be successively subjected to the process A.

Abstract: The invention relates to a process for manufacturing a multilayered semiconductor wafer comprising a handle wafer (5) and a layer (40) comprising silicon carbide bonded to the handle wafer (5), the process comprising the steps of: a) providing a handle wafer (5), b) providing a donor wafer (1) comprising a donor layer (2) and a remainder (3) of the donor wafer, the donor layer (2) comprising monocrystalline silicon, e) bonding the donor layer (2) of the donor wafer (1) to the handle wafer (5), and f) removing the remainder (3) of the donor wafer in order to expose the donor layer (2) which remains bonded to the handle wafer (5), the process being characterized by further steps of c) implanting carbon ions into the donor layer (2) in order to produce a layer (4) comprising implanted carbon, and d) heat-treating the donor layer (2) comprising the layer (4) comprising implanted carbon in order to form a silicon carbide donor layer (44) in at least part of the donor layer (2).

Abstract: The method for forming wavelike coherent nanostructures by irradiating a surface of a material by a homogeneous flow of ions is disclosed. The rate of coherency is increased by applying preliminary preprocessing steps.

Abstract: Oxide films are deposited under conditions generating a silicon-rich oxide in which silicon nanoclusters form either during deposition or during subsequent annealing. Such deposition conditions include those producing films with optical indices (n) greater than 1.46. The method of the present invention reduces the TID radiation-induced shifts for the oxides.

Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.

Abstract: According to one embodiment, a semiconductor device includes a SiC layer of a first conductivity type, a SiC region of a second conductivity type, and a conductive layer of the second conductivity type. The SiC layer of the first conductivity type has a hexagonal crystal structure. The SiC region of the second conductivity type is formed in a surface of the SiC layer. The conductive layer of the second conductivity type is provided on the SiC region and is in contact with a portion of the SiC region including SiC of a cubic crystal structure.

Abstract: In an atmosphere in which a silicon carbide (SiC) substrate implanted with impurities is annealed to activate the impurities, by setting a partial pressure of H2O to be not larger than 10?2 Pa, preferably not larger than 10?3 Pa, surface irregularity of the silicon carbide (SiC) substrate is controlled to be not greater than 2 nm, more preferably not greater than 1 nm in RMS value.

Abstract: A field-effect transistor that increases the operation speeds of complementary field-effect transistors. Each of an nMOSFET and a pMODFET has a Ge channel and source and drain regions formed of an NiGe layer. The height of Schottky barriers formed at a junction between a channel region and the source region of the nMOSFET and at a junction between the channel region and the drain region of the nMOSFET is changed by very thin high-concentration segregation layers formed by making As atoms, Sb atoms, S atoms or the like segregate at the time of forming the NiGe layer. As a result, Schottky barrier height suitable for the nMOSFET and the pMODFET can be obtained, this being capable of realizing high-speed CMOSFETS.

Abstract: The present invention provides metal precursors for low temperature deposition. The metal precursors include a metal ring compound including at least one metal as one of a plurality of elements forming a ring. Methods of forming a metal thin layer and manufacturing a phase change memory device including use of the metal precursors is also provided.

Abstract: A semiconductor process for improved etch control in which an anisotropic selective etch is used to better control the shape and depth of trenches formed within a semiconductor material. The etchants exhibit preferential etching along at least one of the crystallographic directions, but exhibit an etch rate that is much slower in a second crystallographic direction. As such, one dimension of the etching process is time controlled, a second dimension of the etching process is self-aligned using sidewall spacers of the gate stack, and a third dimension of the etching process is inherently controlled by the selective etch phenomenon of the selective etchant along the second crystallographic direction. A deeper trench is implemented by first forming a lightly doped drain (LDD) region under the gate stack and using the sidewall spacers in combination with the LDD regions to deepen the trenches formed within the semiconductor material.

Abstract: The invention concerns a micro-electronic device comprising a substrate, a first insulating zone and a second insulating zone laying on said substrate, a first active zone comprising at least one layer made of a first semi-conductor crystalline material, resting on said first insulating zone which insulates it from the substrate, at least one second active zone comprising at least one layer in a second semi-conductor crystalline material, laying on said second insulating zone which insulates it from the substrate, said first semi-conductor crystalline material having a different composition from that of the second semi-conductor crystalline material and/or different crystalline orientation from that of the second semi-conductor crystalline material and/or mechanical strains from that of the second semi-conductor crystalline material.

Abstract: A method for generating n-type carriers in a semiconductor is disclosed. The method includes supplying a semiconductor having an atomic radius. Implanting an n-type dopant species into the semiconductor, which n-type dopant species has a dopant atomic radius. Implanting a compensating species into the semiconductor, which compensating species has a compensating atomic radius. Selecting the n-type dopant species and the compensating species in such manner that the size of the semiconductor atomic radius is inbetween the dopant atomic radius and the compensating atomic radius. A further method is disclosed for generating n-type carriers in germanium (Ge). The method includes setting a target concentration for the carriers, implanting a dose of an n-type dopant species into the Ge, and selecting the dose to correspond to a fraction of the target carrier concentration. Thermal annealing the Ge in such manner as to activate the n-type dopant species and to repair a least a portion of the implantation damage.

Abstract: Device structures with a self-aligned damage layer and methods of forming such device structures. The device structure first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate. A third doped region of opposite conductivity type laterally separates the first doped region from the second doped region. A gate structure is disposed on a top surface of the substrate and has a vertically stacked relationship with the third doped region. A first crystalline damage layer is defined within the semiconductor material of the substrate. The first crystalline damage layer has a first plurality of voids surrounded by the semiconductor material of the substrate. The first doped region is disposed vertically between the first crystalline damage layer and the top surface of the substrate. The first crystalline damage layer does not extend laterally into the third doped region.

Abstract: A method of forming a Si strained layer 16 on a Si substrate 10 includes forming a first SiGe buffer layer 12 on the Si substrate 10. Then, the first SiGe buffer layer is implanted with an amorphising implant to render the first SiGe buffer layer amorphous using ion implantation. A second SiGe buffer layer 14 is grown on the first SiGe buffer layer after annealing. This produces a relaxed SiGe layer 12, 14. Then, the strained layer of Si 16 is grown.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: By selectively performing a pre-amorphization implantation process in logic areas and memory areas, the negative effect of the interaction between stressed overlayers and dislocation defects may be avoided or at least significantly reduced in the memory areas, thereby increasing production yield and stability of the memory areas.

Abstract: By embedding a silicon/germanium mixture in a silicon layer of high tensile strain, a moderately high degree of tensile strain may be maintained in the silicon/germanium mixture, thereby enabling increased performance of N-channel transistors on the basis of silicon/germanium material. In other regions, the germanium concentration may be varied to provide different levels of tensile or compressive strain.

Abstract: A method for fabricating a semiconductor device employing a selectivity poly deposition is disclosed. The disclosed method comprises depositing selectivity poly on a gate poly and source/drain regions of the silicon substrate, and forming salicide regions on the gate and active regions from the deposited selectivity poly. Accordingly, the present invention employing selectivity poly deposition can reduce or minimize contact surface resistance and improve the electrical characteristics of the semiconductor device by reducing the surface resistance in a miniature semiconductor device. In addition, because the size of the gate electrode is getting small, the present invention can be used as an essential part of the future generations of nano-scale technology. Moreover, mass semiconductor production systems can promptly employ the present invention with existing equipment.

Abstract: An integrated circuit system that includes: providing a PFET device including a PFET gate and a PFET gate dielectric; forming a source/drain extension from a first epitaxial layer aligned to a first PFET gate sidewall spacer; and forming a source/drain from a second epitaxial layer aligned to a second PFET gate sidewall spacer.

Abstract: Instabilities and related drawbacks that arise when interruptions of a perimetral high voltage ring extension implanted regions (RHV) of a main junction (P_tub 1, (P_tub2, . . . ) of an integrated device must be realized may be effectively prevented. This important result is achieved by an extremely simple expedient: whenever an interruption (I) of the high voltage ring extension must be created, it is not realized straight across it along a common orthogonal direction to the perimetral implanted region, on the contrary, the narrow interruption is defined obliquely or slantingly across the width of the perimetral high voltage ring extension. In case of a straight interruption, the angle of slant (?) may be generally comprises between 30 and 60 degrees and more preferably is 45 degrees or close to it. Naturally, the narrow interruption is created by masking it from dopant implantation when realizing the perimetral high voltage ring extension region.

Abstract: A method of fabricating a semiconductor transistor device is provided. The fabrication method begins by forming a gate structure overlying a layer of semiconductor material, such as silicon. Then, spacers are formed about the sidewalls of the gate structure. Next, ions of an amorphizing species are implanted into the semiconductor material at a tilted angle toward the gate structure. The gate structure and the spacers are used as an ion implantation mask during this step. The ions form amorphized regions in the semiconductor material. Thereafter, the amorphized regions are selectively removed, resulting in corresponding recesses in the semiconductor material. In addition, the recesses are filled with stress inducing semiconductor material, and fabrication of the semiconductor transistor device is completed.

Abstract: An impurity region is formed in a surface of a substrate by exposing the substrate to a plasma generated from a gas containing an impurity in a vacuum chamber. In this process, a plasma doping condition is set with respect to a dose of the impurity to be introduced into the substrate so that a first one of doses in a central portion and in a peripheral portion of the substrate is greater than a second one of the doses during an initial period of doping, with the second dose becoming greater than the first dose thereafter.

Abstract: There are provided a semiconductor device having an overlay measurement mark, and a method of fabricating the same. The semiconductor device includes a scribe line region disposed on a semiconductor substrate. A first main scale layer having a first group of line and space patterns and a second group of line and space patterns is disposed on the scribe line region. Line-shaped second main scale patterns are disposed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are disposed on space regions of the second group of the line and space patterns. In the method, a first main scale layer having a first group of line and space patterns and a second group of line and space patterns is formed on a semiconductor substrate. Line-shaped second main scale patterns are formed on space regions of the first group of the line and space patterns. Line-shaped vernier scale patterns are formed on space regions of the second group of the line and space patterns.

Abstract: A method for manufacturing a semiconductor device includes forming a diffusion layer on a silicon substrate by doping an impurity of a first conductivity type into a region of a second conductivity type opposite to the first conductivity type and performing a heat treatment; implanting nitrogen or fluorine ions into the diffusion layer; and irradiating carbon dioxide gas laser light to the diffusion layer after the implanting.

Abstract: The aim of the invention is to improve the energy yield efficiency of solar cells. According to the invention, the silicon material is doped with one or more different lanthanides such that said material penetrates into a layer approximately 60 nm deep. Photons, whose energy is at least double that of the 1.2 eV silicon material band gap, are thus converted into at least two photons having energy in the region of the silicon band gap, by excitation and recombination of the unpaired 4f electrons of the lanthanides. As a result, additional photons having advantageous energy close to the silicon band gap are provided for electron-hole pair formation.

Abstract: Semiconductor structures having a decreased semiconductor junction capacitance of a semiconductor junction within an active semiconductor layer may be fabricated using an ion implantation and thermal annealing method. The ion implantation and thermal annealing method provides for a plurality of voids located completely within the active semiconductor layer proximate to the semiconductor junction located within the active semiconductor layer, absent stressing of the active semiconductor layer.

Abstract: A method of making a silicon carbide MOSFET is disclosed. The method includes providing a semiconductor device structure, wherein the device structure comprises a silicon carbide semiconductor device layer, an ion implanted well region of a first conductivity type formed in the semiconductor device layer, an ion implanted source region of a second conductivity type formed into the ion implanted well region; providing a mask layer over the semiconductor device layer, the mask layer exposing a portion of the ion implanted source region, then etching through the portion of the ion implanted source region to form a dimple; then implanting ions through the dimple to form a high dopant concentration first conductivity type ion implanted contact region, wherein the ion implanted contact region is deeper than the ion implanted well region; then removing the contact region mask layer and annealing implanted ions.

Abstract: A dislocation region is formed by implanting a light inert species, such as hydrogen, to a specified depth and with a high concentration, and by heat treating the inert species to create “nano” bubbles, which enable a certain mechanical decoupling to underlying device regions, thereby allowing a more efficient creation of strain that is induced by an external stress-generating source. In this way, strain may be created in a channel region of a field effect transistor by, for instance, a stress layer or sidewall spacers formed in the vicinity of the channel region.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes a step of ion-implanting an impurity in a surface of a silicon carbide wafer (1 and 2); a step of forming a carbon protection film (6) of a predetermined thickness over the entire surface of the silicon carbide wafer (1 and 2) having been ion-implanted with the impurity, by a chemical vapor deposition method that deposits a film by pyrolyzing a hydrocarbon gas; and a step of annealing the silicon carbide wafer (1 and 2) having been formed with the carbon protection film (6). Thereby, the carbon protection film (6) can be formed that contains extremely few contaminants, and prevents step bunching from creating on the surface of the silicon carbide wafer (1 and 2) and crystal defects created therein due to unbalanced thermal stress form increasing.

Abstract: After forming a field insulating film 12 on a substrate, sacrificing or gate oxidation films are formed as oxidation films 14a and 14b. An ion implantation layer 18 is formed by one or plurality of implantation process of argon (or fluoride) ion in an element hole 12a using a resist layer 16 as a mask via the oxidation film 14a. When the oxidation films 14a and 14b are used as sacrificing oxidation films, gate oxidation films are formed in the element holes 12a and 12b after removing the resist film 16 and the oxidation films 14a and 14b. When the oxidation films 14a and 14b are used as gate oxidation films, the oxidation films are once thinned by etching and then thickened after removing the resist layer 16. The gate oxidation film 14a is thicker than the gate oxidation film 14b by forming the ion implantation layer 18.

Abstract: A method of forming a semiconductor structure includes providing a substrate having a first feature and a second feature. A mask is formed over the substrate. The mask covers the first feature. An ion implantation process is performed to introduce ions of a non-doping element into the second feature. The mask is adapted to absorb ions impinging on the first feature. After the ion implantation process, an annealing process is performed.

Abstract: A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusion step so that the arsenic is not intentionally driven. Device junction are then diffused into the epitaxially grown layer.

Abstract: A method for manufacturing a SiC semiconductor device includes: forming an impurity layer in a SiC layer; and forming an oxide film on the SiC layer. The forming the impurity layer includes: implanting an impurity in the SiC layer; applying a cap layer on the SiC layer; annealing the cap layer to be transformed a carbon layer; annealing the SiC layer to activate the impurity; and removing the carbon layer. The annealing the SiC layer includes: increasing a temperature of the SiC layer from a second temperature to a first temperature within a first time duration; and decreasing the temperature of the SiC layer from the first temperature to the second temperature within a second time duration. The first temperature is equal to or higher than 1800° C., and the second temperature is lower than 1800° C. The first and second time durations are small.

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. In particular, this invention provides a melt-recrystallization ATR method, for use alone or in combination with non-melt-recrystallization ATR methods, in which selected Si regions bounded by dielectric-filled trenches are induced to undergo an orientation change by the steps of preamorphization, laser-induced melting, and corner-defect-free templated recrystallization from the melt.

Abstract: To make it possible to obtain a sharp impurity profile without presenting a disadvantage such as an increase in parasitic resistance or the like using a laser annealing method to thereby meet sufficiently the requirements for making a semiconductor element finer and more highly integrated. A gate electrode is pattern formed above a semiconductor substrate made of n-type silicon single crystal through a gate insulating film. Thereafter, atoms, Ge+ here, having properties just enough to amorphize single crystal Si are ion implanted (shown by arrows) from oblique directions to the Si surface of the substrate with the gate electrode as a mask to melt and re-crystallize the single crystal Si so as to form amorphous regions which seep into the substrate under the gate electrode. Thereafter B+ ions are implanted into the amorphous regions and laser irradiation is executed thereon.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) is disclosed. The MOSFET includes a semiconductor substrate, a germanium layer formed by implanting germanium (Ge) ions into the semiconductor substrate, an epitaxial layer doped with high concentration impurities over the germanium layer, a gate structure on the epitaxial layer, and source/drain regions with lightly doped drain (LDD) regions in the semiconductor substrate. The germanium layer supplies carriers into the epitaxial layer so that short channel effects are reduced.

Abstract: Instabilities and related drawbacks that arise when interruptions of a perimetral high voltage ring extension implanted regions (RHV) of a main junction (P_tub 1, (P_tub2, . . . ) of an integrated device must be realized may be effectively prevented. This important result is achieved by an extremely simple expedient: whenever an interruption (I) of the high voltage ring extension must be created, it is not realized straight across it along a common orthogonal direction to the perimetral implanted region, on the contrary, the narrow interruption is defined obliquely or slantingly across the width of the perimetral high voltage ring extension. In case of a straight interruption, the angle of slant (?) may be generally comprises between 30 and 60 degrees and more preferably is 45 degrees or close to it. Naturally, the narrow interruption is created by masking it from dopant implantation when realizing the perimetral high voltage ring extension region.

Abstract: A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semiconductor substrate located below both sides of the gate electrode. Insides of the n-type diffused source and drain layers are formed with p-type impurity implanted regions having a lower p-type impurity concentration than the impurity concentration of the n-type diffused source and drain layer.

Abstract: Methods for forming a field effect transistor are disclosed. An illustrated method comprises: forming a gate electrode on a substrate; and forming a nitride layer on at least a part of the gate electrode and the substrate.

Abstract: A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an element from the main surface to the inside of a silicon layer as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer as a semiconductor substrate to form the semiconductor region being aligned with the gate electrode.

Abstract: The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.

Abstract: A semiconductor device is formed by performing an amorphizing ion implantation to implant dopants of a first conductivity type into a semiconductor body. The first ion implantation causes a defect area (e.g., end-of-range defects) within the semiconductor body at a depth. A non-amorphizing implantation implants dopants of the same conductivity type into the semiconductor body. This ion implantation step implants dopants throughout the defect area. The dopants can then be activated by heating the semiconductor body for less than 10 ms, e.g., using a flash anneal or a laser anneal.

Abstract: Described herein are methods of forming a thin silicon dioxide layer having a thickness of less than eight angstroms on a semiconductor substrate to form the bottom layer of a gate dielectric. A silicon dioxide layer having a thickness of less than eight angstroms may be formed by two different methods. In one method, a sulfuric acid solution is applied to a semiconductor substrate to grow a silicon dioxide layer of less than eight angstroms. The growth of the silicon dioxide layer by the sulfuric acid solution is self-limiting. In another method, a hydrogen peroxide containing solution is applied to a semiconductor substrate for a time sufficient to grow a silicon dioxide layer having a thickness of greater than eight angstroms and then applying an etching solution to etch the silicon dioxide layer down to a thickness of less than eight angstroms.

Abstract: Methods and apparatus are disclosed for selectively inducing stress in a semiconductor device, wherein a first region of a substrate is implanted so as to induce stress in a second region. An electrical device is formed at least partially in the second region, wherein the induced stress therein may improve one or more operational characteristics of the device, such as channel region carrier mobility.

Abstract: A method of forming a field effect transistor is provided which includes forming an amorphized semiconductor region having a first depth from a single-crystal semiconductor region and subsequently forming a first gate conductor above a channel portion of the amorphized semiconductor region. A first dopant including at least one of an n-type dopant and a p-type dopant is then implanted to a second depth into portions of the amorphized semiconductor region not masked by the first gate conductor to form source/drain portions adjacent to the channel portion. The substrate is then heated to recrystallize the channel portion and the source/drain portions of the amorphized semiconductor region. After the heating step, at least a part of the recrystallized semiconductor region is locally heated to activate a dopant in at least one of the channel portion and the source/drain portion.

Abstract: In a method of fabricating an integrated silicon-germanium heterobipolar transistor a silicon dioxide layer arranged between a silicon-germanium base layer and a silicon emitter layer is formed by means of Rapid Thermal Processing (RTP) to ensure enhanced component properties of the integrated silicon-germanium heterobipolar transistor.