Abstract: Provided here are methods and manufacturing systems to implant protons into SiC IGBT devices at multiple depths in the drift layer of the SiC IGBT device. Provides are SiC IGBT devices manufactured with process steps including multiple proton implant processes where the SiC IGBT device is irradiated with ion to affect proton implantation into the SiC IGBT device at multiple depths in the drift region to reduced minority carrier lifetime.

Abstract: A method may include providing a substrate, where the substrate includes a first main surface and a second main surface, opposite the first main surface. The second main surface may include a stress compensation layer. The method may include directing ions to the stress compensation layer in an ion implant procedure. The ion implant procedure may include exposing a first region of the stress compensation layer to a first implant process, wherein a second region of the stress compensation layer is not exposed to the first implant process.

Abstract: A method comprises depositing a mask layer on a front-side surface of a wafer, wherein a portion of the wafer has a first resistivity; with the mask layer in place, performing an ion implantation process on a backside surface of the wafer to implant a resistivity reduction impurity into the wafer through the backside surface of the wafer to lower the first resistivity of the portion of the wafer to a second resistivity; after performing the ion implantation process, removing the mask layer from the front-side surface of the wafer; and forming semiconductor devices on the front-side surface of the wafer.

Abstract: A charge-balance power device includes a semiconductor body having a first conductivity type. A trench gate extends in the semiconductor body from a first surface toward a second surface. A body region has a second conductivity type that is opposite the first conductivity type, and the body region faces the first surface of the semiconductor body and extends on a first side and a second side of the trench gate. Source regions having the first conductivity type extend in the body region and face the first surface of the semiconductor body. A drain terminal extends on the second surface of the semiconductor body. The device further comprises a first and a second columnar region having the second conductivity, which extend in the semiconductor body adjacent to the first and second sides of the trench gate, and the first and second columnar regions are spaced apart from the body region and from the drain terminal.

Abstract: A method of producing a structure made of a piezoelectric material, including: a) production of a stack including at least one metal layer and at least one conductive layer on a substrate made of piezoelectric material, wherein at least one electrical contact is established between the conductive layer and a metal element outside the stack; b) an ionic and/or atomic implantation, through the conductive layer and the metal layer; c) transfer of the substrate onto a transfer substrate, followed by fracturing of the transferred piezoelectric substrate, in an embrittlement area.

Abstract: A system and method for providing electrical isolation between closely spaced devices in a high density integrated circuit (IC) are disclosed herein. An integrated circuit (IC) comprising a substrate, a first device, a second device, and a trench in the substrate and a method of fabricating the same are also discussed. The trench is self-aligned between the first and second devices and comprises a first filled portion and a second filled portion. The first fined portion of the trench comprises a dielectric material that forms a buried trench isolation for providing electrical isolation between the first and second devices. The self-aligned placement of the buried trench isolation allows for higher packing density without negatively affecting the operation of closely spaced devices in a high density IC.

Abstract: The disclosed subject matter provides a p-channel metal-oxide-semiconductor (PMOS) and fabrication method thereof. The PMOS transistor is fabricated by a method including forming a dummy gate structure on a semiconductor substrate, forming a source region and a drain region in the semiconductor substrate on both sides of the dummy gate structure, forming an intermediate layer to cover the dummy gate structure and the semiconductor substrate, and forming a multiple-level etching stop layer including at least a first etching stop layer and a second etching stop layer. The fabrication method also includes performing a UV curing process after forming each of the first and second etching stop layers.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed by an annealing or a rapid thermal annealing (RTA) process, thereby establishing a degree overlap between a gate electrode material of a buried gate and a junction.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed by an annealing or a rapid thermal annealing (RTA) process, thereby establishing a degree overlap between a gate electrode material of a buried gate and a junction.

Abstract: A method of forming a stable nickel silicide layer is provided. The method may include forming a nickel silicide layer on a substrate. A fluorine-rich nickel layer is formed over the nickel silicide layer. The fluorine-rich nickel layer is subjected to a process that drives the fluorine in the fluorine-rich nickel layer into the nickel silicide layer thereunder.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which include a gate electrode material in a recess or a buried gate cell structure, a polysilicon material doped with impurities over a sidewall of a recess located over the gate electrode material, and a junction formed by an annealing or a rapid thermal annealing (RTA) process, thereby establishing a degree overlap between a gate electrode material of a buried gate and a junction.

Abstract: After formation of a silicon Fin part on a silicon substrate, a thin film including an impurity atom which becomes a donor or an acceptor is formed so that a thickness of the thin film formed on the surface of an upper flat portion of the silicon Fin part becomes large relative to a thickness of the thin film formed to the surface of side wall portions of the silicon Fin part. A first diagonal ion implantation from a diagonal upper direction to the thin film is performed and subsequently a second diagonal ion implantation is performed from an opposite diagonal upper direction to the thin film. Recoiling of the impurity atom from the inside of the thin film to the inside of the side wall portions and to the inside of the upper flat portion is realized by performing the first and second diagonal ion implantations.

Abstract: A backside illuminated CMOS image sensor comprises an extended photo active region formed over a substrate using a first high energy ion implantation process and an isolation region formed over the substrate using a second high energy ion implantation process. The extended photo active region is enclosed by the isolation region, which has a same depth as the extended photo active region. The extended photo active region helps to increase the number of photons converted into electrons so as to improve quantum efficiency.

Abstract: A semiconductor device includes a p-type well region 3 and an n+ source region 4, both formed selectively in the surface portion of n? drift region 2. A trench 6 is in contact with n+ source region 4 and extends through p-type well region 3 into n? drift region 2. A field plate 8 is formed in trench 6, with a first insulator film 7 being interposed between the trench 6 surface and field plate 8. A gate electrode 10 is formed in trench 6 above field plate 10, with a second insulator film 9 being interposed between the trench 6 surface and gate electrode 10. An n?? lightly doped region 21 in n? drift region 2 crosses under the bottom of trench 6.

Abstract: The present application relates to technology for improving a withstand voltage of a semiconductor device. The semiconductor device includes a termination area that surrounds a cell area. The cell area is provided with a plurality of main trenches. The termination area is provided with one or more termination trenches surrounding the cell area. A termination trench is disposed at an innermost circumference of one or more termination trenches. A body region is disposed on a surface of a drift region. Each main trench reaches the drift region. A gate electrode is provided within each main trench. The termination trench reaches the drift region. Sidewalls and a bottom surface of the termination trench are covered with a insulating layer. A surface of the insulating layer covering the bottom surface of the termination trench is covered with a buried electrode. A gate potential is applied to the buried electrode.

Abstract: A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate.

Abstract: An ion injection simulation method includes: calculating a reinjection dose injected into a substrate and a structure formed on the substrate and reinjected from a side face of the structure; and calculating concentration distribution of impurities injected into the substrate from a distribution function and reinjection conditions of the reinjection dose.

Abstract: Provided is a method for manufacturing a semiconductor device which includes, on a wafer which has a notch, a plurality of transistors parallel with and perpendicular to a notch direction extending between the center of the wafer and the notch, the method including: preparing the wafer having the front surface which has Off angle of at least 2 degrees and at most 2.8 degrees from plane in a direction in which Twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and doping impurities into the front surface of the wafer in a direction perpendicular to the front surface.

Abstract: A novel process for using enriched and highly enriched dopant gases is provided herein that eliminates the problems currently encountered by end-users from being able to realize the process benefits associated with ion implanting such dopant gases. For a given flow rate within a prescribed range, operating at a reduced total power level of the ion source is designed to reduce the ionization efficiency of the enriched dopant gas compared to that of its corresponding non-enriched or lesser enriched dopant gas. The temperature of the source filament is also reduced, thereby mitigating the adverse effects of fluorine etching and ion source shorting when a fluorine-containing enriched dopant gas is utilized. The reduced levels of total power in combination with a lower ionization efficiency and lower ion source temperature can interact synergistically to improve and extend ion source life, while beneficially maintaining a beam current that does not unacceptably deviate from previously qualified levels.

Abstract: Method for the treatment of a semiconductor substrate (2), in which an ion beam (4) is produced from a doping gas and is directed onto the semiconductor substrate (2), characterized in that the doping gas is fed through a plastic hose (6) to a unit (3) for producing an ion beam (4), and is then ionized. The method and the device advantageously permit the supply of the unit 3 for producing an ion beam 4 with a doping gas from customary gas reservoirs 14 such as customary compressed gas cylinders, for example. Voltage flashovers from the deflection elements 5 are effectively prevented by the use of a plastic hose 6. The method and the device thus permit the simple construction of a corresponding ion implantation apparatus in conjunction with possible inexpensive supply thereof with doping gas.

Abstract: A method for manufacturing a semiconductor device includes the steps of: preparing a substrate made of silicon carbide; forming, on one main surface of the substrate, a detection film having a light transmittance different from that of silicon carbide; confirming presence of the substrate by applying light to the detection film; and forming an active region in the substrate whose presence has been confirmed.

Abstract: A global shutter pixel cell includes a serially connected anti-blooming (AB) transistor, storage gate (SG) transistor and transfer (TX) transistor. The serially connected transistors are coupled between a voltage supply and a floating diffusion (FD) region. A terminal of a photodiode (PD) is connected between respective terminals of the AB and the SG transistors; and a terminal of a storage node (SN) diode is connected between respective terminals of the SG and the TX transistors. A portion of the PD region is extended under the SN region, so that the PD region shields the SN region from stray photons. Furthermore, a metallic layer, disposed above the SN region, is extended downwardly toward the SN region, so that the metallic layer shields the SN region from stray photons. Moreover, a top surface of the metallic layer is coated with an anti-reflective layer.

Abstract: Solar cells and other semiconductor devices are fabricated more efficiently and for less cost using an implanted doping fabrication system. A system for implanting a semiconductor substrate includes an ion source (such as a single-species delivery module), an accelerator to generate from the ion source an ion beam having an energy of no more than 150 kV, and a beam director to expose the substrate to the beam. In one embodiment, the ion source is single-species delivery module that includes a single-gas delivery element and a single-ion source. Alternatively, the ion source is a plasma source used to generate a plasma beam. The system is used to fabricate solar cells having lightly doped photo-receptive regions and more highly doped grid lines. This structure reduces the formation of “dead layers” and improves the contact resistance, thereby increasing the efficiency of a solar cell.

Abstract: A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer.

Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current. In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.

Abstract: A method for selective deposition of Si or SiGe on a Si or SiGe surface exploits differences in physico-chemical surface behavior according to a difference in doping of first and second surface regions. By providing at least one first surface region with a Boron doping of a suitable concentration range and exposing the substrate surface to a cleaning and passivating ambient atmosphere in a prebake step at a temperature lower or equal than 800° C., a subsequent deposition step of Si or SiGe will not lead to a layer deposition in the first surface region. This effect is used for selective deposition of Si or SiGe in the second surface region, which is not doped with Boron in the suitable concentration range, or doped with another dopant, or not doped. Several devices are, thus, provided. The method thus saves a usual photolithography sequence required for selective deposition of Si or SiGe in the second surface region according to the prior art.

Abstract: A lateral overflow drain and a channel stop are fabricated using a double mask process. Each lateral overflow drain is formed within a respective channel stop. Due to the use of two mask layers, one edge of each lateral overflow drain is aligned, or substantially aligned, with an edge of a respective channel stop.

Abstract: An ion implantation method includes reciprocally scanning an ion beam, mechanically scanning a wafer in a direction perpendicular to the ion beam scanning direction, implanting ions into the wafer, and generating an ion implantation amount distribution in a wafer surface of an isotropic concentric circle shape for correcting non-uniformity in the wafer surface in other semiconductor manufacturing processes, by controlling a beam scanning speed in the ion beam scanning direction and a wafer scanning speed in the mechanical scanning direction at the same time and independently using the respective control functions defining speed correction amounts.

Abstract: A method of ion implantation comprising: providing a plasma within a plasma region of a chamber; positively biasing a first grid plate, wherein the first grid plate comprises a plurality of apertures; negatively biasing a second grid plate, wherein the second grid plate comprises a plurality of apertures; flowing ions from the plasma in the plasma region through the apertures in the positively-biased first grid plate; flowing at least a portion of the ions that flowed through the apertures in the positively-biased first grid plate through the apertures in the negatively-biased second grid plate; and implanting a substrate with at least a portion of the ions that flowed through the apertures in the negatively-biased second grid plate.

Abstract: A method of manufacturing a semiconductor device which includes forming first and second gate patterns, forming first and second sidewall spacers on sidewalls of the first and second gate patterns respectively, implanting a first impurity into the semiconductor substrate, forming a third sidewall spacer on the first sidewall spacer and a fourth sidewall spacer on the second sidewall spacer in such a manner that the third sidewall spacer is in contact with the fourth sidewall spacer between the first and second gate patterns, implanting a second impurity into the semiconductor substrate, and removing the third and the fourth sidewall spacers.

Abstract: A method of fabricating a semiconductor device having reduced plasma-induced damage includes providing a p-type semiconductor substrate. The p-type semiconductor substrate has a front surface including the semiconductor device and a back surface. The method further includes doping the back surface with an n-type dopant to form an n-type semiconductor region before forming metal interconnections on the front surface. The n-type semiconductor region and the p-type semiconductor substrate form a pn junction. The method also includes forming an insulation layer on an exposed surface of the n-type semiconductor region.

Abstract: Disclosed herein are various methods of forming stressed channel regions on 3D semiconductor devices, such as, for example, FinFET semiconductor devices, through use of epitaxially formed materials. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate, wherein the trenches define at least a portion of a fin for the device, and performing an epitaxial deposition process to form an epitaxially formed stress-inducing material in the trenches.

Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.

Abstract: In order to realize a plasma doping method capable of carrying out a stable low-density doping, exhaustion is carried out with a pump while introducing a predetermined gas into a vacuum chamber from a gas supplying apparatus, the pressure of the vacuum chamber is held at a predetermined pressure and a high frequency power is supplied to a coil from a high frequency power source. After the generation of plasma in the vacuum chamber, the pressure of the vacuum chamber is lowered, and the low-density plasma doping is performed to a substrate placed on a substrate electrode. Moreover, the pressure of the vacuum chamber is gradually lowered, and the high frequency power is gradually increased, thereby the low-density plasma doping is carried out to the substrate placed on the substrate electrode.

Abstract: A method of ion implantation is disclosed. A beam of ions is accelerated to a first energy level. The beam of ions is decelerated from the first energy level to produce a contamination beam of ions via an ion collision process. The ions of the contamination beam are implanted in a substrate to obtain a selected dopant profile in the substrate.

Abstract: A method of ion implantation comprising: providing a plasma within a plasma region of a chamber; positively biasing a first grid plate, wherein the first grid plate comprises a plurality of apertures; negatively biasing a second grid plate, wherein the second grid plate comprises a plurality of apertures; flowing ions from the plasma in the plasma region through the apertures in the positively-biased first grid plate; flowing at least a portion of the ions that flowed through the apertures in the positively-biased first grid plate through the apertures in the negatively-biased second grid plate; and implanting a substrate with at least a portion of the ions that flowed through the apertures in the negatively-biased second grid plate.

Abstract: In plasma doping a non-planar semiconductor device, a substrate having a non-planar semiconductor body formed thereon is obtained. The substrate having the non-planar semiconductor body may be placed into a chamber. A plasma may be formed in the chamber and the plasma may contain dopant ions. A first bias voltage may be generated to implant dopant ions into a region of the non-planar semiconductor body. A second bias voltage may be generated to implant dopant ions into the same region. In one example, the first bias voltage and the second bias voltage may be different.

Abstract: A method and apparatus are disclosed for controlling a semiconductor process temperature. In one embodiment a thermal control device includes a heat source and a housing comprising a vapor chamber coupled to the heat source. The vapor chamber includes an evaporator section and a condenser section. The evaporator section has a first wall associated with the heat source, the first wall having a wick for drawing a working fluid from a lower portion of the vapor chamber to the evaporator section. The condenser section coupled to a cooling element. The vapor chamber is configured to transfer heat from the heat source to the cooling element via continuous evaporation of the working fluid at the evaporator section and condensation of the working fluid at the condenser section. Other embodiments are disclosed and claimed.

Abstract: A method of processing a substrate having horizontal and non-horizontal surfaces is disclosed. The substrate is implanted with particles using an ion implanter. During the ion implant, due to the nature of the implant process, a film may be deposited on the surfaces, wherein the thickness of this film is thicker on the horizontal surfaces. The presences of this film may adversely alter the properties of the substrate. To rectify this, a second process step is performed to remove the film deposited on the horizontal surfaces. In some embodiments, an etching process is used to remove this film. In some embodiments, a material modifying step is used to change the composition of the material comprising the film. This material modifying step may be instead of, or in addition to the etching process.

Abstract: Integrated circuits that include SRAM cells having additional read stacks and methods for their fabrication are provided. In accordance with one embodiment a method for fabricating such an integrated circuit includes forming a plurality of SRAM cells in and on a semiconductor substrate, each of the plurality of SRAM cells including a read pull down transistor and a read pass gate transistor. First conductivity-determining impurity ions are implanted to establish a first threshold voltage in each of the read pull down transistors; and second conductivity-determining impurity ions are implanted to establish a second threshold voltage different than the first threshold voltage in each of the read pass gate transistors.

Abstract: Semiconductor device structures and related fabrication methods are provided. An exemplary method of fabricating a semiconductor device on a doped region of semiconductor material having a first conductivity type involves forming a first region having a second conductivity type within the doped region, forming a body region having the first conductivity type overlying the first region, and forming a drift region having the second conductivity type within the doped region, wherein at least a portion of the drift region abuts at least a portion of the first region. In one embodiment, the dopant concentration of the first region is less than the dopant concentration of the body region and different from the dopant concentration of the drift region.

Abstract: A method of manufacturing a semiconductor device is disclosed. A p-type substrate is doped to form an N-well in a selected portion of a p-type substrate adjacent an anode region of the substrate. A p-type doped region is formed in the anode region of the p-type substrate. The p-type doped region and the N-well form a p-n junction.

Abstract: An integrated circuit includes an NMOS SCR in which a p-type body well of the NMOS transistor provides a base layer for a vertical NPN layer stack. The base layer is formed by implanting p-type dopants using an implant mask which has a cutout mask element over the base area, so as to block the p-type dopants from the base area. The base layer is implanted concurrently with p-type body wells under NMOS transistors in logic components in the integrated circuit. Subsequent anneals cause the p-type dopants to diffuse into the base area, forming a base with a lower doping density that adjacent regions of the body well of the NMOS transistor in the NMOS SCR. The NMOS SCR may have a symmetric transistor, a drain extended transistor, or may be a bidirectional NMOS SCR with a symmetric transistor integrated with a drain extended transistor.

Abstract: An array includes vertically-oriented transistors, rows of access lines, and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The data/sense line has silicon-comprising semiconductor material between the transistors in that column that is conductively-doped n-type with at least one of As and Sb. The conductively-doped semiconductor material of the data/sense line includes a conductivity-neutral dopant between the transistors in that column. Methods are disclosed.

Abstract: A method for manufacturing a silicon carbide semiconductor device includes the step of forming a mask pattern of a silicon oxide film by removing a portion of the silicon oxide film by means of etching employing a gas containing oxygen gas and at least one fluorine compound gas selected from a group consisting of CF4, C2F6, C3F8, and SF6.

Abstract: A semiconductor device includes a semiconductor substrate and at least one integrated circuit formed on a frontside of the semiconductor substrate. A shielding layer is formed on a backside of the semiconductor substrate. The shielding layer includes one or more elements having a high thermal neutron absorption cross section.

Abstract: An Integrated Circuit (IC) and a method of making the same. In one embodiment, the IC includes: a substrate; a first semiconductor layer disposed on the substrate; a shallow trench isolation (STI) extending through the first semiconductor layer to within a portion of the substrate, the STI substantially separating a first n+ region and a second n+ region; and a gate disposed on a portion of the first semiconductor layer and connected to the STI, the gate including: a buried metal oxide (BOX) layer disposed on the first semiconductor layer and connected to the STI; a cap layer disposed on the BOX layer; and a p-type well component disposed within the first semiconductor layer and the substrate, the p-type well component connected to the second n+ region.

Abstract: The present invention relates to a developable bottom antireflective coating (BARC) composition and a pattern forming method using the BARC composition. The BARC composition includes a first polymer having a first carboxylic acid moiety, a hydroxy-containing alicyclic moiety, and a first chromophore moiety; a second polymer having a second carboxylic acid moiety, a hydroxy-containing acyclic moiety, and a second chromophore moiety; a crosslinking agent; and a radiation sensitive acid generator. The first and second chromophore moieties each absorb light at a wavelength from 100 nm to 400 nm. In the patterning forming method, a photoresist layer is formed over a BARC layer of the BARC composition. After exposure, unexposed regions of the photoresist layer and the BARC layer are selectively removed by a developer to form a patterned structure in the photoresist layer. The BARC composition and the pattern forming method are especially useful for implanting levels.

Abstract: A method of reducing current leakage in unused circuits performed during semiconductor fabrication and a semiconductor device or integrated circuit thereby formed. The method involves modifying a characteristic of at least one idle circuit that is unused in a product variant, to inhibit the circuit and reduce current leakage therefrom upon powering as well as during operation. The method can substantially increase the Vt (threshold voltage) of all transistors of a given type, such as all N-type transistors or all P-type transistors. The method is also suitable for controlling other transistor parameters, such as transistor channel length, as well as other active elements, such as N-type resistors or P-type resistors, in unused circuits which affect leakage current as well as for other unused circuits, such as a high Vt circuit, a standard Vt circuit, a low Vt circuit, and an SRAM cell Vt circuit.