Active Layer Is Group Iii-v Compound (epo) Patents (Class 257/E21.365)
  • Patent number: 9035319
    Abstract: The present disclosure relates to nitride semiconductor and a fabricating method thereof, and a nitride semiconductor according to an exemplary embodiment of the present disclosure includes a nitride based first and second electrode placed with a distance on a substrate, a nitride based channel layer which connects the first and second electrode, an insulating layer which covers the channel layer, and a third electrode which is formed to cover the insulating layer on the insulating layer.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: May 19, 2015
    Assignee: KYUNGPOOK NATIONAL UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Jung-hee Lee, Ki-sik Im, Dong-seok Kim, Hee-sung Kang, Dong-hyeok Son
  • Patent number: 8652958
    Abstract: A vertical geometry light emitting diode with a strain relieved superlattice layer on a substrate comprising doped AlXInYGa1-X-YN. A first doped layer is on the strain relieved superlattice layer AlXInYGa1-X-YN and the first doped layer has a first conductivity. A multilayer quantum well is on the first doped layer comprising alternating layers quantum wells and barrier layers. The multilayer quantum well terminates with a barrier layer on each side thereof. A second doped layer is on the quantum well wherein the second doped layer comprises AlXInYGa1-X-YN and said second doped layer has a different conductivity than said first doped layer. A contact layer is on the third doped layer and the contact layer has a different conductivity than the third doped layer. A metallic contact is in a vertical geometry orientation.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: February 18, 2014
    Assignee: Nitek, Inc.
    Inventor: Asif Khan
  • Patent number: 8524581
    Abstract: Methods and apparatus for depositing thin films incorporating the use of a surfactant are described. Methods and apparatuses include a deposition process and system comprising multiple isolated processing regions which enables rapid repetition of sub-monolayer deposition of thin films. The use of surfactants allows the deposition of high quality epitaxial films at lower temperatures having low values of surface roughness. The deposition of Group III-V thin films such as GaN is used as an example.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: September 3, 2013
    Assignee: Intermolecular, Inc.
    Inventors: Philip A. Kraus, Boris Borisov, Thai Cheng Chua, Sandeep Nijhawan, Yoga Saripalli
  • Patent number: 8415685
    Abstract: A light-emitting element has a cathode, an anode, a light-emitting portion interposed between the cathode and the anode and having a light-emitting layer that emits light on energization between the cathode and the anode, and a hole-injection layer interposed between and in direct contact with the anode and the light-emitting layer and having a capability of receiving holes, and the hole-injection layer is mainly composed of a benzidine derivative.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: April 9, 2013
    Assignee: Seiko Epson Corporation
    Inventors: Tetsuji Fujita, Hidetoshi Yamamoto, Shinichi Iwata, Koji Yasukawa
  • Patent number: 8252662
    Abstract: A method for manufacturing a plurality light emitting diodes includes providing a gallium nitride containing bulk crystalline substrate material configured in a non-polar or semi-polar crystallographic orientation, forming an etch stop layer, forming an n-type layer overlying the etch stop layer, forming an active region, a p-type layer, and forming a metallization. The method includes removing a thickness of material from the backside of the bulk gallium nitride containing substrate material. A plurality of individual LED devices are formed from at least a sandwich structure comprising portions of the metallization layer, the p-type layer, active layer, and the n-type layer. The LED devices are joined to a carrier structure.
    Type: Grant
    Filed: March 29, 2010
    Date of Patent: August 28, 2012
    Assignee: Soraa, Inc.
    Inventors: Christiane Poblenz, Mathew C. Schmidt, Daniel F. Feezell, James W. Raring, Rajat Sharma
  • Patent number: 8193016
    Abstract: A semiconductor laser device includes a substrate and a semiconductor layer formed on a surface of the substrate and having a waveguide extending in a first direction parallel to the surface, wherein the waveguide is formed on a region approaching a first side from a center of the semiconductor laser device in a second direction parallel to the surface and intersecting with the first direction, a first region separated from the waveguide on a side opposite to the first side of the waveguide and extending parallel to the first direction and a first recess portion separated from the waveguide on an extension of a facet of the waveguide, intersecting with the first region and extending in the second direction are formed on an upper surface of the semiconductor laser device, and a thickness of the semiconductor layer on the first region is smaller than a thickness of the semiconductor layer on a region other than the first region.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: June 5, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryoji Hiroyama, Daijiro Inoue, Yasuyuki Bessho, Masayuki Hata
  • Patent number: 8173469
    Abstract: Provided is a method for fabricating a light emitting device. The method for fabricating the light emitting device includes forming a buffer layer including a compound semiconductor in which a rare-earth element is doped on a substrate, forming a light emitting structure including a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, which are successively stacked on the buffer layer, forming a first electrode layer on the light emitting structure, removing the substrate, and forming a second electrode layer under the light emitting structure.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: May 8, 2012
    Assignee: LG Innotek Co., Ltd.
    Inventors: Kyung Wook Park, Myung Hoon Jung
  • Patent number: 8124432
    Abstract: In an InGaN-based nitride semiconductor optical device having a long wavelength (440 nm or more) equal to or more than that of blue, the increase of a wavelength is realized while suppressing In (Indium) segregation and deterioration of crystallinity. In the manufacture of an InGaN-based nitride semiconductor optical device having an InGaN-based quantum well active layer including an InGaN well layer and an InGaN barrier layer, a step of growing the InGaN barrier layer includes: a first step of adding hydrogen at 1% or more to a gas atmosphere composed of nitrogen and ammonia and growing a GaN layer in the gas atmosphere; and a second step of growing the InGaN barrier layer in a gas atmosphere composed of nitrogen and ammonia.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: February 28, 2012
    Assignee: Opnext Japan, Inc.
    Inventors: Tomonobu Tsuchiya, Shigehisa Tanaka, Akihisa Terano, Kouji Nakahara
  • Patent number: 7772599
    Abstract: A gallium-nitride-based semiconductor stacked structure includes a low-temperature-deposited buffer layer and an active layer. The low-temperature-deposited buffer layer is composed of a Group III nitride material that has been grown at low temperature and includes a single-crystal layer in an as-grown state, the single-crystal layer being present in the vicinity of a junction area that is in contact with a (0001) (c) plane of a sapphire substrate. The active layer is composed of a gallium-nitride (GaN)-based semiconductor layer that is provided on the low-temperature-deposited buffer layer. The single-crystal layer is composed of a hexagonal AlXGaYN (0.5<X?1, X+Y=1) crystal that contains aluminum in a predominant amount with respect to gallium such that a [2.?1.?1.0.] direction of the AlXGaYN crystal orients along with a [2.?1.?1.0.] direction of the (0001) bottom plane of the sapphire substrate.
    Type: Grant
    Filed: May 25, 2005
    Date of Patent: August 10, 2010
    Assignee: Showa Denko K.K.
    Inventor: Takashi Udagawa
  • Patent number: 7736925
    Abstract: A method of manufacturing a nitride-based semiconductor laser diode that can minimize optical absorption on a cavity mirror plane and improve the surface roughness of the cavity mirror plane is provided. The method includes the steps of: forming on a (0001) GaN (gallium nitride) substrate having at least two masks spaced apart by a distance equal to a laser cavity length in stripes that extend along the <11-20> direction; growing an n-GaN layer on the GaN substrate between the masks so that two (1-100) edges of the n-GaN layer are thicker than the remaining regions thereof; sequentially stacking an n-clad layer, an active layer, and a p-clad layer on the n-GaN layer to form an edge-emitting laser cavity structure in which laser light generated in the active layer passes through a region of the n-clad layer aligned laterally with the active layer and is output; and etching a (1-100) plane of the laser cavity structure to form a cavity mirror plane.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: June 15, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tan Sakong, Youn-joon Sung, Ho-sun Paek
  • Patent number: 7547587
    Abstract: A laminated structure having light-emitting units is formed on a single-crystal wafer. Electrode patterns are formed on the single-crystal wafer opposite the light-emitting units. Dummy patterns are formed on the single-crystal wafer at a location spaced apart from a location opposite the light-emitting units, and offset from a desired cleavage line intersecting the light-emitting units. A scratch is formed on the desired cleavage line. The wafer is cleaved, originating on the scratch, along the cleavage line orientation, in the direction from the dummy pattern, toward the light-emitting units.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: June 16, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hitoshi Nakamura, Hajime Abe, Noriaki Ishio
  • Publication number: 20090023274
    Abstract: Hybrid chemical vapor deposition systems for depositing a semiconductor-containing thin film over a substrate comprise a reaction space, a substrate support member configured to permit movement of a substrate in a longitudinal direction and a plasma-generating apparatus disposed in the reaction space and configured to form plasma-excited species of a vapor phase chemical. The systems further comprise a hot wire unit disposed in the reaction space and configured to heat and decompose a vapor phase chemical. The hot wire unit can be a filament. The systems can further comprise an additional reaction space proximate the reaction space. The additional reaction space can comprise a plasma-generating apparatus configured to form plasma-excited species of a vapor phase chemical and a hot wire unit configured to heat and decompose a vapor phase chemical.
    Type: Application
    Filed: July 7, 2008
    Publication date: January 22, 2009
    Inventors: Xinmin Cao, Xunming Deng, Aarohi Vijh
  • Publication number: 20080108217
    Abstract: Methods and apparatus are provided for ESD protection of integrated passive devices (IPDs). The apparatus comprises one or more IPDs having terminals or other elements potentially exposed to ESD transients coupled by charge leakage resistances having resistance values much larger than the ordinary impedance of the IPDs at the operating frequency of interest. When the IPD is built on a semi-insulating substrate, various elements of the IPD are coupled to the substrate by spaced-apart connections so that the substrate itself provides the high value resistances coupling the elements, but this is not essential. When applied to an IPD RF coupler, the ESD tolerance increased by over 70%. The invented arrangement can also be applied to active devices and integrated circuits and to IPDs with conductive or insulating substrates.
    Type: Application
    Filed: January 10, 2008
    Publication date: May 8, 2008
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Agni Mitra, Darrell Hill, Karthik Rajagopalan, Adolfo Reyes
  • Patent number: 7368309
    Abstract: The present invention relates to nitride semiconductor, and more particularly, to GaN-based nitride semiconductor and fabrication method thereof. The nitride semiconductor according to the present invention comprises a substrate; a GaN-based buffer layer formed in any one of a group of three-layered structure AlyInxGa1?(x+y)N/InxGa1?xN/GaN where 0?x?1 and 0?y?1, two-layered structure InxGa1?xN/GaN where 0?x?1 and superlattice structure of InxGa1?xN/GaN where 0?x?1; and a GaN-based single crystalline layer.
    Type: Grant
    Filed: August 19, 2003
    Date of Patent: May 6, 2008
    Assignee: LG Innotek Co., Ltd.
    Inventor: Suk Hun Lee