Abstract: In a lateral bipolar transistor including an emitter, a base and a collector which are formed in a semiconductor thin film formed on an insulating substrate, the semiconductor thin film is a semiconductor thin film which is crystallized in a predetermined direction. In addition, in a MOS-bipolar hybrid transistor formed in a semiconductor thin film formed on an insulating substrate, the semiconductor thin film is a semiconductor thin film which is crystallized in a predetermined direction.

Abstract: A method of manufacturing an active matrix substrate that enables increased productivity due to a reduction in the number of patterning processes and low generation of particles during the patterning processes. The method includes forming a patterned electrode on a substrate, and covering the first electrode with an insulating film. A mono-crystalline semiconductor layer is then formed on the insulating film by attaching a first layer formed on a surface of a semiconductor wafer to the first insulating film, and peeling off a portion of the semiconductor wafer. The semiconductor layer is then patterned and doped, in part, by utilizing the patterned electrode as a photo mask for light illuminated from a lower side of the substrate. This results in part in mono-crystalline active layers for thin film transistors, which are then configured to form a pixel for an active matrix substrate.

Abstract: A method of manufacturing an active matrix substrate that enables increased productivity due to a reduction in the number of patterning processes and low generation of particles during the patterning processes. The method includes forming a patterned electrode on a substrate, and covering the first electrode with an insulating film. A mono-crystalline semiconductor layer is then formed on the insulating film by attaching a first layer formed on a surface of a semiconductor wafer to the insulating film, and peeling off a portion of the semiconductor wafer. The semiconductor layer is then patterned and doped, in part, by utilizing the patterned electrode as a photo mask for light illuminated from a lower side of the substrate. This results in part in mono-crystalline active layers for thin film transistors, which are then configured to form a pixel for an active matrix substrate.

Abstract: A thin-film transistor (“TFT”) substrate includes an insulating substrate, a gate line and a data line which are insulated from each other, disposed on the insulating substrate and are arranged in a lattice, and a pixel electrode which is electrically connected to the gate line and the data line by a switching device. The data line includes a lower layer which is formed of a transparent electrode, and an upper layer which is disposed directly on the lower layer.

Abstract: A method of forming a thin-film transistor array substrate is provided. A first mask is used to define a source, a drain and a channel on a substrate. A dielectric layer is formed to cover the source, the drain, the channel and the substrate. A second mask is used to define a patterned photoresist and the dielectric layer. A transparent conductive layer is formed to cover the patterned photoresist and the substrate. A lift-off process is performed to remove the patterned photoresist and a portion of the transparent conductive layer disposed on the patterned photoresist. A third mask is used to define a gate disposed on the dielectric layer.

Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.

Abstract: A system and method are disclosed for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter. An active region of a transistor is formed and a silicon nitride sacrificial emitter is formed above the active region of the transistor. Then a physical vapor deposition oxide layer is deposited over the silicon nitride sacrificial emitter using a physical vapor deposition process. The physical vapor deposition oxide layer is then etched away from the side walls of the sacrificial emitter. The sacrificial emitter is then etched away to form an emitter window. Then a polysilicon emitter structure is formed in the emitter window. The self aligned bipolar transistor architecture of the invention is compatible with BiCMOS technology.

Abstract: A method of producing a semiconductor device having a thickness of 90 ?m to 200 ?m and with an electrode on the rear surface, which achieves a high proportion of non-defective devices by optimizing the silicon concentration and thickness of the aluminum-silicon electrode. A surface device structure is formed on a first major surface of a silicon substrate. A buffer layer and a collector layer are formed on the second major surface after grinding to reduce the thickness of the substrate. On the collector layer, a collector electrode is formed including a first layer of an aluminum-silicon film having a thickness of 0.3 ?m to 1.0 ?m and a silicon concentration of 0.5 percent to 2 percent by weight, preferably not more than 1 percent by weight.

Abstract: A method of manufacturing an electronic device including a PNP bipolar transistor comprises forming a collector in a substrate, depositing a base layer and an emitter layer on the substrate, and growing a nitride interface layer on the base layer as a base current modulation means, such that the nitride interface layer is arranged between the base layer and the emitter layer.

Abstract: A method is described for forming a semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide. The emitter region and collector region also may be formed from polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49phase titanium silicide.

Abstract: In some aspects, a method of forming a memory cell is provided that includes (1) forming a first conductor above a substrate; (2) forming a diode above the first conductor; (3) forming a reversible resistance-switching element above the first conductor using a selective deposition process; and (4) forming a second conductor above the diode and the reversible resistance-switching element. Numerous other aspects are provided.

Abstract: A method for manufacturing a semiconductor device includes: an element portion formation step of forming an element portion on a base layer; a delaminating layer formation step of forming a delaminating layer in the base layer; a bonding step of bonding the base layer having the element portion to a substrate; and a separation step of separating and removing a portion of the base layer in the depth direction along the delaminating layer by heating the base layer bonded to the substrate. The method further includes, after the separation step, an ion implantation step of ion-implanting a p-type impurity element in the base layer for adjusting the impurity concentration of a p-type region of the element.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The method includes forming a collector region of a second conductivity type in a semiconductor substrate of a first conductivity type; forming a base region of the first conductivity type in the collector region, and forming an emitter region of the second conductivity type into the base region; forming an emitter in the emitter region, and forming a collector in the collector region; and forming a base in the semiconductor substrate through implanting high concentration impurity ions of the first conductive type into the semiconductor substrate.

Abstract: A bipolar transistor with very high dynamic performance, usable in an integrated circuit. The bipolar transistor has a single-crystal silicon emitter region with a thickness smaller than 50 nm. The base of the bipolar transistor is made of an SiGe alloy.

Abstract: Provided is an image display device comprising, on a TFT substrate: a plurality of gate lines and a plurality of drain lines which intersect with each other; a pixel TFT provided within a pixel which is enclosed by a pair of adjacent gate lines and a pair of adjacent drain lines; a gate driver TFT which is connected to one of the plurality of gate lines to drive the one of the plurality of gate lines, wherein the pixel TFT and the gate driver TFT each include an amorphous semiconductor film as a channel, wherein the pixel TFT has a bottom gate structure, wherein the gate driver TFT has a dual gate structure, and wherein a mobility on a top surface side of the semiconductor film of the gate driver TFT is higher than a mobility on a top surface side of the semiconductor film of the pixel TFT.

Abstract: A method is described for forming a thin film transistor having its current-switching region in polycrystalline semiconductor material which has been crystallized in contact with titanium silicide, titanium silicide-germanide, or titanium germanide. The titanium silicide, titanium silicide-germanide, or titanium germanide is formed having feature size no more than 0.25 micron in the smallest dimension. The small feature size tends to inhibit the phase transformation from C49 to C54 phase titanium silicide. The C49 phase of titanium silicide has a very close lattice match to silicon, and thus provides a crystallization template for the silicon as it forms, allowing formation of large-grain, low-defect silicon. Titanium does not tend to migrate through the silicon during crystallization, limiting the danger of metal contamination. In preferred embodiments, the transistors thus formed may be, for example, field-effect transistors or bipolar junction transistors.

Abstract: The disclosed invention provides a method for the fabrication of a bipolar transistor having a collector region comprised within a semiconductor body separated from an overlying base region by one or more isolation cavities (e.g., air gaps) filled with low permittivity gas. In particular, a multilayer base-collector dielectric film is deposited over the collector region. A base region is formed onto the multilayer dielectric film and is patterned to form one or more base connection regions. The multilayer dielectric film is selectively etched during a plurality of isotropic etch processes to allow for the formation of one or more isolation region between the base connection regions and the collector region, wherein the one or more isolation regions comprise cavities filled with a gas having a low dielectric constant (e.g., air). The resultant bipolar transistor has a reduced base-collector capacitance, thereby allowing for improved frequency properties (e.g., higher maximum frequency operation).

Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

Abstract: An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zone 4a of the collector. The substrate includes a lightly doped lateral zone and a highly doped central zone. The dopant species in the zone of the substrate are electrically inactive.

Abstract: The present invention relates to a semiconductor device comprising a homojunction or a heterojunction with a controlled dopant (concentration) profile and a method of making the same. Accordingly, one aspect of the invention is a method for manufacturing a junction comprising forming a first semiconductor material comprising a first dopant having a first concentration and thereupon; forming a second semiconductor material comprising a second dopant, having a second concentration thereby forming a junction, and depositing by Atomic Layer Epitaxy or Vapor Phase Doping at least a fraction of a monolayer of a precursor suitable to form the second dopant on the first semiconductor material, prior to forming the second semiconductor material, thereby increasing the second concentration of the second dopant at the junction.

Abstract: Disclosed herein is a method for production of a thin-film semiconductor device which includes, a first step to form a gate electrode on a substrate, a second step to form a gate insulating film of silicon oxynitride on the substrate in such a way as to cover the gate electrode, a third step to form a semiconductor thin film on the gate insulating film, and a fourth step to perform heat treatment in an oxygen-containing oxidizing atmosphere for modification through oxygen binding with oxygen-deficient parts in the silicon oxynitride film constituting the gate insulating film.

Abstract: Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

Abstract: The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

Abstract: A manufacturing method of a thin film transistor array substrate incorporating the manufacture of a photo-sensor is provided. In the manufacturing method, a photo-sensing dielectric layer is formed between a transparent conductive layer and a metal electrode for detecting ambient light. Since the transparent conductive layer is adopted as an electrode, the ambient light can pass through the transparent conductive layer and get incident light into the photo-sensing dielectric layer. Therefore, the sensing area of the photo-sensor can be enlarged and the photo-sensing efficiency is improved. In addition, the other side of the photo sensitive dielectric layer may be a metal electrode. The metal electrode can block the backlight from getting incident into the photo-sensing dielectric layer and thus reduce the background noise. A manufacturing method of a liquid crystal display panel adopting the aforementioned thin film transistor array substrate is also provided.

Abstract: Disclosed is a semiconductor device having a driver circuit operable at high speed and a method for manufacturing same. An active matrix liquid crystal display device uses a polysilicon film for its TFT active layer constituting a pixel matrix circuit because of low off current characteristics. On the other hand, a TFT active layer constituting driver circuits and a signal processing circuit uses a poly silicon germanium film because of high speed operation characteristics.

Abstract: The invention provides a bipolar transistor with a reduced collector series resistance integrated in a trench (4, 44) of a standard CMOS shallow trench isolation region. The bipolar transistor includes a collector region (6, 34) manufactured in one fabrication step, therefore having a shorter conductive path with a reduced collector series resistance, improving the high frequency performance of the bipolar transistor. The bipolar transistor further includes a base region (8, 22, 38) with a first part on a selected portion of the collector region (6, 34), which is on the bottom of the trench (4, 44), and an emitter region (10, 24, 39) on a selected portion of the first part of the base region (8, 22, 38). A base contact (11, 26, 51) electrically contacts the base region (8, 22, 38) on a second part of the base region (8, 22, 38), which is on an insulating region (2, 42). The collector region (6, 34) is electrically contacted on top of a protrusion (5, 45) with a collector contact (13, 25, 50).

Abstract: A thin film transistor array substrate including an insulating substrate, a first metallic pattern formed on the insulating substrate, and an insulating film provided on the first metallic pattern. A semiconductor pattern is provided on the insulating film, and a second metallic pattern is provided on the semiconductor pattern. The second metallic pattern is surrounded by the semiconductor pattern.

Abstract: Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of the layer of doped semiconductor material with the dielectric region separating the active region from the reach-through region; and siliciding the reach-through region and a portion of the sub-collector region to form a partially silicided conductive pathway. A semiconductor device made thereby is also provided.

Abstract: It is an object of the present invention to provide a method for forming a layer having functionality including a conductive layer and a colored layer and a flexible substrate having a layer having functionality with a high yield. Further, it is an object of the present invention to provide a method for manufacturing a semiconductor device that is small-sized, thin, and lightweight. After coating a substrate having heat resistance with a silane coupling agent, a layer having functionality is formed. Then, after attaching an adhesive to the layer having functionality, the layer having functionality is peeled from the substrate. Further, after coating a substrate having heat resistance with a silane coupling agent, a layer having functionality is formed. Then, an adhesive is attached to the layer having functionality. Thereafter, the layer having functionality is peeled from the substrate, and a flexible substrate is attached to the layer having functionality.

Abstract: An exemplary method for fabricating a thin film transistor (TFT) array substrate includes: providing an insulating substrate; forming a plurality of gate electrodes and a plurality of reflective patterns on the insulating substrate using a first photo-mask process; forming a gate insulating layer, an amorphous silicon layer, a doped amorphous silicon layer, and a source/drain metal layer on the insulating substrate having the gate electrodes and the reflective patterns; forming a plurality of source electrodes and a plurality of drain electrodes on the doped amorphous silicon layer; depositing a passivation layer on the source electrodes, the drain electrodes and the gate insulating layer; and forming a pixel electrode on the passivation layer.

Abstract: A semiconductor component is formed using the following processes: (a) forming a first dielectric layer over the semiconductor substrate; (b) forming a base electrode for the bipolar transistor over the dielectric layer; (c) forming an oxide nitride structure over the base electrode; (d) forming a first spacer adjacent to the oxide nitride structure and the base electrode; (e) removing a top layer of the oxide nitride structure; (f) removing a first portion of the dielectric layer; (g) forming an epitaxial layer over the semiconductor substrate; (h) forming a second spacer over the epitaxial layer; and (i) forming an emitter electrode over the epitaxial layer and adjacent to the second spacer.

Abstract: A thin film transistor array panel includes an insulating substrate, a gate wire formed on the insulating substrate. A gate insulating layer covers the gate wire. A semiconductor pattern is formed on the gate insulating layer. A data wire having source electrodes, drain electrodes and data lines is formed on the gate insulating layer and the semiconductor pattern. A protective layer is formed on the data wire. Pixel electrodes connected to the drain electrode via contact holes are formed on the protective layer. The gate wire and the data wire are made of Ag alloy containing Ag and an additive including at least one selected from Zn, In, Sn and Cr.

Abstract: A method of growing nitride semiconductor material and particularly a method of growing Indium nitride is disclosed can increase surface flatness of a nitride semiconductor material and decrease density of V-defects therein. Further, the method can increase light emission efficiency of a quantum well or quantum dots of the produced LED as well as greatly increase yield. The method is also applicable to the fabrications of electronic devices made of nitride semiconductor material and diodes of high breakdown voltage for rectification. The method can greatly increase surface flatness of semiconductor material for HBT, thereby increasing quality of the produced semiconductor devices.

Abstract: A method of fabricating a bipolar transistor in a first trench (11) is disclosed wherein only one photolithographic mask is applied which forms a first trench (11) and a second trench (12). A collector region (21) is formed self-aligned in the first trench (11) and the second trench (12). A base region (31) is formed self-aligned on a portion of the collector region (21), which is in the first trench (11). An emitter region (41) is formed self-aligned on a portion of the base region (31). A contact to the collector region (21) is formed in the second trench (12) and a contact to the base region (31) is formed in the first trench (11). The fabrication of the bipolar transistor may be integrated in a standard CMOS process.

Abstract: A method for producing a microelectronic device having one or more Si1?zGez based semiconductor wire(s) (with 0<z?1), including: a) thermal oxidation of at least a portion of a Si1?xGex-based semiconductor layer (with 0<x<1) resting on a support, so as to form at least one Si1?yGey-based semiconductor zone (with 0<y<1 and x<y), b) lateral thermal oxidation of the sides of one or more so-called semiconductor connection blocks from the Si1?yGey-based semiconductor zone and connecting a semiconductor block intended to form a transistor source region and another block intended to form a transistor drain region so as to reduce the semiconductor connection blocks in at least one direction parallel to the main plane of the support and to form one or more Si1?zGez-based semiconductor wire(s) (with 0<y<1 and y<z).

Abstract: A bipolar transistor is formed on a heavily doped silicon substrate (1). An epitaxially grown collector (12) is formed on the substrate (1) and comprises silicon containing germanium at least at the top of the collector (12). An epitaxial base (13) is formed on the collector (12) to have the opposite polarity and also comprises silicon containing germanium at least at the bottom of the base (13). An emitter is formed at the top of the base (13) and comprises polysilicon doped to have the same polarity as the collector (12).

Abstract: A liquid crystal display device includes a gate line and a data line crossing each other to define a pixel region on a substrate, a gate electrode connected to the gate line, a gate insulating layer on the gate electrode, an active layer on the gate insulating layer, source and drain electrodes on the active layer, spaced apart from each other and each having inner sides that face each other, wherein the source electrode is connected to the data line, ohmic contact layers between the active layer and each of the source and drain electrodes, a shielding pattern over the active layer and having outer sides, wherein at least one of the outer sides faces at least one of the inner sides of the source and drain electrodes, and a pixel electrode in the pixel region and connected to the drain electrode.

Abstract: The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (11) comprising a bipolar transistor with an emitter region (1), a base region (2) and a collector region (3) comprising a first, a second and a third connection conductor, which emitter region (1) comprises a mesa-shaped emitter connection region (1A) provided with spacers (4) and adjacent thereto a base connection region (2A) comprising a conductive region (2AA) of poly crystalline silicon. In a device (10) according to the invention, the base connection region (2A) comprises a further conducting region (2AB), which is positioned between the conductive region (2AA) of poly crystalline silicon and the base region (2) and which is made of a material with respect to which the conducting region (2AA) of polycrystalline silicon is selectively etchable. Such a device (10) is easy to manufacture by means of a method according to the invention and its bipolar transistor possesses excellent RF properties.

Abstract: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and a source electrode and drain electrode formed under the semiconductor thin film so as to be electrically connected to the semiconductor thin film.

Abstract: The invention relates to a semiconductor device (10) with a substrate (12) and a semiconductor body (11) of silicon comprising a bipolar transistor with an emitter region, a base region and a collector region (1,2,3) first conductivity type, a second conductivity type opposite to said first conductivity type and the first conductivity type, respectively, with a first semiconductor region (3) comprising the collector region or the emitter region being formed in the semiconductor body (11), on top of which a second semiconductor region (2) comprising the base region is present, on top of which a third semiconductor region (1) comprising the other of said collector region and said emitter region is present, said semiconductor body (11) being provided with a constriction at the location of the transition between the first and the second semiconductor region (3, 2), which constriction has been formed by means of an electrically insulating region (26, 27) buried in the semiconductor body (11).

Abstract: Provided is a NAND-type nonvolatile memory device and method of forming the same. In the method, a plurality of cell layers are stacked on a semiconductor substrate. Seed contact holes for forming a semiconductor pattern included in a stacked cell are formed at regular distance. At this time, the seed contact holes are arranged such that a bit line plug or a source line pattern is disposed at a center between one pair of seed contact holes adjacent to each other.

Abstract: Disclosed herein is a method for production of a thin-film semiconductor device which includes, a first step to form a gate electrode on a substrate, a second step to form a gate insulating film of silicon oxynitride on the substrate in such a way as to cover the gate electrode, a third step to form a semiconductor thin film on the gate insulating film, and a fourth step to perform heat treatment in an oxygen-containing oxidizing atmosphere for modification through oxygen binding with oxygen-deficient parts in the silicon oxynitride film constituting the gate insulating film.

Abstract: A heterojunction bipolar transistor is formed in a semiconductor substrate of a first conductivity type including a collector region. A base region is formed on the substrate and an emitter region is formed over the base region. At least one of the collector, base and emitter regions includes a first region doped with an impurity having a first concentration and a second region doped with the impurity having a second concentration. Noise performance and reliability of the heterojunction bipolar transistor is improved without degrading ac performance.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further includes a cap layer situated on the base, where the cap layer includes a barrier region. The barrier region can comprises carbon and has a thickness, where the thickness of the barrier region determines a depth of an emitter-junction of the heterojunction bipolar transistor. An increase in the thickness of the barrier region can cause a decrease in the depth of the emitter-base junction. According to this exemplary embodiment, the heterojunction bipolar transistor further includes an emitter situated over the cap layer, where the emitter comprises an emitter dopant, which can be phosphorus. A diffusion retardant in the barrier region of the cap layer impedes diffusion of the emitter dopant.

Abstract: A method of producing a thin film transistor array substrate which includes an insulating substrate, a display pixel having a pixel electrode connected to a drain electrode, a gate wiring, and a source wiring perpendicular to the gate wiring, comprising forming a first thin metal multi-layer film an upper layer of which includes aluminum, and spreading a photo-resist, forming the photo-resist to a thickness less in an area connected to a second thin metal film than other area, patterning the first thin metal film, reducing a thickness of the photo-resist layer and removing the photo-resist in the area, removing the upper layer in the area to expose a lower layer, forming an interlayer insulating film and patterning it to expose the lower layer in the area, and patterning the second thin metal film to include the area, to connect the lower layer to the second thin metal film.

Abstract: A method is described for forming a thin film transistor having its current-switching region in polycrystalline semiconductor material which has been crystallized in contact with titanium silicide, titanium silicide-germanide, or titanium germanide. The titanium silicide, titanium silicide-germanide, or titanium germanide is formed having feature size no more than 0.25 micron in the smallest dimension. The small feature size tends to inhibit the phase transformation from C49 to C54 phase titanium silicide. The C49 phase of titanium silicide has a very close lattice match to silicon, and thus provides a crystallization template for the silicon as it forms, allowing formation of large-grain, low-defect silicon. Titanium does not tend to migrate through the silicon during crystallization, limiting the danger of metal contamination. In preferred embodiments, the transistors thus formed may be, for example, field-effect transistors or bipolar junction transistors.

Abstract: In a display device such as a liquid crystal display device, a large-sized display screen is realized under low power consumption. A surface of a source wiring line of a pixel portion employed in an active matrix type liquid crystal display device is processed by way of a plating process operation so as to lower a resistance value of this source wiring line. The source wiring line of the pixel portion is manufactured at a step different from a step for manufacturing a source wiring line of a drive circuit portion. Further, electrodes of a terminal portion are processed by a plating process operation so as to reduce a resistance value thereof.

Abstract: A method of fabricating an image TFT array of a direct X-ray image sensor includes forming a first transparent conductive layer on a substrate; forming a gate line including a gate electrode, a common line, and a common electrode jutting out from the common line; forming an insulation layer; forming a semiconducting island on the insulation layer in the transistor region; forming a first via hole for the common electrode; forming a data line and a source electrode and a drain electrode; forming a passivation layer and a second via hole penetrating the passivation layer for the source electrode; forming a second transparent conductive layer as a top electrode. The insulation layer is formed on the first transparent conductive layer to serve as a dielectric layer of a capacitor before the TFT structure formed and can be formed at a relatively high temperature.

Abstract: A bipolar transistor (100) is manufactured using the following processes: (a) forming a base electrode layer (129) as a portion of a base electrode over a semiconductor substrate (110); (b) forming a first portion of an emitter electrode (154) over the base electrode layer; (c) forming a mask layer (280) over a first portion of the base electrode layer, a portion of the first portion of the emitter electrode and a portion of the semiconductor substrate; and (d) implanting a dopant into a second portion of the base electrode layer after forming the emitter electrode after forming the mask layer.

Abstract: A structure and method of forming a body contact for an semiconductor-on-insulator trench device. The method including: forming set of mandrels on a top surface of a substrate, each mandrel of the set of mandrels arranged on a different corner of a polygon and extending above the top surface of the substrate, a number of mandrels in the set of mandrels equal to a number of corners of the polygon; forming sidewall spacers on sidewalls of each mandrel of the set of mandrels, sidewalls spacers of each adjacent pair of mandrels merging with each other and forming a unbroken wall defining an opening in an interior region of the polygon, a region of the substrate exposed in the opening; etching a contact trench in the substrate in the opening; and filling the contact trench with an electrically conductive material to form the contact.