Abstract: Systems, methods and apparatus are provided for a semiconductor structure. An example method includes a method for forming a contact surface on a vertically oriented access devices. The method includes forming a first source/drain region and a second source/drain region vertically separated by a channel region, forming a sacrificial etch stop layer on a first side of the second source/drain region, wherein the channel region is in contact with a second side of the second source/drain region, forming a dielectric layer on a first side of the sacrificial etch stop layer, where the second source/drain region is connected to a second side of the sacrificial etch stop layer, removing the dielectric layer using a first etch process to expose the sacrificial etch stop layer, and removing the sacrificial etch stop layer using a second etch process to form a contact surface on the second source/drain region.

Abstract: A semiconductor device formed in a semiconductor substrate having a first main surface comprises a transistor array and a termination region. The transistor array comprises a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region. The gate electrode is disposed in first trenches. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a first ridge extending along the first direction. The termination region comprises a termination trench, a portion of the termination trench extending in the first direction, a length of the termination trench being larger than a length of the first trenches, the length being measured along the first direction.

Abstract: A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first nanowire extending through a first gate electrode and between first source and drain regions. The second transistor includes a second nanowire extending through a second gate electrode and between a second source and drain regions. The first nanowire has a first size in a first direction and a second size in a second direction, and the second nanowire has a second size in the first direction and substantially the second size in the second direction. The first nanowire has a first on current and the second nanowire has a second on current. The on current of the first nanowire may be substantially equal to the on current of the second nanowire based on a difference between the sizes of the first and second nanowires. In another arrangement, the on currents may be different.

Abstract: In accordance with an example embodiment of the present invention, a device comprising one or more porous graphene layers, the or each graphene porous layer comprising a multiplicity of pores. The device may form at least part of a flexible and/or stretchable, and or transparent electronic device.

Abstract: A method to fabricate a carbon nanotube (CNT)-based transistor includes providing a substrate having a CNT disposed over a surface; forming a protective electrically insulating layer over the CNT and forming a first multi-layer resist stack (MLRS) over the protective electrically insulating layer. The first MLRS includes a bottom layer, an intermediate layer and a top layer of resist. The method further includes patterning and selectively removing a portion of the first MLRS to define an opening for a gate stack while leaving the bottom layer; selectively removing a portion of the protective electrically insulating layer within the opening to expose a first portion of the CNT; forming the gate stack within the opening and upon the exposed first portion of the carbon nanotube, followed by formation of source and drain contacts also in accordance with the inventive method so as to expose second and third portions of the CNT.

Abstract: A structure includes a substrate having a carbon nanotube (CNT) disposed over a surface. The CNT is partially disposed within a protective electrically insulating layer. The structure further includes a gate stack disposed over the substrate. A first portion of a length of the CNT not covered by the protective electrically insulating layer passes through the gate stack. Source and drain contacts are disposed adjacent to the gate stack, where second and third portions of the length of CNT not covered by the protective electrically insulating layer are conductively electrically coupled to the source and drain contacts. The gate stack and the source and drain contacts are contained within the protective electrically insulating layer and within an electrically insulating organic planarization layer that is disposed over the protective electrically insulating layer. A method to fabricate a CNT-based transistor is also described.

Abstract: The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact.

Abstract: According to example embodiments, a HEMT includes a channel layer, a channel supply layer on the channel layer, a source electrode and a drain electrode spaced apart on the channel layer, a depletion-forming layer on the channel supply layer, and a plurality of gate electrodes on the depletion-forming layer between the source electrode and the drain electrode. The channel supply layer is configured to induce a two-dimensional electron gas (2DEG) in the channel layer. The depletion-forming layer is configured to form a depletion region in the 2DEG. The plurality of gate electrodes include a first gate electrode and a second gate electrode spaced apart from each other.

Abstract: An Impact Ionization Field-Effect Transistor (I-MOS) device in which device degradation caused by hot carrier injection into a gate oxide is prevented. The device includes source, drain, and gate contacts, and a channel between the source and the drain. The channel has a dimension normal to the direction of a charge carrier transport in the channel such that the energy separation of the first two sub-bands equals or exceeds the effective energy band gap of the channel material.

Abstract: A method of forming a semiconductor is provided and includes patterning a pad and a nanowire onto a wafer, the nanowire being substantially perpendicular with a pad sidewall and substantially parallel with a wafer surface and epitaxially growing on an outer surface of the nanowire a secondary layer of semiconductor material, which is lattice mismatched with respect to a material of the nanowire and substantially free of defects.

Abstract: A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.

Abstract: The invention can be used for producing different luminescent materials and as a basis for producing subminiature light-emitting diodes, white light sources, single-electron transistors, nonlinear optical devices and photosensitive and photovoltaic devices. The inventive method for producing semiconductor quantum dots involves synthesizing nanocrystal nuclei from a chalcogen-containing precursor and a precursor containing a group II or IV metal using an organic solvent and a surface modifier. The method is characterized in that (aminoalkyl)trialkoxysilanes are used as the surface modifier, core synthesis is carried out at a permanent temperature ranging from 150 to 250 C for 15 seconds to 1 hour and in that the reaction mixture containing the nanocrystal is additionally treated by UV-light for 1-10 minutes and by ultrasound for 5-15 minutes.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: A photodetector includes: a substrate; a first dielectric material positioned on the substrate; an optical waveguide positioned on the first dielectric material; a second dielectric material positioned on the optical waveguide; a graphene layer positioned on the second dielectric material; and a first electrode and a second electrode that are positioned on the graphene layer.

Abstract: The semiconductor device is provided in which a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is arranged in matrix and a wiring (also referred to as a bit line) for connecting one of the memory cells and another one of the memory cells and a source or drain region in the first transistor are electrically connected through a conductive layer and a source or drain electrode in the second transistor provided therebetween. With this structure, the number of wirings can be reduced in comparison with a structure in which the source or drain electrode in the first transistor and the source or drain electrode in the second transistor are connected to different wirings. Thus, the integration degree of a semiconductor device can be increased.

Abstract: A semiconductor device includes a substrate, first plural contacts formed in the substrate, a graphene layer formed on the substrate and on the first plural contacts and second plural contacts formed on the graphene layer such that the graphene layer is formed between the first plural contacts and the second plural contacts.

Abstract: A method for forming a nanowire field effect transistor (FET) device, the method includes forming a suspended nanowire over a semiconductor substrate, forming a gate structure around a portion of the nanowire, forming a protective spacer adjacent to sidewalls of the gate and around portions of nanowire extending from the gate, removing exposed portions of the nanowire left unprotected by the spacer structure, and epitaxially growing a doped semiconductor material on exposed cross sections of the nanowire to form a source region and a drain region.

Abstract: Non-planar semiconductor devices are provided that include at least one semiconductor nanowire suspended above a semiconductor oxide layer that is present on a first portion of a bulk semiconductor substrate. An end segment of the at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of the at least one semiconductor nanowire is attached to a second semiconductor pad region. The first and second pad regions are located above and are in direct contact with a second portion of the bulk semiconductor substrate which is vertically offsets from the first portion. The structure further includes a gate surrounding a central portion of the at least one semiconductor nanowire, a source region located on a first side of the gate, and a drain region located on a second side of the gate which is opposite the first side of the gate.

Abstract: A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming first and second nanowire channels connected at each end to semiconductor pads at first and second wafer regions, respectively, with second nanowire channel sidewalls being misaligned relative to a crystallographic plane of the semiconductor more than first nanowire channel sidewalls and displacing the semiconductor toward an alignment condition between the sidewalls and the crystallographic plane such that thickness differences between the first and second nanowire channels reflect the greater misalignment of the second nanowire channel sidewalls.

Abstract: Non-planar semiconductor devices including at least one semiconductor nanowire having a tapered profile which widens from the source side of the device towards the drain side of the device are provided which have reduced gate to drain coupling and therefore reduced gate induced drain tunneling currents.

Abstract: Semiconductor nano-devices, such as nano-probe and nano-knife devices, which are constructed using graphene films that are suspended between open cavities of a semiconductor structure. The suspended graphene films serve as electro-mechanical membranes that can be made very thin, from one or few atoms in thickness, to greatly improve the sensitivity and reliability of semiconductor nano-probe and nano-knife devices.

Abstract: A method for forming a nanowire field effect transistor (FET) device includes forming a nanowire over a substrate, forming a liner material around a portion of the nanowire, forming a capping layer on the liner material, forming a first spacer adjacent to sidewalls of the capping layer and around portions of the nanowire, forming a hardmask layer on the capping layer and the first spacer, removing an exposed portion of the nanowire to form a first cavity partially defined by the gate material, epitaxially growing a semiconductor material on an exposed cross section of the nanowire in the first cavity, removing the hardmask layer and the capping layer, forming a second capping layer around the semiconductor material epitaxially grown in the first cavity to define a channel region, and forming a source region and a drain region contacting the channel region.

Abstract: A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided.

Abstract: A method of modifying a wafer having semiconductor disposed on an insulator is provided and includes establishing first and second regions of the wafer with different initial semiconductor thicknesses, forming pairs of semiconductor pads connected via respective nanowire channels at each of the first and second regions and reshaping the nanowire channels into nanowires each having a respective differing thickness reflective of the different initial semiconductor thicknesses at each of the first and second regions.

Abstract: A method of modifying a wafer having a semiconductor disposed on an insulator is provided and includes forming pairs of semiconductor pads connected via respective nanowire channels at each of first and second regions with different initial semiconductor thicknesses and reshaping the nanowire channels into nanowires to each have a respective differing thickness reflective of the different initial semiconductor thicknesses.

Abstract: A method to fabricate a carbon nanotube (CNT)-based transistor includes providing a substrate having a CNT disposed over a surface; forming a protective electrically insulating layer over the CNT and forming a first multi-layer resist stack (MLRS) over the protective electrically insulating layer. The first MLRS includes a bottom layer, an intermediate layer and a top layer of resist. The method further includes patterning and selectively removing a portion of the first MLRS to define an opening for a gate stack while leaving the bottom layer; selectively removing a portion of the protective electrically insulating layer within the opening to expose a first portion of the CNT; forming the gate stack within the opening and upon the exposed first portion of the carbon nanotube, followed by formation of source and drain contacts also in accordance with the inventive method so as to expose second and third portions of the CNT.

Abstract: Embodiments relate to a method for fabricating nano-wires in nano-devices, and more particularly to nano-device fabrication using end-of-range (EOR) defects. In one embodiment, a substrate with a surface crystalline layer over the substrate is provided and EOR defects are created in the surface crystalline layer. One or more fins with EOR defects embedded within is formed and oxidized to form one or more fully oxidized nano-wires with nano-crystals within the core of the nano-wire.

Abstract: A semiconductor power switch and method is disclosed. In one Embodiment, the semiconductor power switch has a source contact, a drain contact, a semiconductor structure which is provided between the source contact and the drain contact, and a gate which can be used to control a current flow through the semiconductor structure between the source contact and the drain contact. The semiconductor structure has a plurality of nanowires which are connected in parallel and are arranged in such a manner that each nanowire forms an electrical connection between the source contact and the drain contact.

Abstract: In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.

Abstract: A luminous device and a method of manufacturing the luminous device are provided. The luminous device includes a light emitting layer and first and second electrodes connected to the light emitting layer. The light emitting layer is a strained nanowire.

Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Abstract: A method of manufacturing at least one nanowire, the nanowire being parallel to its supporting substrate, the method including the formation on the supporting substrate of a structure comprising a bar and two regions, a first end of the bar being secured to one of the two regions and a second end of the bar being secured to the other region, the width of the bar being less than the width of the regions, the subjection of the bar to an annealing under gaseous atmosphere in order to transform the bar into a nanowire, the annealing being carried out under conditions allowing control of the sizing of the neck produced during the formation of the nanowire.

Abstract: A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.

Abstract: A method for forming a semiconductor device includes forming a nanotube region using a thin epitaxial layer formed on the sidewall of a trench in the semiconductor body. The thin epitaxial layer has uniform doping concentration. In another embodiment, a first thin epitaxial layer of the same conductivity type as the semiconductor body is formed on the sidewall of a trench in the semiconductor body and a second thin epitaxial layer of the opposite conductivity type is formed on the first epitaxial layer. The first and second epitaxial layers have uniform doping concentration. The thickness and doping concentrations of the first and second epitaxial layers and the semiconductor body are selected to achieve charge balance. In one embodiment, the semiconductor body is a lightly doped P-type substrate. A vertical trench MOSFET, an IGBT, a Schottky diode and a P-N junction diode can be formed using the same N-Epi/P-Epi nanotube structure.

Abstract: A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.

Abstract: A semiconductor device includes a semiconductor island having at least one electrical dopant atom and encapsulated by dielectric materials including at least one dielectric material layer. At least two portions of the at least one dielectric material layer have a thickness less than 2 nm to enable quantum tunneling effects. A source-side conductive material portion and a drain-side conductive material portion abuts the two portions of the at least one dielectric material layer. A gate conductor is located on the at least one dielectric material layer between the source-side conductive material portion and the drain-side conductive material portion. The potential of the semiconductor island responds to the voltage at the gate conductor to enable or disable tunneling current through the two portions of the at least one dielectric material layer. Design structures for the semiconductor device are also provided.

Abstract: In one exemplary embodiment, a method includes: providing a semiconductor device having a substrate, a nanowire, a first structure and a second structure, where the nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate; and performing atomic layer deposition to deposit a film on at least a portion of the semiconductor device, where performing atomic layer deposition to deposit the film includes performing atomic layer deposition to deposit the film on at least a surface of the nanowire.

Abstract: A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.

Abstract: A graphene device structure and a method for manufacturing the same are provided. The graphene device structure comprises: a graphene layer; a gate region formed on the graphene layer; and a doped semiconductor region formed at one side of the gate region and connected with the graphene layer, wherein the doped semiconductor region is a drain region of the graphene device structure, and the graphene layer formed at one side of the gate region is a source region of the graphene device structure. The on/off ratio of the graphene device structure may be improved by the doped semiconductor region without increasing the band gaps of the graphene material, so that the applicability of the graphene material in CMOS devices may be enhanced without decreasing the carrier mobility of graphene materials and speed of the devices.

Abstract: Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.

Abstract: A plurality of nanowires is grown on a first substrate in a first direction perpendicular to the first substrate. An insulation layer covering the nanowires is formed on the first substrate to define a nanowire block including the nanowires and the insulation layer. The nanowire block is moved so that each of the nanowires is arranged in a second direction parallel to the first substrate. The insulation layer is partially removed to partially expose the nanowires. A gate line covering the exposed nanowires is formed. Impurities are implanted into portions of the nanowires adjacent to the gate line.

Abstract: A PRAM device includes a lower electrode, a phase-change nanowire and an upper electrode. The phase-change nanowire may be electrically connected to the lower electrode and includes a single element. The upper electrode may be electrically connected to the phase-change nanowires.

Abstract: An electronic device and method of manufacturing the device. The device includes a semiconducting region, which can be a nanowire, a first contact electrically coupled to the semiconducting region, and at least one second contact capacitively coupled to the semiconducting region. At least a portion of the semiconducting region between the first contact and the second contact is covered with a dipole layer. The dipole layer can act as a local gate on the semiconducting region to enhance the electric properties of the device.

Abstract: A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.

Abstract: A graphene-based field effect transistor includes source and drain electrodes that are self-aligned to a gate electrode. A stack of a seed layer and a dielectric metal oxide layer is deposited over a patterned graphene layer. A conductive material stack of a first metal portion and a second metal portion is formed above the dielectric metal oxide layer. The first metal portion is laterally etched employing the second metal portion, and exposed portions of the dielectric metal oxide layer are removed to form a gate structure in which the second metal portion overhangs the first metal portion. The seed layer is removed and the overhang is employed to shadow proximal regions around the gate structure during a directional deposition process to form source and drain electrodes that are self-aligned and minimally laterally spaced from edges of the gate electrode.

Abstract: A single electron transistor includes source/drain layers disposed apart on a substrate, at least one nanowire channel connecting the source/drain layers, a plurality of oxide channel areas in the nanowire channel, the oxide channel areas insulating at least one portion of the nanowire channel, a quantum dot in the portion of the nanowire channel insulated by the plurality of oxide channel areas, and a gate electrode surrounding the quantum dot.

Abstract: A resonant structure is provided, including a first terminal, a second terminal which faces the first terminal, a wire unit which connects the first terminal and the second terminal, a third terminal which is spaced apart at a certain distance from the wire unit and which resonates the wire unit, and a potential barrier unit which is formed on the wire unit and which provides a negative resistance component. Accordingly, transduction efficiency can be enhanced.

Abstract: In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.