Field-effect Transistor (epo) Patents (Class 257/E21.4)
- Using static field induced region, e.g., SIT, PBT (EPO) (Class 257/E21.406)
- With an heterojunction interface channel or gate, e.g., HFET, HIGFET, SI SFET, HJFET, HEMT (EPO) (Class 257/E21.407)
- With one or zero or quasi-one or quasi-zero dimensional channel, e.g., in plane gate transistor (IPG), single electron transistor (SET), striped channel transistor, coulomb blockade device (EPO) (Class 257/E21.408)
- Vertical transistor (EPO) (Class 257/E21.41)
- Thin film unipolar transistor (EPO) (Class 257/E21.411)
- With channel containing layer, e.g., p-base, fo rmed in or on drain region, e.g., DMOS transistor (EPO) (Class 257/E21.417)
- With multiple gate, one gate having MOS structure and others having same or a different structure, i.e., non MOS, e.g., JFET gate (EPO) (Class 257/E21.421)
- With floating gate (EPO) (Class 257/E21.422)
- With charge trapping gate insulator, e.g., MNOS transistor (EPO) (Class 257/E21.423)
- Lateral single gate silicon transistor (EPO) (Class 257/E21.424)
- With source or drain region formed by Schottky barrier or conductor-insulator-semiconductor structure (EPO) (Class 257/E21.425)
- With single crystalline channel formed on the silicon substrate after insulating device isolation (EPO) (Class 257/E21.426)
- With asymmetry in channel direction, e.g., high-voltage lateral transistor with channel containing layer, e.g., p-base (EPO) (Class 257/E21.427)
- With a recessed gate, e.g., lateral U-MOS (EPO) (Class 257/E21.428)
- With source and drain recessed by etching or recessed and refi lled (EPO) (Class 257/E21.431)
- With source and drain contacts formation strictly before final gate formation, e.g., contact first technology (EPO) (Class 257/E21.432)
- Where the source and drain or source and drain extensions are self-aligned to sides of gate (EPO) (Class 257/E21.433)
- Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO) (Class 257/E21.435)
- Gate comprising layer with ferroelectric properties (EPO) (Class 257/E21.436)
- With lightly doped drain selectively formed at side of gate (EPO) (Class 257/E21.437)
- Using self-aligned silicidation, i.e., salicide (EPO) (Class 257/E21.438)
- Using self-aligned selective metal deposition simultaneously on gate and on source or drain (EPO) (Class 257/E21.44)
- Active layer is Group III-V compound (EPO) (Class 257/E21.441)
- With gate at side of channel (EPO) (Class 257/E21.442)
- Using self-aligned punch through stopper or threshold implant under gate region (EPO) (Class 257/E21.443)
- Using dummy gate wherein at least part of final gate is self-aligned to dummy gate (EPO) (Class 257/E21.444)
- Active layer being Group III-V compound (EPO) (Class 257/E21.451)
- Lateral single-gate transistors (EPO) (Class 257/E21.452)
- Process wherein final gate is made after formation of source and drain regions in active layer, e.g., dummy-gate process (EPO) (Class 257/E21.453)
- Process wherein final gate is made before formation, e.g., activation anneal, of source and drain regions in active layer (EPO) (Class 257/E21.454)
- Lateral transistor with two or more independen t gates (EPO) (Class 257/E21.455)