Abstract: A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.

Abstract: A transistor includes substrate having an active region therein. The active region includes a recess therein having opposing sidewalls and a surface therebetween. A protrusion extends from the surface of the recess between the opposing sidewalls thereof. The transistor further includes a gate insulation layer on the protrusion in the recess, a gate electrode on the gate insulation layer in the recess, and source/drain regions in the active region on opposite sides of the gate electrode and adjacent to the opposing sidewalls of the recess. The gate electrode includes portions that extend into the recess between the protrusion and the opposing sidewalls of the recess. Related methods of fabrication are also discussed.

Abstract: Example embodiments relate to a non-volatile semiconductor memory device and a method of manufacturing the same. A semiconductor device includes an isolation layer protruding from a substrate, a spacer, a tunnel insulation layer, a floating gate, a dielectric layer pattern and a control gate. The spacer may be formed on a sidewall of a protruding portion of the isolation layer. The tunnel insulation layer may be formed on the substrate between adjacent isolation layers. The floating gate may be formed on the tunnel insulation layer. The floating gate contacts the spacer and has a width that gradually increases from a lower portion toward an upper portion. The dielectric layer pattern and the control gate may be sequentially formed on the floating gate.

Abstract: Embodiments relate to a method for manufacturing a semiconductor device that may be capable of obtaining a stable device characteristic by securing an optimal CD of a gate. In embodiments, a method may include forming a gate oxide layer on a semiconductor substrate, forming a photoresist pattern at a first region of an upper portion of the gate oxide layer, forming an insulating layer on the substrate of a second region except for the photoresist pattern, removing the photoresist pattern after a formation of the insulating layer, forming a polysilicon on the substrate from which the photoresist pattern is removed, planarizing the polysilicon to expose the insulating layer in order to form a gate, forming sidewalls at both sides of the gate: and implanting ions in a resulting object using the sidewalls as a mask to form source/drain.

Abstract: Provided are example embodiments of a non-volatile memory device and a method of fabricating the same. The non-volatile memory device may include a control gate electrode arranged on a semiconductor substrate, a gate insulating layer interposed between the semiconductor substrate and the control gate electrode, a storage node layer interposed between the gate insulating layer and the control gate electrode, a blocking insulating layer interposed between the storage node layer and the control gate electrode, first dopant doping regions along a first side of the control gate electrode, and second dopant doping regions along a second side of the control gate electrode. The first dopant doping regions may alternate with the second dopant doping regions. Stated differently, each of the second dopant doping regions may be arranged in a region on the second side of the control gate electrode that is adjacent to one of the first dopant doping regions.

Abstract: There is provided a system and method for fabricating a fin field effect transistor. More specifically, in one embodiment, there is provided a method comprising depositing a layer of nitride on a substrate, applying a photolithographic mask on the layer of nitride to define a location of a wall, etching the layer of nitride to create the wall, removing the photolithographic mask, depositing a spacer layer adjacent to the wall, etching the spacer layer to create a spacer adjacent to the wall, wherein the spacer and the wall cover a first portion of the substrate, and etching a second portion of the substrate not covered by the spacer to create a trench.

Abstract: In order to reduce the integrated circuit area that is occupied by an array of a given number of flash memory cells, floating gate charge storage elements are positioned along sidewalls of substrate trenches, preferably being formed of doped polysilicon spacers. An array of dual floating gate memory cells includes cells with this structure, as an example. A NAND array of memory cells is another example of an application of this cell structure. The memory cell and array structures have wide application to various specific NOR and NAND memory cell array architectures.

Abstract: A method of manufacturing a semiconductor device according to an embodiment of the present invention includes: forming a first insulating film on a semiconductor substrate; forming a mask with an opening of a predetermined pattern in the first insulating film; performing anisotropic etching on the semiconductor substrate with the mask used as an etching mask to form a trench; forming a second insulating film on a surface of an inner wall of the trench with the mask used as a selective oxidation mask; removing the mask; forming a conductive film on the semiconductor substrate to fill the trench with the conductive film; and etching back the conductive film until at least a surface of the semiconductor substrate is exposed.

Abstract: Methods of making Si-containing films that contain relatively high levels of Group III or Group V dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain at least about 3×1020 atoms cm?3 of an electrically active dopant. Substitutionally doped Si-containing films may be selectively deposited onto the crystalline surfaces of mixed substrates by introducing an etchant gas during deposition.

Abstract: The present invention is to provide a trench MOSFET with an etching buffer layer in a trench gate, comprising: a substrate which has a first surface and a second surface opposite to each other and comprises at least a drain region, a gate region, and a source region which are constructed as a plurality of semiconductor cells with MOSFET effect; a plurality of gate trenches, each of which is extended downward from the first surface and comprises a gate oxide layer covered on a inner surface thereof and a gate conductive layer filled inside, comprised in the gate region; at least a drain metal layer formed on the second surface according to the drain region; at least a gate runner metal layer formed on the first surface according to the gate region; and at least a source metal layer formed on the first surface according to the source region; wherein the gate trenches distinguished into at least a second gate trench formed at a terminal of the source region and at least a first gate trenches wrapped in the sourc

Abstract: A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.

Abstract: A metal oxide semiconductor (MOS) includes an isolation layer disposed in a semiconductor substrate to define an active region. A source region and a drain region are disposed on both sides of the active region such that a first direction is defined from the source region to the drain region. A channel recess is disposed in the active region between the source and drain regions. The channel recess has a convex surface when viewed from a cross-sectional view taken along a second direction orthogonal to the first direction. A gate electrode fills the channel recess and crosses the active region in the second direction. A gate insulating layer is interposed between the gate electrode and the active region.

Abstract: a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

Abstract: A method for fabricating a semiconductor device is provided which has first and second regions, transistors of different conductivity types being formed on parts of a substrate corresponding to the first and second regions. The method includeujs the steps of: (a) forming a first insulating film to cover the parts of the substrate corresponding to the first and second regions; (b) forming a first thin film on the first insulating film, the first thin film having a relatively higher etching rate than the first insulating film in plasma etching using a halogen gas; and (c) removing a part of the first thin film corresponding to the first region by the plasma etching using a mask covering the second region and modifying a part of the first insulating film corresponding to the first region.

Abstract: A method of forming a field effect transistor comprises providing a semiconductor substrate, a gate electrode being formed over the semiconductor substrate. At least one cavity is formed adjacent the gate electrode. A strain-creating element is formed in the at least one cavity. The strain-creating element comprises a compound material comprising a first chemical element and a second chemical element. A first concentration ratio between a concentration of the first chemical element in a first portion of the strain-creating element and a concentration of the second chemical element in the first portion of the strain-creating element is different from a second concentration ratio between a concentration of the first chemical element in a second portion of the strain-creating element and a concentration of the second chemical element in the second strain-creating element.

Abstract: A method of manufacturing a semiconductor device is provided. Device separation portions defining first, second and third regions are formed in a substrate. A recess is formed at the first region. An N-type well is formed at the third region. An N-type polysilicon layer is formed at the first and second regions. A P-type polysilicon layer is formed at the third region. At least one of metal silicide film and a metal film is formed on the N-type polysilicon layer and the P-type polysilicon layer. Etching is performed to form a gate electrode including the N-type polysilicon layer at the first and second regions and a gate electrode including the P-type polysilicon layer at the third region. A cell transistor having a recess channel structure is formed at the first region, an nMOSFET structure is formed at the second region, and a pMOSFET structure is formed at the third region.

Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a trench in a semiconductor substrate; and forming an epitaxial film on the substrate including a sidewall and a bottom of the trench so that the epitaxial film is filled in the trench. The step of forming the epitaxial film includes a final step before the trench is filled with the epitaxial film. The final step has a forming condition of the epitaxial film in such a manner that the epitaxial film to be formed on the sidewall of the trench has a growth rate at an opening of the trench smaller than a growth rate at a position of the trench, which is deeper than the opening of the trench.

Abstract: A semiconductor device includes: a layer provided on or above a semiconductor substrate, having an opening, and containing Si and Ge; and a gate provided at a position corresponding to the opening. It is possible to provide a semiconductor device and a manufacturing method of the same which realize easy control of a recess amount and reduction in damage at the time of the recessing.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: sequentially forming an oxide layer and a nitride layer on a substrate having a gate insulating layer and a gate formed in the order named thereon; forming a spacer at both sidewalls of the gate by etching the nitride layer; forming a source region and a drain region at both sides of the spacer in the substrate; removing the oxide layer formed on the gate and the substrate; partially removing surfaces of the gate, the source region and the drain region from which the oxide layer is removed; and depositing and thermally annealing a metal layer on the surfaces of the gate, source and drain whose surfaces are partially removed, to form a salicide layer.

Abstract: Method for manufacturing a semiconductor device including a transistor having a grooved gate structure and a transistor having a planar gate structure on the same substrate, in which, even when the semiconductor device is configured as a dual gate structure in which a gate electrode structure is a poly-metal gate structure, and a grooved gate and a planar gate are made in different conductivity types, then sufficient dopant is injected into polysilicon in the grooved gate to prevent depletion, and impurity ions do not pass through a gate insulating film even when the planar gate is formed also polysilicon having the same film thickness. The method includes: injecting ions into an amorphous silicon layer for the grooved gate; subsequently, turning it into polysilicon once; injecting ions once again to amorphousize a surface layer of the polysilicon layer and injecting ions of a different conductivity type for the planar gate.

Abstract: A MOS transistor made in monolithic form, vias contacting the gate and the source and drain regions of the transistor being formed on the other side of the channel region with respect to the gate.

Abstract: A method for manufacturing a trench power transistor includes providing a substrate, forming an epitaxy layer on the substrate, performing a dry etching process on the epitaxy layer for generating a first trench, forming a gate oxide layer in the first trench and depositing poly-Si on the gate oxide layer in the first trench, performing a boron implant process on regions outside the first trench and inside the epitaxy layer, performing an arsenic implant process on regions beside the first trench and inside the epitaxy layer, depositing a first dielectric material on the surface of the epitaxy layer, performing a dry etching process on the epitaxy layer for generating a second trench, depositing a conductive material in the second trench for forming a p-well junction on sidewalls of the second trench, and performing a wet immersion process for forming a contact hole, and depositing frontside and backside metal.

Abstract: A semiconductor device includes a substrate having a recess, a gate electrode in the recess in the substrate, and a source electrode and a drain electrode disposed on opposite sides of the gate electrode. An insulating film is on at least on a surface of the gate electrode and a portion in the recess, other than where the gate electrode is located, and a shield electrode connected to the source electrode is located on a portion of the insulating film between the gate electrode and the drain electrode.

Abstract: A semiconductor device includes a device isolation structure having a grounded conductive layer to define an active region, and a gate formed over the active region and the device isolation structure.

Abstract: A method of manufacturing a metal oxide semiconductor transistor having a metal gate is provided. The method firstly includes a step of providing a substrate. A dummy gate is formed on the substrate, a spacer is formed around the dummy gate, and doped regions are formed in the substrate outside of the dummy gate. A bevel edge is formed on the spacer, and a trench is formed in the inner sidewall of the spacer. A barrier layer, and a metal gate are formed in the trench and on the bevel edge, and the barrier layer will not form poor step coverage.

Abstract: A method for fabricating a semiconductor device with a step gated asymmetric recess is provided.

Abstract: A method for fabricating recess channel MOS transistors of the present invention utilizes a lithography process to form trenches in the recess channel MOS transistors after finishing a STI process. Furthermore, the method of the present invention can make the critical dimension variation to be controlled in a range required in the precision semiconductor process. Therefore, the short problem between the transistors can be avoided.

Abstract: A method for fabricating a semiconductor device having a flask type recess gate includes forming a hard mask pattern on a substrate, etching the substrate to a predetermined depth using the hard mask pattern to form a first recess pattern, forming a passivation layer on sidewalls of the first recess pattern and the hard mask pattern, etching a bottom surface of the first recess pattern exposed by the passivation layer to form a second recess pattern, oxidizing sidewalls of the second recess pattern to form a silicon oxide layer, removing the passivation layer and the silicon oxide layer in sequential order, and forming a gate pattern over an intended recess pattern including the first recess pattern and the second recess pattern.

Abstract: Disclosed are a semiconductor device and a method for fabrication of the same. The fabrication method may include selectively forming an oxide layer pattern on a semiconductor substrate, forming an insulation layer pattern on the same substrate to cover edge portions of the oxide layer pattern, etching the oxide layer pattern and the substrate to form a recess as well as first and second oxide layer patterns corresponding to the edge portions of the oxide layer pattern, forming a third oxide layer pattern on the substrate in the recess to produce a gate insulation layer comprising the first, second, and third oxide layer patterns, and forming a gate pattern in the recess. The fabricated semiconductor device minimizes occurrence of current leakage such as gate induction drain leakage, among other things, thereby improving transistor performance.

Abstract: A long channel semiconductor device and a manufacturing method thereof are provided. The method for forming a long channel semiconductor device includes: providing a substrate; forming a trench in the substrate with a trench bottom defining a first channel length; forming a spacer on a sidewall of the trench; recessing the trench bottom to form a recessed bottom defining a second channel length longer than the first channel length; forming a gate dielectric layer on the recessed bottom; forming a gate conductor on the gate dielectric layer; and forming source/drain regions in the substrate adjacent to the spacer.

Abstract: A U-shape Metal-Oxide-Semiconductor (UMOS) device comprises a P-base layer, an N+ source region disposed in the P-base layer where the source region has a first surface coplanar with a first surface of the P-base layer, a dielectric layer extending through the P-base layer and forming a U-shape trench having side walls and floor enclosing a trench interior region, a conducting gate material filling the trench interior region, a first accumulation channel layer disposed along a first side wall of the U-shape trench and in contact with the source region and a first side wall of the U-shape trench, a P-junction gate disposed adjacent to the dielectric layer floor and in proximity to the first accumulation channel layer, and an N-drift region where the P-junction gate is disposed between the dielectric layer and the N-drift region.

Abstract: Disclosed herein are a recess-gate structure in which junctions have a thickness significantly smaller than the thickness of a device isolation layer to thereby prevent shorting of the junctions located at opposite lateral sides of the device isolation layer close thereto, resulting in an improvement in the operational reliability of a resultant device, and a method for forming the same. The recess-gate structure comprises a silicon substrate in which an active region and a device isolation region are defined, a plurality of gates formed on the substrate, gate spacers formed at the side wall of the respective gates, and junctions formed in the substrate at opposite lateral sides of the gates and defining an asymmetrical structure relative to each other. A gate recess is defined in the active region of the substrate to have a stepped profile consisting of a bottom plane, top plane, and vertical plane.

Abstract: A transistor includes a substrate and an isolation region disposed in the substrate. The isolation regions defines an active region comprising upper and lower active regions, the upper active region having a first width and the lower active region having a second width greater than the first width. An insulated gate electrode extends through the upper active region and into the lower active region. Source and drain regions are disposed in the active region on respective first and second sides of the insulated gate electrode. The insulated gate electrode may include an upper gate electrode disposed in the upper active region and a lower gate electrode disposed in the lower active region, wherein the lower gate electrode is wider than the upper gate electrode. Related fabrication methods are described.

Abstract: Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a field effect transistor device comprises the following steps. A substrate is provided having a silicon layer thereon. A fin lithography hardmask is patterned on the silicon layer. A dummy gate structure is placed over a central portion of the fin lithography hardmask. A tiller layer is deposited around the dummy gate structure. The dummy gate structure is removed to reveal a trench in the filler layer, centered over the central portion of the fin lithography hardmask, that distinguishes a fin region of the device from source and drain regions of the device. The fin lithography hardmask in the fin region is used to etch a plurality of fins in the silicon layer. The trench is filled with a gate material to form a gate stack over the fins.

Abstract: The present invention provides a semiconductor device comprising: a dual-gate peripheral transistor having a transistor structure of surface channel nMOSFET and a transistor structure of surface channel pMOSFET; and a cell transistor having an nMOSFET structure with a recess channel structure, a gate electrode of the cell transistor having an N-type polysilicon layer which contains of N-type impurities at an approximately constant concentration.

Abstract: A method of forming films in a trench is applied to the manufacturing process of a power MOS device. In one embodiment, the method comprises providing a semiconductor substrate, forming a trench in the semiconductor substrate, forming a first dielectric layer on sidewalls of the trench, forming a second dielectric layer on the first dielectric layer, and forming a polysilicon layer in the trench. The method of forming films in a trench of the present invention can reduce or eliminate the thermal stress resulting from the different thermal expansion coefficients of different material layers after high temperature process.

Abstract: Method for manufacturing a semiconductor device including a transistor having a grooved gate structure and a transistor having a planar gate structure on the same substrate, in which, even when the semiconductor device is configured as a dual gate structure in which a gate electrode structure is a poly-metal gate structure, and a grooved gate and a planar gate are made in different conductivity types, then sufficient dopant is injected into polysilicon in the grooved gate to prevent depletion, and impurity ions do not pass through a gate insulating film even when the planar gate is formed also polysilicon having the same film thickness. The method includes: injecting ions into an amorphous silicon layer for the grooved gate; subsequently, turning it into polysilicon once; injecting ions once again to amorphousize a surface layer of the polysilicon layer and injecting ions of a different conductivity type for the planar gate.

Abstract: A method of forming a semiconductor device uses an anneal technique to planarize and round corners of a trench formed in a substrate. The substrate is annealed under a normal pressure in an inert atmosphere, such as an atmosphere containing one of argon, helium, and neon, or an atmosphere of a gas mixture of hydrogen of 4% or less and one of argon, helium, and neon at a temperature of between 900° C. and 1050° C. for a time of between 30 seconds and 30 minutes to round the trench corners and planarize the trench side walls. Alternatively, after removing a mask for forming the trench, the substrate can be annealed in the inert atmosphere. This provides easy and inexpensive way of planarizing the trench side walls, as well as rounding of the trench corners. Moreover, by removing the mask for forming the trench before annealing enables the semiconductor device to have a highly reliable gate insulator film with good reproducibility.

Abstract: By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the performance of transistor devices, in which two channel regions may be defined.

Abstract: A semiconductor device includes a semiconductor substrate, a cell region in a surface portion of the substrate for operating as a transistor, a gate lead wiring region having a gate lead pattern on the substrate, a trench in the surface portion of the substrate extending from the cell region to the gate lead wiring region, an oxide film on an inner surface of the trench, and a gate electrode in the trench insulated with at least the oxide film from the substrate. A speed of formation of a main portion of the sidewalls of the trench at the gate lead wiring region is greater than that of a main portion of the sidewalls of the trench at the cell region, so that a thickness of the oxide film at the gate lead wiring region is greater than that at the cell region.

Abstract: Methods of fabricating a single transistor floating body dynamic random access memory (DRAM) cell include forming a barrier layer on a semiconductor substrate. A body layer is formed on the barrier layer. An isolation layer is formed defining a floating body region within the body layer. A recess region is formed in the floating body region. A gate electrode is formed in the recess region. Impurity ions of a first conductivity type are implanted into a portion of the floating body region on a first side of the recess region to define a source region and into a portion of the floating body on an opposite side of the recess region to define a drain region to provide a floating body.

Abstract: A semiconductor device including a transistor and a method of forming thereof are provided. The semiconductor device comprises a metal gate electrode. A lower portion of the metal gate electrode fills a channel trench formed at a predetermined region of a substrate, and an upper portion of the metal gate electrode protrudes on the substrate. A gate insulating layer is interposed between inner sidewalls and a bottom surface of the channel trench, and the metal gate electrode. Source/drain regions are formed at the substrate in both sides of the metal gate electrode.

Abstract: A metal-oxide-semiconductor (MOS) transistor device is provided. The MOS transistor device includes a substrate, a gate structure, a spacer, a source/drain region and a barrier layer. The gate structure is disposed on the substrate. The gate structure includes a gate and a gate dielectric layer disposed between the gate and the substrate. The spacer is disposed on the sidewall of the gate structure. The source/drain region is disposed in the substrate on two sides of the spacer. The barrier layer is disposed around the source/drain region. The source/drain region and the barrier layer are fabricated using an identical material. However, the doping concentration of the source/drain region is larger than the doping concentration of the barrier layer.

Abstract: A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film by patterning the polycrystalline silicon film in an active cell area, a gate electrode is formed within the groove portion, and the inside of the groove portion is embedded in a gate wiring area. Extending to the outside of the groove portion continuously out of the groove portion, there is a gate drawing electrode electrically connected to the gate electrode. Slits extending from the end portion of the gate drawing electrode are formed in the gate drawing electrode outside of the groove portion. Then, a silicon oxide film and a BPSG film are deposited on the substrate.

Abstract: Methods of forming field effect transistors include the steps of forming a first electrically insulating layer on a semiconductor substrate having a plurality of trench isolation regions therein that define an active region therebetween. The first electrically insulating layer is then patterned to define a first plurality of openings therein that extend opposite the active region. A trench mask having a second plurality of openings therein is then formed by filling the first plurality of openings with electrically insulating plugs and then etching the patterned first electrically insulating layer using the electrically insulating plugs as an etching mask. A plurality of trenches are then formed in the active region by etching the semiconductor substrate using the trench mask as an etching mask. A plurality of insulated gate electrodes are then formed that extend into the plurality of trenches.

Abstract: An electrically conductive bit line layer is applied and patterned into portions arranged parallel to one another before the trench is etched into the semiconductor material, in which case, after the patterning of the bit line layer (3, 4) and before the etching of the trench, an implantation is introduced for the purpose of defining the position of the junctions, or, after the implantation of the n+-type well (19) for the source/drain regions, the bit line layer (3, 4) is patterned using an etching stop layer (2) arranged on the semiconductor body (1).

Abstract: The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements regarding the tolerances of the lithography in the gate contact plane are diminished.

Abstract: A semiconductor device provides a gate structure that includes a conductive portion and a high-k dielectric material formed beneath and along sides of the conductive material. An additional gate dielectric material such as a gate oxide may be used in addition to the high-k dielectric material. The method for forming the structure includes forming an opening in an organic material, forming the high-k dielectric material and a conductive material within the opening and over the organic material then using chemical mechanical polishing to remove the high-k dielectric material and conductive material from regions outside the gate region.

Abstract: A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portions reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.