Abstract: Provided are a DRAM semiconductor device and a method for fabricating the DRAM semiconductor device. The method provides forming a silicon epitaxial layer on a source/drain region of a cell region and a peripheral circuit region using selective epitaxial growth (SEG), thereby forming a raised active region. In addition, in the DRAM semiconductor device, a metal silicide layer and a metal pad are formed on the silicon epitaxial layer in the source/drain region of the cell region. By doing this, the DRAM device is capable of forming a source/drain region as a shallow junction region, reducing the occurrence of leakage current and lowering the contact resistance with the source/drain region.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: sequentially forming an oxide layer and a nitride layer on a substrate having a gate insulating layer and a gate formed in the order named thereon; forming a spacer at both sidewalls of the gate by etching the nitride layer; forming a source region and a drain region at both sides of the spacer in the substrate; removing the oxide layer formed on the gate and the substrate; partially removing surfaces of the gate, the source region and the drain region from which the oxide layer is removed; and depositing and thermally annealing a metal layer on the surfaces of the gate, source and drain whose surfaces are partially removed, to form a salicide layer.

Abstract: A transistor includes a gate insulating layer over a semiconductor substrate; a first insulating layer on both sides of the gate insulating layer; first spacers over the first insulating layer and being spaced apart from each other; and a gate conductive plug between the first spacers. A method for manufacturing a transistor includes sequentially depositing a first insulating layer and a second insulating layer over a semiconductor substrate; etching the second insulating layer; implanting impurity ions; depositing and etching a layer of spacer material to form first spacers; removing a first portion of the first insulating layer between the first spacers; depositing a gate insulating layer the place of the first portion of the first insulating layer; forming a gate conductive plug on the gate insulating layer; forming second spacers on sidewalls of the gate conductive plug; and forming a silicide on an upper surface of the gate conductive plug.

Abstract: A fabrication method of a semiconductor device includes: forming a gate insulating film and a gate electrode on an N type well; forming first source/drain regions by implanting a first element in regions of the N type well on both sides of the gate electrode, the first element being larger than silicon and exhibiting P type conductivity; forming second source/drain regions by implanting a second element in the regions of the N type well on the both sides of the gate electrode, the second element being smaller than silicon and exhibiting P type conductivity; and forming a metal silicide layer on the source/drain regions.

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Abstract: A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween, extension regions built up on the semiconductor substrate, and source/drain regions formed on the extension regions, wherein a first epitaxial layer is formed so as to fill up portions, cut out at the time of forming the side wall spacer, of the semiconductor substrate, and the extension regions are formed on the first epitaxial layer from a second epitaxial layer of a conduction type opposite to that of the first epitaxial layer.

Abstract: One embodiment relates to a method of forming an integrated circuit. In this method, at least one dopant species of a first conductivity type is implanted in a first manner along a first axis to form first pocket implant regions extending at least partially under some gates. At least one dopant species of the first conductivity type is then implanted in a second manner that differs from the first manner along a second axis that is laterally rotated with respect to the first axis to form second pocket implant regions extending at least partially under other gates.

Abstract: In a method for manufacturing a semiconductor device having an N-channel field effect transistor, the N-channel field effect transistor is formed by a process including the steps of forming a high dielectric constant gate insulating film on a substrate, forming a gate electrode on the high dielectric constant gate insulating film, forming an extension region by introducing N-type impurities into the substrate by using at least the gate electrode as a mask, and forming a pocket region by introducing P-type impurities under the extension region in the substrate by using at least the gate electrode as a mask. An amount of arsenic (As) that is introduced as the N-type impurities is in a range that is equal to or lower than a prescribed value that is determined based on a thickness of the high dielectric constant gate insulating film.

Abstract: A method of manufacturing a semiconductor device such as a MOS transistor. The device comprises a polysilicon gate (10) and doped regions (22,24) formed in a semiconductor substrate (12), separated by a channel region (26). The exposed surface of the semiconductor substrate is amorphized, by ion bombardment for example, so as to inhibit subsequent diffusion of the dopant ions during thermal annealing. Low thermal budgets are favoured for the activation and polysilicon regrowth to ensure an abrupt doping profile for the source/drain regions. As a consequence an upper portion (10b) of the gate electrode remains amorphous. The upper portion of the gate electrode is removed so as to allow a low resistance contact to be made with the polysilicon lower portion (10a).

Abstract: A semiconductor device and/or a method of manufacturing the same that may include: Forming a gate insulating film over a semiconductor substrate in a gate region. Forming a first gate pattern over the gate insulating film. Forming a second gate pattern over the first gate pattern, such that the second gate pattern is wider than the first gate pattern. Forming sidewall spacers at both sides of the first gate pattern and the second gate pattern, such that spaces are formed between the sidewall spacers and the first gate pattern below the second gate pattern.

Abstract: A plurality of nanowires is grown on a first substrate in a first direction perpendicular to the first substrate. An insulation layer covering the nanowires is formed on the first substrate to define a nanowire block including the nanowires and the insulation layer. The nanowire block is moved so that each of the nanowires is arranged in a second direction parallel to the first substrate. The insulation layer is partially removed to partially expose the nanowires. A gate line covering the exposed nanowires is formed. Impurities are implanted into portions of the nanowires adjacent to the gate line.

Abstract: A method for fabricating a metal oxide semiconductor (MOS) transistor comprises forming a source region of a first conductivity type and a drain region of the first conductivity type, which are separated from each other by a channel region, in upper regions of a semiconductor substrate, forming a gate stack on the channel region, and feeding hydrogen into junctions of the source and drain regions to neutralize dopants of the first conductivity type present within particular portions of the junctions.

Abstract: A MOSFET is disclosed that comprises a channel between a source extension and a drain extension, a dielectric layer over the channel, a gate spacer structure formed on a peripheral portion of the dielectric layer, and a gate formed on a non-peripheral portion of the dielectric layer, with at least a lower portion of the gate surrounded by and in contact with an internal surface of the gate spacer structure, and the gate is substantially aligned at its bottom with the channel. One method of forming the MOSFET comprises forming the dielectric layer, the gate spacer structure and the gate contact inside a cavity that has been formed by removing a sacrificial gate and spacer structure.

Abstract: A semiconductor device and a method for manufacturing the same includes forming a poly-gate including a first poly-gate portion and a second poly-gate portion on and/or over a semiconductor substrate, forming a trench having a predetermined depth in the poly-gate, implanting dopant ions into the entire surface of the semiconductor substrate and the poly-gate including the trench, forming a contact barrier layer to cover a portion of the poly-gate including the trench while exposing an upper surface of the remaining portion of the poly-gate on which a contact will be formed, and forming a contact on the exposed upper surface of the poly-gate.

Abstract: The present invention provides amorphous silicon thin-film transistors and methods of making such transistors for use with active matrix displays. In particular, one aspect of the present invention provides transistors having a structure based on a channel passivated structure wherein the amorphous silicon layer thickness and the channel length can be optimized. In another aspect of the present invention thin-film transistor structures that include a contact enhancement layer that can provide a low threshold voltage are provided.

Abstract: A method of forming compressive nitride film is provided. The method includes performing a chemical vapor deposition (CVD) process to form a nitride film on a substrate, and the method is characterized by adding a certain gas, selected from among Ar, N2, Kr, Xe, and mixtures thereof. Due to the addition of the foregoing certain gas, it can increase the compressive stress, thereby increasing PMOS drive current gain.

Abstract: A method of fabricating a flash memory device includes forming a stack electrode on a semiconductor substrate; forming a side spacer on a side wall of the stack electrode; forming a photo-resist film pattern with a predetermined thickness on the side wall of the side spacer; and forming a source/drain junction on the semiconductor substrate through ion implant using the photo-resist film as a mask for ion implant.

Abstract: A lateral-double diffused MOS device is provided. The device includes: a first well having a first conductive type and a second well having a second conductive type disposed in a substrate and adjacent to each other; a drain and a source regions having the first conductive type disposed in the first and the second wells, respectively; a field oxide layer (FOX) disposed on the first well between the source and the drain regions; a gate conductive layer disposed over the second well between the source and the drain regions extending to the FOX; a gate dielectric layer between the substrate and the gate conductive layer; a doped region having the first conductive type in the first well below a portion of the gate conductive layer and the FOX connecting to the drain region. A channel region is defined in the second well between the doped region and the source region.

Abstract: A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask member is removed. Source and drain regions are formed by implanting impurities into the surface layer of the semiconductor substrate on both sides of the gate electrode. It is possible to reduce variations of cross sectional shape of gate electrodes and set an impurity concentration of the gate electrode independently from an impurity concentration of the source and drain regions.

Abstract: A gate structure in a transistor and method for fabricating the structure. A gate structure is formed on a substrate. The gate structure includes three layers: an oxide layer, a nitride layer and a polysilicon layer. The oxide layer is located on the substrate, the nitride layer is located on the oxide layer, and the polysilicon layer is located on the nitride layer. The gate structure is reoxidized to form a layer of oxide over the gate structure.

Abstract: Ion sources and methods for generating molecular ions in a cold operating mode and for generating atomic ions in a hot operating mode are provided. In some embodiments, first and second electron sources are located at opposite ends of an arc chamber. The first electron source is energized in the cold operating mode, and the second electron source is energized in the hot operating mode. In other embodiments, electrons are directed through a hole in a cathode in the cold operating mode and are directed at the cathode in the hot operating mode. In further embodiments, an ion beam generator includes a molecular ion source, an atomic ion source and a switching element to select the output of one of the ion sources.

Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

Abstract: A method of forming a transistor including: forming a gate oxide layer pattern and gate polysilicon layer pattern on a silicon substrate; forming a low energy ion implantation region aligned with both sidewalls of the gate polysilicon layer pattern; forming an amorphous region at a lower part of both sidewalls of the gate polysilicon layer pattern; reducing a channel length by removing the amorphous region so as to form a notch at a lower part of both sidewalls of the gate polysilicon layer pattern; forming a gate spacer at both sidewalls of the gate polysilicon layer pattern; and forming a high energy ion implantation region by high energy ion implantation of source/drain impurities into an entire surface of the silicon substrate including the gate polysilicon layer pattern and gate spacer.

Abstract: A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

Abstract: Removing a portion of a structure in a semiconductor device to separate the structure. The structure has two portions of different heights. In one example, the structure is removed by forming a spacer over the lower portion adjacent to the sidewall of the higher portion. A second material is then formed on the structure outside of the spacer. The spacer is removed and the portion under the spacer is then removed to separate the structure at that location. In one embodiment, separate channel regions are implemented in the separated structures. In other embodiments, separate gate structures are implemented in the separated structures.

Abstract: A semiconductor device is formed on a semiconductor layer. A gate dielectric layer is formed over the semiconductor layer. A layer of gate material is formed over the gate dielectric layer. The layer of gate material is patterned to form a gate structure. Using the gate structure as a mask, an implant into the semiconductor layer is performed. To form a first patterned gate structure and a trench in the semiconductor layer surrounding a first portion and a second portion of the semiconductor layer and the gate, an etch through the gate structure and the semiconductor layer is performed. The trench is filled with insulating material.

Abstract: A CMOS device structure, and a method of fabricating the CMOS device, featuring a gate insulator layer comprised of a high k metal oxide layer, has been developed. The process features formation of recessed, heavily doped source/drain regions, and of vertical, polysilicon LDD spacers, prior to deposition of the high k metal oxide layer. Removal of a silicon nitride shape, previously used as a mask for definition of the recessed regions, which in turn are used for accommodation of the heavily doped source/drain regions, provides the space to be occupied by the high k metal oxide layer. The integrity of the high k, gate insulator layer, butted by the vertical polysilicon spacers, and overlying a channel region provided by the non-recessed portion of the semiconductor substrate, is preserved via delayed deposition of the metal oxide layer, performed after high temperature anneals such as the activation anneal for heavily doped source/drain regions, as well as the anneal used for metal silicide formation.

Abstract: A semiconductor device formed on a first conductive type substrate is provided. The device includes a gate, a second conductive type drain region, a second conductive type source region, and a second conductive type first lightly doped region. The gate is formed on the first conductive type substrate. The second conductive type drain region and the second conductive type source region are formed in the first conductive type substrate at both sides of the gate. The second conductive type first lightly doped region is formed in the first conductive type substrate between the gate and the second conductive type source region.

Abstract: A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the oxide film is formed by a plasma CVD process with a reduced plasma power such that the H2O content in the oxide film is less than about 2.4 wt %.

Abstract: A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the oxide film is formed by a plasma CVD process with a reduced plasma power such that the H2O content in the oxide film is less than about 2.4 wt %.

Abstract: In a method of manufacturing a semiconductor device to improve structural stability of a semiconductor device in a silicidation process, a substrate is provided to have an active region defined by an isolation layer. An etching mask is formed on the active region and the isolation layer to have a silicidation prevention pattern that at least partially exposes the active region. A gate structure is formed on the exposed active region. A gate spacer is formed on a sidewall of the gate structure positioned on the silicidation prevention pattern. Source/drain regions are formed on the active region using the gate spacer as a mask to thereby form the semiconductor device. Since voids may not be generated in a transistor of the semiconductor device or intrusion of the transistor may be prevented in the silicidation process, the semiconductor device including the transistor may have improved reliability and electrical characteristics.