With Heterojunction Gate (epo) Patents (Class 257/E21.448)
-
Patent number: 8536620Abstract: An integrated circuit including a hetero-interface and a manufacturing method thereof is disclosed. One embodiment includes forming a hetero-structure including a hetero-interface at a junction between a first region and a second region, and, thereafter introducing a material into the first region and at least up to the hetero-interface, wherein a diffusion constant of the material is higher in the first region than in the second region.Type: GrantFiled: September 30, 2008Date of Patent: September 17, 2013Assignee: Qimonda AGInventors: Henning Riechert, Walter Michael Weber
-
Patent number: 8338860Abstract: A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer.Type: GrantFiled: October 30, 2009Date of Patent: December 25, 2012Assignee: Alpha and Omega Semiconductor IncorporatedInventors: Anup Bhalla, Tinggang Zhu
-
Patent number: 8253168Abstract: Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.Type: GrantFiled: June 29, 2010Date of Patent: August 28, 2012Assignee: University of Utah Research FoundationInventors: Mark S. Miller, Justin B. Jackson, Divesh Kapoor, Justin Millis
-
Patent number: 8120072Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.Type: GrantFiled: July 24, 2008Date of Patent: February 21, 2012Assignee: Micron Technology, Inc.Inventor: Chandra Mouli
-
Publication number: 20110198669Abstract: The invention provides a transistor having a leak current between a source and drain in a nitride compound semiconductor formed on a substrate that is reduced. A gate electrode, a source electrode and a drain electrode are formed respectively on the surface of the nitride compound semiconductor formed on the silicon substrate in the transistor. At least one of the source electrode and the drain electrode is surrounded by an auxiliary electrode connected with the gate electrode. Because a depletion layer is formed in the nitride compound semiconductor under the auxiliary electrode, a route of the leak current is shut off and the leak current between the source and drain may be effectively reduced.Type: ApplicationFiled: February 12, 2010Publication date: August 18, 2011Applicant: Furukawa Electric Co., Ltd.Inventors: Shusuke Kaya, Nariaki Ikeda, Jiang Li
-
Patent number: 7952088Abstract: The present invention, in one embodiment, provides a semiconductor device including a substrate having an dielectric layer; at least one graphene layer overlying the dielectric layer; a back gate structure underlying the at least one graphene layer; and a semiconductor-containing layer present on the at least one graphene layer, the semiconductor-containing layer including a source region and a drain region separated by an upper gate structure, wherein the upper gate structure is positioned overlying the back gate structure.Type: GrantFiled: July 11, 2008Date of Patent: May 31, 2011Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
-
Publication number: 20110103148Abstract: A heterostructure field effect transistor (HFET) gallium nitride (GaN) semiconductor power device comprises a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The power device further comprises a source electrode and a drain electrode disposed on two opposite sides of a gate electrode disposed on top of the hetero-junction structure for controlling a current flow between the source and drain electrodes in the 2DEG layer.Type: ApplicationFiled: October 30, 2009Publication date: May 5, 2011Inventors: Anup Bhalla, Tinggang Zhu
-
Patent number: 7843006Abstract: A semiconductor component arrangement includes a power transistor and a temperature measurement circuit. The power transistor includes a gate electrode, a source zone, a drain zone and a body zone. The body zone is arranged in a first semiconductor zone of a first conduction type. The temperature measuring circuit comprises a temperature-dependent resistor and an evaluation circuit coupled to the temperature-dependent resistor. The resistor is formed by a portion of said first semiconductor zone.Type: GrantFiled: February 1, 2007Date of Patent: November 30, 2010Assignee: Infineon Technologies AGInventors: Rainald Sander, Markus Zundel
-
Patent number: 7795679Abstract: Device structures with a self-aligned damage layer and methods of forming such device structures. The device structure first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate. A third doped region of opposite conductivity type laterally separates the first doped region from the second doped region. A gate structure is disposed on a top surface of the substrate and has a vertically stacked relationship with the third doped region. A first crystalline damage layer is defined within the semiconductor material of the substrate. The first crystalline damage layer has a first plurality of voids surrounded by the semiconductor material of the substrate. The first doped region is disposed vertically between the first crystalline damage layer and the top surface of the substrate. The first crystalline damage layer does not extend laterally into the third doped region.Type: GrantFiled: July 24, 2008Date of Patent: September 14, 2010Assignee: International Business Machines CorporationInventors: Ethan H. Cannon, Fen Chen
-
Patent number: 7772056Abstract: Junction field effect transistors (JFETs) are shown to be a viable replacement for metal oxide semiconductor field effect transistors (MOSFETs) for gate lengths of less than about 40 nm, providing an alternative to the gate leakage problems presented by scaled down MOSFETs. Integrated circuit designs can have complementary JFET (CJFET) logic cells substituted for existing MOSFET-based logic cells to produce revised integrated circuit designs. Integrated circuits can include JFETS where the channel comprises a wide bandgap semiconductor material and the gate comprises a narrow bandgap semiconductor material. Mixtures of JFET and MOSFET transistors can be included on an integrated circuit design.Type: GrantFiled: June 18, 2008Date of Patent: August 10, 2010Assignee: University of Utah Research FoundationInventors: Mark S. Miller, Justin B. Jackson, Divesh Kapoor, Justin Millis
-
Publication number: 20100187569Abstract: A hetero-structure field effect transistor (HFET). The HFET may include a first contact and a second contact and a hetero-junction structure. The hetero-junction structure may include a first layer made from a first semiconductor material and a second layer made from a second semiconductor material. An interface at which the first layer and the second layer are in contact with each other may be provided, along which a two dimensional electron gas (2DEG) is formed in a part of the first layer directly adjacent to the interface, for propagating of electrical signals from the first contact to the second contact or vice versa. The transistor may further include a gate structure for controlling a conductance of the channel; a substrate layer made from a substrate semiconductor material, and a dielectric layer separating the first layer from the substrate layer. The second contact may include an electrical connection between the substrate layer and the first layer.Type: ApplicationFiled: May 16, 2008Publication date: July 29, 2010Applicant: Freescale Semiconductor, Inc.Inventor: Philippe Renaud
-
Publication number: 20100078681Abstract: An integrated circuit including a hetero-interface and a manufacturing method thereof is disclosed. One embodiment includes forming a hetero-structure including a hetero-interface at a junction between a first region and a second region, and, thereafter introducing a material into the first region and at least up to the hetero-interface, wherein a diffusion constant of the material is higher in the first region than in the second region.Type: ApplicationFiled: September 30, 2008Publication date: April 1, 2010Applicant: QIMONDA AGInventors: Henning Riechert, Walter Michael Weber
-
Publication number: 20100019249Abstract: Devices and methods for providing JFET transistors with improved operating characteristics are provided. Specifically, one or more embodiments of the present invention relate to JFET transistors with a higher diode turn-on voltage. For example, one or more embodiments include a JFET with a doped silicon-carbide gate, while other embodiments include a JFET with a metal gate. One or more embodiments also relate to systems and devices in which the improved JFET may be employed, as well as methods of manufacturing the improved JFET.Type: ApplicationFiled: July 24, 2008Publication date: January 28, 2010Applicant: MICRON TECHNOLOGY, INC.Inventor: Chandra Mouli
-
Publication number: 20100006823Abstract: The present invention, in one embodiment, provides a semiconductor device including a substrate having an dielectric layer; at least one graphene layer overlying the dielectric layer; a back gate structure underlying the at least one graphene layer; and a semiconductor-containing layer present on the at least one graphene layer, the semiconductor-containing layer including a source region and a drain region separated by an upper gate structure, wherein the upper gate structure is positioned overlying the back gate structure.Type: ApplicationFiled: July 11, 2008Publication date: January 14, 2010Applicant: International Business Machines CorporationInventors: Brent A. Anderson, Edward J. Nowak
-
Patent number: 7473587Abstract: A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.Type: GrantFiled: January 5, 2005Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Anthony G. Domenicucci, Keith E. Fogel, Devendra K. Sadana
-
Publication number: 20090001422Abstract: There is provided a manufacturing method of a semiconductor apparatus, including forming an InGaP layer on a substrate, forming a gate electrode having a Ti layer and an Au layer by vapor deposition on an upper surface of the InGaP layer, further forming a GaAs layer on the upper surface of the InGaP layer in a region different from a region in which the gate electrode is formed, and further forming a source electrode and a drain electrode on an upper surface of the GaAs layer. When the gate electrode having the Ti and Au layers is formed on the upper surface of the InGaP layer, the Ti and Au layers are formed with a substrate temperature being set equal to or lower than 180° C.Type: ApplicationFiled: October 19, 2007Publication date: January 1, 2009Applicant: ADVANTEST CORPORATIONInventors: Junichi OKAYASU, Takuya OIZUMI
-
Publication number: 20080149965Abstract: A transistor includes: a first semiconductor layer and a second semiconductor layer with a first region and a second region, which are sequentially formed above a substrate; a first p-type semiconductor layer formed on a region of the second semiconductor layer other than the first and second regions; and a second p-type semiconductor layer formed on the first p-type semiconductor layer. The first p-type semiconductor layer is separated from a drain electrode by interposing therebetween a first groove having a bottom composed of the first region, and from a source electrode by interposing therebetween a second groove having a bottom composed of the second region.Type: ApplicationFiled: November 14, 2007Publication date: June 26, 2008Inventors: Kazuhiro KAIBARA, Masahiro HIKITA, Tetsuzo UEDA, Yasuhiro UEMOTO, Tsuyoshi TANAKA
-
Publication number: 20080093631Abstract: A semiconductor device has a substrate of one type of semiconductor material, such as silicon. A contact structure is formed on the substrate, and the contact structure is formed of a compound of a metal and a second type of semiconductor material, such as germanium. The contact structure according to embodiments of the present invention include a semiconductor material which a different semiconductor material forming the substrate. Higher or lower barrier height is obtained by embodiment of the invention. A method for forming a contact structure in which a substrate of one type of semiconductor material is provided. A layer of another different semiconductor material is formed on the substrate. A layer of metal is then formed on the layer of the other different semiconductor material. Upon annealing, a contact structure is formed on the substrate, which is a compound of the metal and the other different semiconductor material, onto the substrate.Type: ApplicationFiled: October 5, 2007Publication date: April 24, 2008Inventors: Dong Chi, Cheng Cheh Tan, Chee Chua