Abstract: A semiconductor pressure sensor includes: a first substrate; a buried insulating film laminated on the first substrate; a second substrate laminated on the buried insulating film; a plurality of electrodes including a lower electrode and at least two upper electrodes, the lower electrode being formed on the second substrate; and a piezoelectric film laminated on the lower electrode and having the upper electrodes formed thereon. In the sensor, there is removed at least a portion of a region of the first substrate corresponding to a region of the second substrate including the piezoelectric film and the electrodes.

Abstract: A manufacturing method of a multi-level non-volatile memory includes following steps. First, a tunneling dielectric layer and a charge storage layer are sequentially formed on the substrate. At least two stacked layers are formed on the charge storage layer. Every two stacked layers include an inter-gate dielectric layer, a control gate, and a cap layer in sequence. Next, the charge storage layer between the two stacked layers is removed to form a first trench. After spacers are formed at the sidewalls of the two stacked layers and of the first trench, the charge storage layer outside the two stacked layers is removed. Thereafter, a dielectric layer is formed on the substrate. An assist gate is formed between the two stacked layers and a select gate is respectively formed on the sidewalls outside the two stacked layers. A doped region is then formed in the substrate outside the two stacked layers.

Abstract: Oxide semiconductor thin film transistors (TFT) and methods of manufacturing the same are provided. The methods include forming a channel layer on a substrate, forming source and drain electrodes at opposing sides of the channel layer, and oxidizing a surface of the channel layer by placing an oxidizing material in contact with the surface of the channel layer, reducing carriers on the surface of the channel layer. Due to the oxidizing agent treatment of the surface of the channel layer, excessive carriers that are generated naturally, or during the manufacturing process, may be more effectively controlled.

Abstract: An oxide thin film transistor and a method of manufacturing the oxide TFT are provided. The oxide thin film transistor (TFT) including: a gate; a channel formed to correspond to the gate, and a capping layer having a higher work function than the channel; a gate insulator disposed between the gate and the channel; and a source and drain respectively contacting either side of the capping layer and the channel and partially on a top surface of the capping layer.

Abstract: A microelectronic device includes a thin film transistor having an oxide semiconductor channel and an organic polymer passivation layer formed on the oxide semiconductor channel.

Abstract: An integrated circuit that includes: providing a substrate including a support structure, a dielectric layer, and a variable thickness film processed to include the dielectric layer within a recess of the variable thickness film; forming a gate over the variable thickness film; and forming a channel and a source/drain within the variable thickness film.

Abstract: Provided is a zinc (Zn) oxide-based thin film transistor that may include a gate, a gate insulating layer on the gate, a channel including zinc oxide and may be on a portion of the gate insulating layer, and a source and drain contacting respective sides of the channel. The zinc (Zn) oxide-based thin film transistor may further include a recession in the channel between the source and the drain, and a zinc oxide-based etchant may be used to form the recession.

Abstract: The disclosed thin film transistor array panel includes an insulating substrate, a channel layer including an oxide formed on the insulating substrate. A gate insulating is layer formed on the channel layer and a gate electrode is formed on the gate insulating layer. An interlayer insulating layer is formed on the gate electrode and a data line formed on the interlayer insulating layer and includes a source electrode, wherein the data line is made of a first conductive layer and a second conductive layer. A drain electrode formed on the interlayer insulating layer, and includes the first conductive layer and the second conductive layer. A pixel electrode extends from the first conductive layer of the drain electrode and a passivation layer formed on the data line and the drain electrode. A spacer formed on the passivation layer.

Abstract: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and a source electrode and drain electrode formed under the semiconductor thin film so as to be electrically connected to the semiconductor thin film.

Abstract: A TFT includes a zinc oxide (ZnO)-based channel layer having a plurality of semiconductor layers. An uppermost of the plurality of semiconductor layers has a Zn concentration less than that of a lower semiconductor layer to suppress an oxygen vacancy due to plasma. The uppermost semiconductor layer of the channel layer also has a tin (Sn) oxide, a chloride, a fluoride, or the like, which has a relatively stable bonding energy against plasma. The uppermost semiconductor layer is relatively strong against plasma shock and less decomposed when being exposed to plasma, thereby suppressing an increase in carrier concentration.

Abstract: A method of making a thin film transistor comprising a zinc-oxide-containing semiconductor material and spaced apart first and second electrodes in contact with the material. The co-generation of high quality zinc oxide semiconductor films and contact electrodes is obtained, at low temperatures, using non-vacuum conditions, silver nanoparticles are deposited to form the source and drain and, upon heating, converted to conducting metal. Such an in-situ formation of the silver metal/zinc oxide interface provides superior transistor activity compared to evaporated silver.

Abstract: A ZnO-based thin film transistor (TFT) is provided herein, as is a method of manufacturing the TFT. The ZnO-based TFT has a channel layer that comprises ZnO and ZnCl, wherein the ZnCl has a higher bonding energy than ZnO with respect to plasma. The ZnCl is formed through the entire channel layer, and specifically is formed in a region near THE surface of the channel layer. Since the ZnCl is strong enough not to be decomposed when exposed to plasma etching gas, an increase in the carrier concentration can be prevented. The distribution of ZnCl in the channel layer, may result from the inclusion of chlorine (Cl) in the plasma gas during the patterning of the channel layer.

Abstract: Thin film transistors and organic light emitting displays using the same are provided. The thin film transistor may include a substrate, a semiconductor layer, a gate electrode, and source/drain electrodes on the substrate. The semiconductor layer is composed of a P-type semiconductor layer obtained by diffusing phosphorus into a zinc oxide semiconductor. The phosphorus is doped in the semiconductor layer to a concentration ranging from about 1×1014 to about 1×1018 cm?3.

Abstract: A thin film transistor includes a gate electrode; an active layer formed of an oxide and insulated from the gate electrode; and a source electrode and a drain electrode formed of an oxide on the active layer such that the source electrode and the drain electrode are insulated from the gate electrode and electrically connected to the active layer, wherein the active layer, the source and the drain electrode are formed using an atomic layer deposition (ALD) and an insitu process, and a root mean square (RMS) value of the surface roughness of the active layer which contacts with the source and drain electrodes is less than 1 nm in order to reduce the contact resistance between the active layer and the source and drain electrodes, a method of manufacturing the same, an organic light emitting display apparatus including the thin film transistor, and a method of manufacturing the same.

Abstract: A method for manufacturing a field-effect transistor includes the steps of forming a source electrode and a drain electrode each containing hydrogen or deuterium; forming an oxide semiconductor layer in which the electrical resistance is decreased if hydrogen or deuterium is added; and, causing hydrogen or deuterium to diffuse from the source electrode and the drain electrode to the oxide semiconductor layer.

Abstract: Provided are a thin film transistor (TFT) including a selectively crystallized channel layer, and a method of manufacturing the TFT. The TFT includes a gate, the channel layer, a source, and a drain. The channel layer is formed of an oxide semiconductor, and at least a portion of the channel layer contacting the source and the drain is crystallized. In the method of manufacturing the TFT, the channel layer is formed of an oxide semiconductor, and a metal component is injected into the channel layer so as to crystallize at least a portion of the channel layer contacting the source and the drain. The metal component can be injected into the channel layer by depositing and heat-treating a metal layer or by ion-implantation.

Abstract: The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.

Abstract: In accordance with the teachings of the present disclosure, methods and apparatus are provided for a semiconductor device having thin anti-reflective layer(s) operable to absorb radiation that may otherwise reflect off surfaces disposed inwardly from the anti-reflective layer(s). In a method embodiment, a method for manufacturing a semiconductor device includes forming a support structure outwardly from a substrate. The support structure has a first thickness and a first outer sidewall surface that is not parallel with the substrate. The first outer sidewall surface has a first minimum refractive index. The method further includes forming an anti-reflective layer outwardly from the first outer sidewall surface. The anti-reflective layer has: a second outer sidewall surface that is not parallel with the substrate, a second refractive index that is greater than the first minimum refractive index, and a second thickness that is less than the first thickness.

Abstract: Disclosed is a thin film transistor including a P-type semiconductor layer, and an organic light-emitting display device having the thin film transistor. The present invention provides a thin film transistor including a substrate, a semiconductor layer, and a gate electrode and a source/drain electrode formed on the substrate, wherein the semiconductor layer is composed of P-type ZnO:N layers through a reaction of a mono-nitrogen gas with a zinc precursor, and the ZnO:N layer includes an un-reacted impurity element at a content of 3 at % or less.

Abstract: A micro-electromechanical device includes a substrate, a first patterned conductive layer, a second patterned conductive layer and a first patterned blocking layer. The first patterned conductive layer is disposed on the substrate. The second patterned conductive layer is disposed on the first patterned conductive layer. The first patterned blocking layer is connected with the first patterned conductive layer and the second patterned conductive layer. In addition, a method of manufacturing the micro-electromechanical device is also disclosed.

Abstract: An accumulation-mode field effect transistor includes a drift region of a first conductivity type, channel regions of the first conductivity type over and in contact with the drift region, and gate trenches having sidewalls abutting the channel regions. The gate trenches extend into and terminate within the drift region. The transistor further includes a first plurality of silicon regions of a second conductivity type forming P-N junctions with the channel regions along vertical walls of the first plurality of silicon regions. The first plurality of silicon regions extend into the drift region and form P-N junctions with the drift region along bottoms of the first plurality of silicon regions.

Abstract: Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor may include a gate; a channel layer; a source and a drain, the source and the drain being formed of metal; and a metal oxide layer, the metal oxide layer being formed between the channel layer and the source and the drain. The metal oxide layer may have a gradually changing metal content between the channel layer and the source and the drain.

Abstract: Metal-semiconductor field-effect transistors (MESFETS) are provided. A MESFET is provided having a source region, a drain region and a gate. The gate is between the source region and the drain region. A p-type conductivity layer is provided beneath the source region, the p-type conductivity layer being self-aligned to the gate. Related methods of fabricating MESFETs are also provided herein.

Abstract: Example methods may provide a thin film etching method. Example thin film etching methods may include forming a Ga—In—Zn—O film on a substrate, forming a mask layer covering a portion of the Ga—In—Zn—O film, and etching the Ga—In—Zn—O film using the mask layer as an etch barrier, wherein an etching gas used in the etching includes chlorine. The etching gas may further include an alkane (CnH2n+2) and H2 gas. The chlorine gas may be, for example, Cl2, BCl3, and/or CCl3, and the alkane gas may be, for example, CH4.

Abstract: A self-aligned enhancement mode metal-oxide-compound semiconductor field effect transistor (10) includes a lower oxide layer that is a mixture of Ga2O, Ga2O3, and other gallium oxide compounds (30), and a second insulating layer that is positioned immediately on top of the gallium oxygen layer together positioned on upper surface (14) of a III-V compound semiconductor wafer structure (13). Together the lower gallium oxide compound layer and the second insulating layer form a gallium oxide gate insulating structure. The gallium oxide gate insulating structure and underlying compound semiconductor gallium arsenide layer (15) meet at an atomically abrupt interface at the surface of with the compound semiconductor wafer structure (14). The initial essentially gallium oxygen layer serves to passivate and protect the underlying compound semiconductor sure from the second insulating oxide layer. A refractory mal gate electrode layer (17) is positioned on upper surface (18) of the second insulating oxide layer.

Abstract: A technique for creating high quality Schottky barrier devices in doped (e.g., Li+) crystalline metal oxide (e.g., ZnO) comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/?50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. The size of the depletion region controls the thickness of the Schottky barrier. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated.

Abstract: In a nitride semiconductor based bipolar transistor, a contact layer formed so as to contact an emitter layer is composed of n-type InAlGaN quaternary mixed crystals, the emitter layer and the contact layer are selectively removed so that the barrier height with the emitter formed thereon is small, and the ohmic electrode contact resistance can be lowered on the InAlGaN quaternary mixed crystals, for example, so that a WSi emitter electrode becomes an eave. A base electrode is formed by a self-aligned process using the emitter electrode as a mask. By such a configuration, the distance between the emitter and the edge of the base electrode is sufficiently shortened, and the base resistance can be lowered. As a result, a bipolar transistor having favorable high-frequency characteristics can be realized.

Abstract: A thin film transistor used as a selection transistor for a three-dimensional stacking cross point memory and a method of manufacturing the thin film transistor are provided. The thin film transistor includes a substrate, a gate, a gate insulation layer, a channel, a source and a drain. The gate may be formed on a portion of the substrate. The gate insulation layer may be formed on the substrate and the gate. The channel includes ZnO and may be formed on the gate insulation layer over the gate. The source and the drain contact sides of the channel.

Abstract: A method for manufacturing a field-effect transistor includes the steps of forming a source electrode and a drain electrode each containing hydrogen or deuterium; forming an oxide semiconductor layer in which the electrical resistance is decreased if hydrogen or deuterium is added; and, causing hydrogen or deuterium to diffuse from the source electrode and the drain electrode to the oxide semiconductor layer.

Abstract: The invention provides a production method for an active matrix substrate in which a plurality of contact holes are formed by a one-mask process so as to reach metal films which are present at different depth positions in an insulating layer and are not evaporated by dry etching using a fluorine-containing gas. The method includes a step of performing dry etching using mixed gas of CHF3, CF4 and O2 to form the plurality of contact hole, a step of subjecting the plurality of contact holes to oxygen ashing, and a step of forming a transparent conductive film in the plurality of contact holes.