Radiation Treatment (epo) Patents (Class 257/E21.471)
  • Patent number: 11450526
    Abstract: The present disclosure is generally related to semiconductor devices, and more particularly to a dielectric material formed in semiconductor devices. The present disclosure provides methods for forming a dielectric material layer by a cyclic spin-on coating process. In an embodiment, a method of forming a dielectric material on a substrate includes spin-coating a first portion of a dielectric material on a substrate, curing the first portion of the dielectric material on the substrate, spin-coating a second portion of the dielectric material on the substrate, and thermal annealing the dielectric material to form an annealed dielectric material on the substrate.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Je-Ming Kuo, Yen-Chun Huang, Chih-Tang Peng, Tien-I Bao
  • Patent number: 10062562
    Abstract: According to the present invention, when a film is formed on a substrate, a film-forming rate or film quality is stabilized. There is provided a method of manufacturing a semiconductor device, including: (a) forming a film on a substrate by supplying at least a gas including hydroxyl group to the substrate in a process chamber while maintaining a temperature of an inside of the process chamber at a first temperature; (b) changing the temperature of the inside of the process chamber from the first temperature to a second temperature higher than the first temperature; and (c) maintaining the temperature of the inside of the process chamber at the second temperature at least in a state that the substrate is not in the process chamber.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: August 28, 2018
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Takaaki Noda, Kotaro Konno
  • Patent number: 8993444
    Abstract: Embodiments of the present invention generally relate to methods for lowering the dielectric constant of low-k dielectric films used in semiconductor fabrication. In one embodiment, a method for lowering the dielectric constant (k) of a low-k silicon-containing dielectric film, comprising exposing a porous low-k silicon-containing dielectric film to a hydrofluoric acid solution and subsequently exposing the low-k silicon-containing dielectric film to a silylation agent. The silylation agent reacts with Si—OH functional groups in the porous low-k dielectric film to increase the concentration of carbon in the low-k dielectric film.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: March 31, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Kelvin Chan, Jin Xu, Kang Sub Yim, Alexandros T. Demos
  • Patent number: 8936963
    Abstract: If an oxide semiconductor layer is crystallized by heat treatment without being covered with an inorganic insulating film, surface unevenness and the like are formed due to the crystallization, which may cause variation in electrical characteristics. Steps are performed in the following order: a second insulating film is formed on an oxide semiconductor layer over a substrate and then heat treatment is performed, instead of performing heat treatment during a period immediately after formation of the oxide semiconductor layer and immediately before formation of an inorganic insulating film including silicon oxide on the oxide semiconductor layer. The density of hydrogen included in the inorganic insulating film including silicon oxide is 5×1020/cm3 or more, and the density of nitrogen is 1×1019/cm3 or more.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: January 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Ohara, Toshinari Sasaki
  • Patent number: 8796069
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: August 5, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 8778813
    Abstract: An apparatus for plasma processing a substrate is provided. The apparatus comprises a processing chamber, a substrate support disposed in the processing chamber, a shield member disposed in the processing chamber below the substrate support, and a lid assembly coupled to the processing chamber. The lid assembly comprises a conductive gas distributor coupled to a power source, and an electrode separated from the conductive gas distributor and the chamber body by electrical insulators. The electrode is also coupled to a source of electric power. The substrate support is formed with a stiffness that permits very little departure from parallelism. The shield member thermally shields a substrate transfer opening in the lower portion of the chamber body. A pumping plenum is located below the substrate support processing position, and is spaced apart therefrom.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: July 15, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Ramprakash Sankarakrishnan, Ganesh Balasubramanian, Juan Carlos Rocha-Alvarez, Dale R. Du Bois, Mark Fodor, Jianhua Zhou, Amit Bansal, Mohamad A. Ayoub, Shahid Shaikh, Patrick Reilly, Deenesh Padhi, Thomas Nowak
  • Patent number: 8691623
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: February 3, 2010
    Date of Patent: April 8, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 8629069
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: January 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 8557719
    Abstract: A method for fabricating a semiconductor device, according to the present invention includes the steps of: preparing an SOI substrate, which comprises a semiconductor supporting layer, an oxide layer formed on the semiconductor supporting layer and an SOI layer formed on the oxide layer; forming a semiconductor device on the SOI layer; forming a passivation layer over the SOI substrate, the passivation layer allowing a UV light to pass through it; and applying a UV light to the SOI substrate after the step of forming the semiconductor device is completed.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: October 15, 2013
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventors: Wataru Shimizu, Ikuo Kurachi
  • Publication number: 20130265031
    Abstract: A nanogap sensor includes a first layer in which a micropore is formed; a graphene sheet disposed on the first layer and including a nanoelectrode region in which a nanogap is formed, the nanogap aligned with the micropore; a first electrode formed on the grapheme sheet; and a second electrode formed on the graphene sheet, wherein the first electrode and the second electrode are connected to respective ends of the nanoelectrode region.
    Type: Application
    Filed: September 6, 2012
    Publication date: October 10, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jeo-young SHIM, Tae-han JEON, Kun-sun EOM, Dong-ho LEE, Hee-jeong JEONG, Seong-ho CHO
  • Patent number: 8551893
    Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
    Type: Grant
    Filed: August 1, 2008
    Date of Patent: October 8, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Tatsuya Honda, Norihito Sone
  • Patent number: 8486753
    Abstract: Disclosed are a patterning method of a metal oxide thin film using nanoimprinting, and a manufacturing method of a light emitting diode (LED). The method for forming a metal oxide thin film pattern using nanoimprinting includes: coating a photosensitive metal-organic material precursor solution on a substrate; preparing a mold patterned to have a protrusion and depression structure; pressurizing the photosensitive metal-organic material precursor coating layer with the patterned mold; forming a cured metal oxide thin film pattern by heating the pressurized photosensitive metal-organic material precursor coating layer or by irradiating ultraviolet rays to the pressurized photosensitive metal-organic material precursor coating layer while being heated; and removing the patterned mold from the metal oxide thin film pattern, and selectively further includes annealing the metal oxide thin film pattern.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: July 16, 2013
    Assignee: Korea Institute of Machinery and Materials
    Inventors: Hyeong Ho Park, Jun Ho Jeong, Ki Don Kim, Dae Geun Choi, Jun Hyuk Choi, Ji Hye Lee, Soon Won Lee
  • Publication number: 20130168797
    Abstract: A thin film photovoltaic device includes a substrate and a first conductive layer coupled to the substrate. The first conductive layer includes at least one first groove extending through a first portion of the first conductive layer to a portion of the substrate. The device also includes at least one semiconductor layer coupled to a remaining portion of the first conductive layer and the portion of the substrate. The at least one semiconductor layer includes a plurality of non-overlapping vias, each via extending through a portion of the at least one semiconductor layer to a portion of the first conductive layer. The device further includes a second conductive layer coupled to a remaining portion of the at least one semiconductor layer and portions of the first conductive layer. The second conductive layer includes at least one second groove extending through a portion of the second conductive layer to a portion of the at least one semiconductor layer.
    Type: Application
    Filed: January 4, 2012
    Publication date: July 4, 2013
    Applicant: ESI-PyroPhotonics Lasers, Inc.
    Inventor: Matthew Rekow
  • Patent number: 8455322
    Abstract: Disclosed is an improved semiconductor structure (e.g., a silicon germanium (SiGe) hetero-junction bipolar transistor) having a narrow essentially interstitial-free SIC pedestal with minimal overlap of the extrinsic base. Also, disclosed is a method of forming the transistor which uses laser annealing, as opposed to rapid thermal annealing, of the SIC pedestal to produce both a narrow SIC pedestal and an essentially interstitial-free collector. Thus, the resulting SiGe HBT transistor can be produced with narrower base and collector space-charge regions than can be achieved with conventional technology.
    Type: Grant
    Filed: March 8, 2010
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Oleg Gluschenkov, Rajendran Krishnasamy, Kathryn T. Schonenberg
  • Publication number: 20130119377
    Abstract: By reducing the contact resistance between an oxide semiconductor film and a metal film, a transistor that uses an oxide semiconductor film and has excellent on-state characteristics is provided. A semiconductor device includes a pair of electrodes over an insulating surface; an oxide semiconductor film in contact with the pair of electrodes; a gate insulating film over the oxide semiconductor film; and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film interposed therebetween. In the semiconductor device, the pair of electrodes contains a halogen element in a region in contact with the oxide semiconductor film. Further, plasma treatment in an atmosphere containing fluorine can be performed so that the pair of electrodes contains the halogen element in a region in contact with the oxide semiconductor film.
    Type: Application
    Filed: November 5, 2012
    Publication date: May 16, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Semiconductor Energy Laboratory Co., Ltd.
  • Publication number: 20130099228
    Abstract: A passivation layer solution composition is provided. A passivation layer solution composition according to an exemplary embodiment of the present invention includes an organic siloxane resin represented by Chemical Formula 1 below. In Chemical Formula 1, R is at least one substituent selected from a saturated hydrocarbon or an unsaturated hydrocarbon having from 1 to about 25 carbon atoms, and x and y may each independently be from 1 to about 200, and wherein each wavy line indicates a bond to an H atom or to an x siloxane unit or a y siloxane unit, or a bond to an x siloxane unit or a y siloxane unit of another siloxane chain comprising x siloxane units or y siloxane units or a combination thereof.
    Type: Application
    Filed: June 27, 2012
    Publication date: April 25, 2013
    Inventors: Byung Du Ahn, Seung Ho Yeon, Sei-Yong Park, Mi-Hyae Park, Bu Sop Song, Tae Gweon Lee, Jun Hyun Park, Je Hun Lee, Jae Woo Park
  • Publication number: 20130043466
    Abstract: A semiconductor device including an oxide semiconductor and including a more excellent gate insulating film is provided. A highly reliable and electrically stable semiconductor device having a small number of changes in the film structure, the process conditions, the manufacturing apparatus, or the like from a mass production technology that has been put into practical use is provided. A method for manufacturing the semiconductor device is provided. The semiconductor device includes a gate electrode, a gate insulating film formed over the gate electrode, and an oxide semiconductor film formed over the gate insulating film. The gate insulating film includes a silicon nitride oxide film, a silicon oxynitride film formed over the silicon nitride oxide film, and a metal oxide film formed over the silicon oxynitride film. The oxide semiconductor film is formed over and in contact with the metal oxide film.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 21, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Masafumi NOMURA, Kenichi OKAZAKI, Toshiyuki MIYAMOTO, Takashi HAMOCHI, Shunpei YAMAZAKI
  • Publication number: 20130023096
    Abstract: Semiconductor devices and methods for making such devices are described. The UMOS semiconductor devices contain single-crystal gates that have been re-grown or formed at low temperature using microwaves. The devices can be formed by providing a semiconductor substrate, forming a trench in the substrate, forming an insulating layer in the trench, depositing a pre-gate layer on the insulating layer, the pre-gate layer comprising a conductive and/or semiconductive material (Si or SiGe) with a non-single crystal structure, contacting the pre-gate layer with a seed layer with a single-crystal structure, and heating the pre-gate layer using microwaves at low temperatures to recrystallize the non-single crystal structure into a single-crystal structure. These processes can improve the resistance and mobility of the gate either as a single crystal structure, optionally with a silicide contact above the source-well junction, enabling a higher switching speed UMOS device. Other embodiments are described.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 24, 2013
    Inventors: Robert J. Purtell, Steve Sapp
  • Patent number: 8328494
    Abstract: A vacuum assembly used for warming processed substrates above the dew point to prevent unwanted moisture on the processed substrate surfaces as well as reducing negative impact on manufacturing throughput. The vacuum assembly includes a processing chamber, a substrate handling robot, and a heater which may be an optical heater. The processing chamber is configured to cryogenically process one or more substrates. The transfer chamber is connected to the processing chamber and houses the substrate handling robot. The substrate handling robot is configured to displace one or more substrates from the processing chamber to the transfer chamber. The heater is connected to the transfer chamber above the substrate handling robot such that the heater emits energy incident on the substrate when the substrate handling robot displaces the substrate in the transfer chamber.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: December 11, 2012
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Roger B. Fish, Jeffrey E. Krampert
  • Patent number: 8329506
    Abstract: It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO3(ZnO)m (m=1) are included in an amorphous structure represented by InGaO3(ZnO)m (m>0).
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: December 11, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Junichiro Sakata, Takuya Hirohashi, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga
  • Publication number: 20120295397
    Abstract: Stable electrical characteristics and high reliability are provided to a semiconductor device including an oxide semiconductor. In a process of manufacturing a transistor including an oxide semiconductor film, an amorphous oxide semiconductor film is formed, and oxygen is added to the amorphous oxide semiconductor film, so that an amorphous oxide semiconductor film containing excess oxygen is formed. Then, an aluminum oxide film is formed over the amorphous oxide semiconductor film, and heat treatment is performed thereon to crystallize at least part of the amorphous oxide semiconductor film, so that a crystalline oxide semiconductor film is formed.
    Type: Application
    Filed: May 9, 2012
    Publication date: November 22, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Junichi KOEZUKA, Yuhei SATO, Shunpei YAMAZAKI
  • Patent number: 8309421
    Abstract: The present invention generally relates to methods of controlling UV lamp output to increase irradiance uniformity. The methods generally include determining a baseline irradiance within a chamber, determining the relative irradiance on a substrate corresponding to a first lamp and a second lamp, and determining correction or compensation factors based on the relative irradiances and the baseline irradiance. The lamps are then adjusted via closed loop control using the correction or compensation factors to individually adjust the lamps to the desired output. The lamps may optionally be adjusted to equal irradiances prior to adjusting the lamps to the desired output. The closed loop control ensures process uniformity from substrate to substrate. The irradiance measurement and the correction or compensation factors allow for adjustment of lamp set points due to chamber component degradation, chamber component replacement, or chamber cleaning.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: November 13, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Yao-Hung Yang, Abhijit Kangude, Sanjeev Baluja, Michael Martinelli, Liliya Krivulina, Thomas Nowak, Juan Carlos Rocha-Alvarez, Scott Hendrickson
  • Publication number: 20120244659
    Abstract: A method for forming an oxide semiconductor film having favorable semiconductor characteristics is provided. In addition, a method for manufacturing a semiconductor device having favorable electric characteristics, with use of the oxide semiconductor film is provided. A method for forming an oxide semiconductor film including the steps of forming an oxide semiconductor film, forming a hydrogen permeable film over and in contact with the oxide semiconductor film, forming a hydrogen capture film over and in contact with the hydrogen permeable film, and releasing hydrogen from the oxide semiconductor film by performing heat treatment. Further, in a method for manufacturing a semiconductor device, the method for forming an oxide semiconductor film is used.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 27, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yuki IMOTO, Tetsunori MARUYAMA, Toru TAKAYAMA
  • Publication number: 20120231580
    Abstract: In a manufacturing process of a transistor including an oxide semiconductor film, oxygen doping treatment is performed on the oxide semiconductor film, and then heat treatment is performed on the oxide semiconductor film and an aluminum oxide film provided over the oxide semiconductor film. Consequently, an oxide semiconductor film which includes a region containing more oxygen than a stoichiometric composition is formed. The transistor formed using the oxide semiconductor film can have high reliability because the amount of change in the threshold voltage of the transistor by a bias-temperature stress test (BT test) is reduced.
    Type: Application
    Filed: March 7, 2012
    Publication date: September 13, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Yuhei SATO, Keiji SATO, Tetsunori MARUYAMA, Junichi KOEZUKA
  • Patent number: 8232552
    Abstract: This invention provides an amorphous oxide semiconductor thin film, which is insoluble in a phosphoric acid-based etching solution and is soluble in an oxalic acid-based etching solution by optimizing the amounts of indium, tin, and zinc, a method of producing the amorphous oxide semiconductor thin film, etc. An image display device (1) comprises a glass substrate (10), a liquid crystal (40) as a light control element, a bottom gate-type thin film transistor (1) for driving the liquid crystal (40), a pixel electrode (30), and an opposing electrode (50). The amorphous oxide semiconductor thin film (2) in the bottom gate-type thin film transistor (1) has a carrier density of less than 10+18 cm?3, is insoluble in a phosphoric acid-based etching liquid, and is soluble in an oxalic acid-based etching liquid.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: July 31, 2012
    Assignee: Idemitsu Kosan Co., Ltd.
    Inventors: Koki Yano, Kazuyoshi Inoue
  • Patent number: 8216861
    Abstract: Methods for the repair of damaged low k films are provided. Damage to the low k films occurs during processing of the film such as during etching, ashing, and planarization. The processing of the low k film causes water to store in the pores of the film and further causes hydrophilic compounds to form in the low k film structure. Repair processes incorporating ultraviolet (UV) radiation and carbon-containing compounds remove the water from the pores and further remove the hydrophilic compounds from the low k film structure.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: July 10, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Kang Sub Yim, Thomas Nowak, Bo Xie, Alexandros T. Demos
  • Publication number: 20110269297
    Abstract: The invention can be used for producing different luminescent materials and as a basis for producing subminiature light-emitting diodes, white light sources, single-electron transistors, nonlinear optical devices and photosensitive and photovoltaic devices. The inventive method for producing semiconductor quantum dots involves synthesizing nanocrystal nuclei from a chalcogen-containing precursor and a precursor containing a group II or IV metal using an organic solvent and a surface modifier. The method is characterized in that (aminoalkyl)trialkoxysilanes are used as the surface modifier , core synthesis is carried out at a permanent temperature ranging from 150 to 250 C for 15 seconds to 1 hour and in that the reaction mixture containing the nanoclystal is additionally treated by UV-light for 1-10 minutes and by ultrasound for 5-15 minutes.
    Type: Application
    Filed: August 18, 2009
    Publication date: November 3, 2011
    Applicant: FEDERALNOE GOSUDARSTVENNOE UNITARNOE PREDPRIATIE "NAUCHNO-ISSLEDOVATELSKIY
    Inventors: Roman Vladimirovich Novichkov, Maxim Sergeevich Wakstein, Ekaterina Leonidovna Nodova, Aleksey Olegovich Maniashin, Irina Ivanovna Taraskina
  • Patent number: 8017528
    Abstract: A thermal cycle includes: increasing a temperature from an initial temperature to a temperature T1 at an arbitrary rate R1 (° C./sec); holding the temperature at the temperature T1 for an arbitrary period t1 (sec); increasing the temperature from the temperature T1 to a temperature T2 at a rate R2 (° C./sec) of 1.0×107 (° C./sec) or less; and holding the temperature at the temperature T2 for a period t2 (sec) of 50 msec or less. The thermal cycle thereafter includes: decreasing the temperature from the temperature T2 to the temperature T1 at a rate R1? (° C./sec) of 1.0×107 (° C./sec) or less; holding the temperature T1 for an arbitrary period t3 (sec); and decreasing the temperature from the temperature T1 to a final temperature at an arbitrary rate R2? (° C./sec). Such a thermal cycle is successively repeated in a plurality of iterations.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: September 13, 2011
    Assignee: Panasonic Corporation
    Inventors: Kenji Yoneda, Kazuma Takahashi
  • Patent number: 7977256
    Abstract: A method of forming a porous low dielectric constant (low-k) dielectric film on a substrate is described, wherein the dielectric constant of the low-k dielectric film is less than a value of approximately 4. The method comprises exposing the low-k dielectric film to infrared (IR) radiation and adjusting a residual amount of cross-linking inhibitor, such as pore-generating material, within the low-k dielectric film.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: July 12, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Junjun Liu, Dorel I. Toma, Eric M. Lee
  • Publication number: 20110151646
    Abstract: The present invention provides a microwave annealing method for a plastic substrate. The method comprises pulsed microwave annealing to an organic photo-voltaic device to avoid warpage and degradation of the plastic substrate. Utilizing pulsed microwave annealing method can improve the wettability of the organic layer on the plastic substrate verified by contact angle measurement, and achieving the organic solar cell fabricated with higher power conversion efficiency.
    Type: Application
    Filed: October 6, 2010
    Publication date: June 23, 2011
    Inventors: Sheng-Fu Horng, Jen-Chun Wang, Tse-Pan Yang, Ming-Kun Lee, Tarng-Shiang Hu, Hsin-Fei Meno
  • Publication number: 20110143461
    Abstract: A vacuum assembly used for warming processed substrates above the dew point to prevent unwanted moisture on the processed substrate surfaces as well as reducing negative impact on manufacturing throughput. The vacuum assembly includes a processing chamber, a substrate handling robot, and a heater which may be an optical heater. The processing chamber is configured to cryogenically process one or more substrates. The transfer chamber is connected to the processing chamber and houses the substrate handling robot. The substrate handling robot is configured to displace one or more substrates from the processing chamber to the transfer chamber. The heater is connected to the transfer chamber above the substrate handling robot such that the heater emits energy incident on the substrate when the substrate handling robot displaces the substrate in the transfer chamber.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 16, 2011
    Applicant: Varian Semiconductor equipment Associates, Inc.
    Inventors: Roger B. Fish, Jeffrey E. Krampert
  • Patent number: 7955995
    Abstract: An object is to provide a technique to manufacture an insulating film having excellent film characteristics. In particular, an object is to provide a technique to manufacture a dense insulating film with a high withstand voltage. Moreover, an object is to provide a technique to manufacture an insulating film with few electron traps. An insulating film including oxygen is subjected to plasma treatment using a high frequency under the conditions where the electron density is 1×1011 cm?3 or more and the electron temperature is 1.5 eV or less in an atmosphere including oxygen.
    Type: Grant
    Filed: May 18, 2007
    Date of Patent: June 7, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuya Kakehata, Tetsuhiro Tanaka, Yoshinobu Asami
  • Patent number: 7928021
    Abstract: A system for and method of processing, i.e., annealing semiconductor materials. By controlling the time, frequency, variance of frequency, microwave power density, wafer boundary conditions, ambient conditions, and temperatures (including ramp rates), it is possible to repair localized damage lattices of the crystalline structure of a semiconductor material that may occur during the ion implantation of impurities into the material, electrically activate the implanted dopant, and substantially minimize further diffusion of the dopant into the silicon. The wafer boundary conditions may be controlled by utilizing susceptor plates (4) or a water chill plate (12). Ambient conditions may be controlled by gas injection (10) within the microwave chamber (3).
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: April 19, 2011
    Assignee: DSGI, Inc.
    Inventors: Jeffrey Michael Kowalski, Jeffrey Edward Kowalski
  • Patent number: 7867926
    Abstract: A substrate processing apparatus is used for radiating UV rays onto a target film formed on a target surface of a substrate to perform a curing process of the target film. The apparatus includes a hot plate configured to heat the substrate to a predetermined temperature, a plurality of support pins disposed on the hot plate to support the substrate, and a UV radiating device configured to radiate UV rays onto the target surface of the substrate supported on the support pins. The support pins are preset to provide a predetermined thermal conductivity to conduct heat of the substrate to the hot plate. The hot plate is preset to have a predetermined thermal capacity sufficient to absorb heat conducted through the support pins.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: January 11, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Naoyuki Satoh, Takeshi Tamura, Hiroyuki Ide, Manabu Hama
  • Publication number: 20100304576
    Abstract: A chamber for annealing a semi-conductor material of II-VI type having a first area for storing an element of group II of the periodic table and a second area designed to receive the semi-conductor material of II-VI type. The chamber s equipped with a separating partition at the level of an intermediate area. This separating partition is provided with a passage aperture equipped with gas anti-reverse flow means to ensure one-way passage of the element of group II of the periodic table, in vapor phase, from the first area to the second area. This chamber is heated by heating means enabling the two areas to be heated independently.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 2, 2010
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent Mollard, Guillaume Bourgeois, Franck Henry, Bernard Pelliciari
  • Patent number: 7790633
    Abstract: A silicon dioxide-based dielectric layer is formed on a substrate surface by a sequential deposition/anneal technique. The deposited layer thickness is insufficient to prevent substantially complete penetration of annealing process agents into the layer and migration of water out of the layer. The dielectric layer is then annealed, ideally at a moderate temperature, to remove water and thereby fully densify the film. The deposition and anneal processes are then repeated until a desired dielectric film thickness is achieved.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: September 7, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Raihan M. Tarafdar, George D. Papasouliotis, Ron Rulkens, Dennis M. Hausmann, Jeff Tobin, Adrianne K. Tipton, Bunsen Nie
  • Publication number: 20100085081
    Abstract: To provide an enhancement-depletion (E/D) inverter which can be easily manufactured, in the present invention, a method of manufacturing an inverter which is composed of an oxide semiconductor in which a channel layer includes at least one element selected from In, Ga and Zn formed on a same substrate, the inverter being the E/D inverter having plural thin film transistors, is characterized by comprising the steps of: forming a first transistor and a second transistor, the thicknesses of the channel layers of the first and second transistors being mutually different; and executing heat treatment to at least one of the channel layers of the first and second transistors.
    Type: Application
    Filed: May 15, 2008
    Publication date: April 8, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Masato Ofuji, Katsumi Abe, Ryo Hayashi, Masafumi Sano, Hideya Kumomi
  • Publication number: 20100081294
    Abstract: A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error.
    Type: Application
    Filed: September 1, 2009
    Publication date: April 1, 2010
    Inventors: Ryuji OGAWA, Masahiro Miyairi, Shimon Maeda, Suigen Kyoh, Satoshi Tanaka
  • Patent number: 7649216
    Abstract: The present invention relates to radiation hardening by design (RHBD), which employs layout and circuit techniques to mitigate the damaging effects of ionizing radiation. Reverse body biasing (RBB) of N-type metal-oxide-semiconductor (NMOS) transistors may be used to counteract the effects of trapped positive charges in isolation oxides due to ionizing radiation. In a traditional MOS integrated circuit, input/output (I/O) circuitry may be powered using an I/O power supply voltage, and core circuitry may be powered using a core power supply voltage, which is between the I/O power supply voltage and ground. However, in one embodiment of the present invention, the core circuitry is powered using a voltage difference between the core power supply voltage and the I/O power supply voltage. The bodies of NMOS transistors in the core circuitry are coupled to ground; therefore, a voltage difference between the core power supply voltage and ground provides RBB.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: January 19, 2010
    Assignee: Arizona Board of Regents for and on behalf of Arizona State University
    Inventors: Lawrence T. Clark, Karl C. Mohr, Keith E. Holbert
  • Publication number: 20090275212
    Abstract: A semiconductor wafer implanted with impurities is loaded into a chamber. After oxygen gas is introduced around the semiconductor wafer, the semiconductor wafer is irradiated with a flash of light from flash lamps for an irradiation time not shorter than 0.1 milliseconds and not longer than 100 milliseconds, to thereby momentarily raise the surface temperature of the semiconductor wafer up to not lower than 800° C. and not higher than 1300° C. Since the temperature rises in an extremely short time, it is possible to activate the impurities while suppressing thermal diffusion thereof. Further, since an extremely thin oxide film is formed on a surface of the semiconductor wafer, this film serves as a protection film in a subsequent cleaning process, to prevent removal of the impurities.
    Type: Application
    Filed: March 16, 2009
    Publication date: November 5, 2009
    Inventor: Shinichi KATO
  • Patent number: 7579285
    Abstract: The invention is related to an ALD method for depositing a layer including the steps of a) providing a semiconductor substrate in a reactor; b) providing a pulse of a first precursor gas into the reactor; c) providing a pulse of a second precursor gas into the reactor; d) providing an inert atmosphere in the reactor; and e) repeating step b) through step d), wherein at least once during step d) the semiconductor substrate is exposed to UV irradiation.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: August 25, 2009
    Assignee: IMEC
    Inventors: Paul Zimmerman, Matty Caymax, Stefan De Gendt, Annelies Delabie, Lars-Ake Ragnarsson
  • Patent number: 7569503
    Abstract: Embodiments of the present invention are provided for improved contact doping and annealing systems and processes. In embodiments, a plasma ion immersion implantation (PIII) process is used for contact doping of nanowires and other nanoelement based thin film devices. According to further embodiments of the present invention, pulsed laser annealing using laser energy at relatively low laser fluences below about 100 mJ/cm2 (e.g., less than about 50 mJ/cm2, e.g., between about 2 and 18 mJ/cm2) is used to anneal nanowire and other nanoelement-based devices on substrates, such as low temperature flexible substrates, e.g., plastic substrates.
    Type: Grant
    Filed: November 10, 2005
    Date of Patent: August 4, 2009
    Assignee: Nanosys, Inc.
    Inventors: Yaoling Pan, David P. Stumbo
  • Patent number: 7569458
    Abstract: A method of non-thermal annealing of a silicon wafer comprising irradiating a doped silicon wafer with electromagnetic radiation in a wavelength or frequency range coinciding with lattice phonon frequencies of the doped semiconductor material. The wafer is annealed in an apparatus including a cavity and a radiation source of a wavelength ranging from 10-25 ?m and more particularly 15-18 ?m, or a frequency ranging from 12-30 THz and more particularly 16.5-20 THz.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: August 4, 2009
    Assignee: Atmel Corporation
    Inventors: Bohumil Lojek, Michael D. Whiteman
  • Publication number: 20090184399
    Abstract: A system for and method of processing, i.e., annealing semiconductor materials. By controlling the time, frequency, variance of frequency, microwave power density, wafer boundary conditions, ambient conditions, and temperatures (including ramp rates), it is possible to repair localized damage lattices of the crystalline structure of a semiconductor material that may occur during the ion implantation of impurities into the material, electrically activate the implanted dopant, and substantially minimize further diffusion of the dopant into the silicon. The wafer boundary conditions may be controlled by utilizing susceptor plates (4) or a water chill plate (12). Ambient conditions may be controlled by gas injection (10) within the microwave chamber (3).
    Type: Application
    Filed: September 17, 2008
    Publication date: July 23, 2009
    Inventors: Jeffrey Michael Kowalski, Jeffrey Edward Kowalski
  • Patent number: 7560354
    Abstract: A process can include forming a doped semiconductor layer over a substrate. The process can also include performing an action that reduces a dopant content along an exposed surface of a workpiece that includes the substrate and the doped semiconductor layer. The action is performed after forming the doped semiconductor layer and before the doped semiconductor layer is exposed to a room ambient. In particular embodiments, the doped semiconductor layer includes a semiconductor material that includes a combination of at least two elements selected from the group consisting of C, Si, and Ge, and the doped semiconductor layer also includes a dopant, such as phosphorus, arsenic, boron, or the like. The action can include forming an encapsulating layer, exposing the doped semiconductor layer to radiation, annealing the doped semiconductor layer, or any combination thereof.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: July 14, 2009
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Stefan Zollner, Bich-Yen Nguyen
  • Patent number: 7553778
    Abstract: A method for producing a semiconductor device includes irradiating an amorphous semiconductor film on an insulating material with a pulsed laser beam having a rectangular irradiation area, while scanning in a direction intersecting a longitudinal direction of the irradiation area, thereby forming a first polycrystalline semiconductor film, and irradiating a part of the amorphous semiconductor film with the laser beam, while scanning in a longitudinal direction intersecting the irradiation area, the part superposing the first polycrystalline semiconductor film and being adjacent to the first polycrystalline semiconductor film, thereby forming a second polycrystalline semiconductor film. The laser beam has a wavelength in a range from 390 nm to 640 nm, and the amorphous semiconductor film has a thickness in a range from 60 nm to 100 nm.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: June 30, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazuyuki Sugahara, Naoki Nakagawa, Atsuhiro Sono, Shinsuke Yura, Kazushi Yamayoshi
  • Publication number: 20090093134
    Abstract: Low dielectric constant materials are cured in a process chamber during semiconductor processing. The low dielectric constant materials are cured by irradiation with UV light. The atmosphere in the process chamber has a CO2 concentration of about 1-16% by volume during the irradiation. The CO2 limits the formation of —Si—H and —Si—OH groups in the low dielectric constant material, thereby reducing the occurrence of moisture absorption and oxidation in the low dielectric constant material.
    Type: Application
    Filed: October 5, 2007
    Publication date: April 9, 2009
    Applicant: ASM Japan K.K
    Inventors: Kiyohiro Matsushita, Kenichi Kagami
  • Patent number: 7510964
    Abstract: The invention is directed to a method for manufacturing semiconductor device. The method comprises steps of providing a substrate and then forming a dielectric material-containing device over the substrate. A plasma vapor deposition process is performed to form a dielectric layer over the substrate. A first baking process is performed.
    Type: Grant
    Filed: January 26, 2006
    Date of Patent: March 31, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Jen Mao, Kuo-Wei Yang, Hui-Shen Shih, Chun-Han Chuang
  • Publication number: 20080093709
    Abstract: A semiconductor substrate in a state that an inter-layer insulation film is formed is loaded in a chamber, air in the chamber is purged by introducing a large amount of a nitrogen gas in the chamber, and an atmospheric gas in the chamber is substituted with a nitrogen gas. After that, UV cure is performed by introducing a small amount of an oxygen gas adjusted to an atmospheric pressure or a little more positive pressure in the chamber by nitrogen purge. For the introduction of an oxygen gas, an oxygen gas is introduced while controlling the flow rate by using a flow meter, and adjustment is performed using the flow meter so that the oxygen concentration in the chamber becomes a constant value in the range of 5 ppm to 400 ppm.
    Type: Application
    Filed: October 19, 2007
    Publication date: April 24, 2008
    Inventors: Masazumi Matsuura, Kinya Goto, Hisashi Yano, Kotaro Nomura
  • Publication number: 20060258064
    Abstract: A method of forming poly-silicon thin film transistors is described. An amorphous silicon thin film transistor is formed on a substrate, and then the Infrared (IR) heating process is used. A gate metal and source/drain metal are heated rapidly, and conduct heat energy to an amorphous silicon layer. Next, crystallization occurs in the amorphous silicon layer to form poly-silicon. Therefore a poly-silicon thin film transistor is produced.
    Type: Application
    Filed: June 30, 2006
    Publication date: November 16, 2006
    Inventors: Chi-Lin Chen, Shun-Fa Huang, Liang-Tang Wang