Abstract: In one embodiment, a method of forming a via includes forming an first opening in the semiconductor substrate, wherein the first opening has a bottom and sidewalls, forming a sacrificial fill in the first opening, forming a dielectric layer over the sacrificial fill, forming a second opening in the dielectric layer, wherein the second opening is over the sacrificial fill, removing the sacrificial fill from the first opening after forming the second opening, and forming a conductive material in the first opening and second opening.

Abstract: The structure and method of formation of an integrated CMOS level and active device level that can be a memory device level. The integration includes the formation of a “super-flat” interface between the two levels formed by the patterning of a full complement of active and dummy interconnecting vias using two separate patterning and etch processes. The active vias connect memory devices in the upper device level to connecting pads in the lower CMOS level. The dummy vias may extend up to an etch stop layer formed over the CMOS layer or may be stopped at an intermediate etch stop layer formed within the device level. The dummy vias thereby contact memory devices but do not connect them to active elements in the CMOS level.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A method for fabricating a semiconductor device with improved performance is disclosed. The method comprises providing a semiconductor substrate; forming one or more gate stacks having an interfacial layer, a high-k dielectric layer, and a gate layer over the substrate; and performing at least one treatment on the interfacial layer, wherein the treatment comprises a microwave radiation treatment, an ultraviolet radiation treatment, or a combination thereof.

Abstract: A method for forming a semiconductor device is provided. In one embodiment, the method includes providing a semiconductor substrate with a surface region. The surface region includes one or more layers overlying the semiconductor substrate. In addition, the method includes depositing a dielectric layer overlying the surface region. The dielectric layer is formed by a CVD process. Furthermore, the method includes forming a diffusion barrier layer overlying the dielectric layer. In addition, the method includes forming a conductive layer overlying the diffusion barrier layer. Additionally, the method includes reducing the thickness of the conductive layer using a chemical-mechanical polishing process. The CVD process utilizes fluorine as a reactant to form the dielectric layer. In addition, the dielectric layer is associated with a dielectric constant equal or less than 3.3.

Abstract: A peeling prevention layer for preventing an insulation film and a protection layer from peeling is formed in corner portions of a semiconductor device. The peeling prevention layer can increase its peeling prevention effect more when formed in a vacant space of the semiconductor device other than the corner portions, for example, between ball-shaped conductive terminals. In a cross section of the semiconductor device, the peeling prevention layer is formed on the insulation film on the back surface of the semiconductor substrate, and the protection layer formed of a solder resist or the like is formed covering the insulation film and the peeling prevention layer. The peeling prevention layer has a lamination structure of a barrier seed layer and a copper layer formed thereon when formed by an electrolytic plating method.

Abstract: The invention relates to a solution for the deposition of barrier layers on metal surfaces, which comprises compounds of the elements nickel and molybdenum, at least one first reducing agent selected from among secondary and tertiary cyclic aminoboranes and at least one complexing agent, where the solution has a pH of from 8.5 to 12.

Abstract: A method is described in which a contact hole (18) to an interconnect (14) in an insulating layer (16) is fabricated. A barrier layer (20) is subsequently applied. Afterward, a photoresist layer (30) is applied, irradiated and developed. With the aid of a galvanic method, a copper contact (32) is then produced in the contact hole (18). Either the barrier layer (20) or an additional boundary electrode layer (22) serves as a boundary electrode in the galvanic process. Critical metal contaminations are minimized in production.

Abstract: A semiconductor device may include a gate insulating layer on a semiconductor substrate, a polysilicon layer doped with impurities on the gate insulating layer, an interface reaction preventing layer on the polysilicon layer, a barrier layer on the interface reaction preventing layer, and a conductive metal layer on the barrier layer. The interface reaction preventing layer may reduce or prevent the occurrence of a chemical interfacial reaction with the barrier layer, and the barrier layer may reduce or prevent the diffusion of impurities doped to the polysilicon layer. The interface reaction preventing layer may include a metal-rich metal silicide having a metal mole fraction greater than a silicon mole fraction, so that the interface reaction preventing layer may reduce or prevent the dissociation of the barrier layer at higher temperatures. Thus, a barrier characteristic of a poly-metal gate electrode may be improved and surface agglomerations may be reduced or prevented.

Abstract: A semiconductor device includes a semiconductor substrate having a through hole. An active layer is formed on a first surface of the semiconductor substrate. An inner wall surface of the through hole, a bottom surface of the through hole closed by the active layer and a second surface of the semiconductor substrate are covered with an insulating layer. A first opening is formed in the insulating layer which is present on the bottom surface of the through hole. A second opening is formed in the insulating layer which is present on the second surface of the semiconductor substrate. A first wiring layer is formed from within the through hole onto the second surface of the semiconductor substrate. A second wiring layer is formed to connect to the second surface through the second opening.

Abstract: Aimed at improving adhesiveness between upper and lower interconnects in semiconductor devices, a semiconductor device of the present invention includes a second dielectric multi-layered film formed on a substrate, and containing a lower interconnect; a first dielectric multi-layered film formed on the second dielectric multi-layered film, and having a recess; an MOx film formed on the inner wall of the recess, and containing a metal M and oxygen as major components; an M film formed on the MOx film, and containing the M as a major component; and an electric conductor formed on the M film so as to fill the recess, and containing Cu as a major component, wherein the surficial portion of the interconnect fallen straight under the bottom of the recess has an oxygen concentration of 1% or smaller.

Abstract: The structures and methods described above provide mechanisms to improve interconnect reliability and resistivity. The interconnect reliability and resistivity are improved by using a composite barrier layer, which provides good step coverage, good copper diffusion barrier, and good adhesion with adjacent layers. The composite barrier layer includes an ALD barrier layer to provide good step coverage. The composite barrier layer also includes a barrier-adhesion-enhancing film, which contains at least an element or compound that contains Mn, Cr, V, Ti, or Nb to improve adhesion. The composite barrier layer may also include a Ta or Ti layer between the ALD barrier layer and the barrier-adhesion-enhancing layer.

Abstract: A memory cell includes a memory cell layer with a first dielectric layer over a bottom electrode layer, a second dielectric layer over the first dielectric layer, and a top electrode over the second dielectric layer. The dielectric layers define a via having a first part bounded by the first electrode layer and the bottom electrode and a second part bounded by the second dielectric layer and the top electrode. A memory element is within the via and is in electrical contact with the top and bottom electrodes. The first and second parts of the via may comprise a constricted, energy-concentrating region and an enlarged region respectively. The constricted region may have a width smaller than the minimum feature size of the process used to form the enlarged region of the via. A method for manufacturing a memory cell is also disclosed.

Abstract: A method of fabricating a dual damascene structure is described. A dielectric layer and a metal hard mask layer are sequentially formed on a substrate having thereon a conductive layer and a liner layer. The metal hard mask layer and the dielectric layer are patterned to form a via hole exposing a portion of the liner layer. A gap-filling layer is filled in the via hole, having a height of ¼ to ½ of the depth of the via hole. A trench is formed in the metal hard mask layer and the dielectric layer. The gap-filling layer is removed to expose the portion of the liner layer, which is then removed. A metal layer is formed filling in the via hole and the trench, and then the metal hard mask layer is removed.

Abstract: A semiconductor device includes a first interconnection pattern embedded in a first insulation film, a second insulation film covering the first interconnection pattern over the first insulation film, an interconnection trench formed in an upper part of the second insulation film, a via-hole extending downward from the interconnection trench at a lower part of the second insulation film, the via-hole exposing the first interconnection pattern, a second interconnection pattern filling the interconnection trench, a via-plug extending downward in the via-hole from the second interconnection pattern and making a contact with the first interconnection pattern, and a barrier metal film formed between the second interconnection pattern and the interconnection trench, the barrier metal film covering a surface of the via-plug continuously, wherein the via-plug has a tip end part invading into the first interconnection pattern across a surface of said first interconnection pattern, the interconnection trench has a flat

Abstract: To provide an insulating film material that can be advantageously used for forming an insulating film having a low dielectric constant and excellent resistance to damage, such as etching resistance and resistance to liquid reagents, a multilayer interconnection structure in which a parasitic capacitance between the interconnections can be reduced, efficient methods for manufacturing the multilayer interconnection structure, and an efficient method for manufacturing a semiconductor device with a high speed and reliability. The insulating film material contains at least a silicon compound having a steric structure represented by Structural Formula (1) below. where, R1, R2, R3, and R4 may be the same or different and at least one of them represents a functional group containing any of a hydrocarbon and an unsaturated hydrocarbon.

Abstract: Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

Abstract: A semiconductor device in which the resistance of a copper wiring to electromigration is increased. The copper wiring is formed so that copper grains will be comparatively large in a central portion of the copper wiring and so that copper grains will be comparatively small in an upper portion and a lower portion of the metal wiring. The copper wiring having this structure is formed by a damascene method. This structure can be formed by controlling electric current density at electroplating time. With the copper wiring having this structure, it is easier for an electric current to run through the central portion than to run through the upper portion. As a result, the diffusion of copper atoms in the upper portion is suppressed and therefore the diffusion of copper atoms from an interface between the copper wiring and a cap film is suppressed.

Abstract: A method for forming deep lithographic interconnects between a first metal and a second metal is provided. The method comprises depositing a first insulator layer on a semiconductor substrate; etching the first insulator layer at a selected location to provide at least a first via to the semiconductor substrate; depositing the first metal on the semiconductor substrate to form at least a first metal contact plug in the first via in contact with the semiconductor substrate; treating the semiconductor substrate with an in-situ plasma of a nitrogen containing gas wherein the plasma forms a nitride layer of the first metal at least capping a top surface of the first metal plug in the first via; and forming a second metal contact to the metal nitride layer capping at least the top surface of the first metal plug.

Abstract: One exemplary embodiment includes a semiconductor chip that has a rectangle principal surface including a first and a second side that oppose each other. A first and a second semiconductor element, and a first and a second wire are formed on the principal surface. The first wire is formed from the first side to reach the second side, and coupled to the first semiconductor element. The second wire is formed to contact at least the first wire, and coupled to the second semiconductor element. Further, an edge part of the first wire on the second side and an edge part of the second wire on the first side are placed to substantially position on a common straight line which is vertical to the first and the second sides.

Abstract: The present invention relates to an interconnect capping layer and a method of fabricating a capping layer for an interconnect. In particular, but not exclusively, the invention relates to a capping layer for a copper interconnect used to interconnect elements in an integrated circuit. Embodiments of the invention provide a method of fabricating a capping layer for an interconnect in an integrated circuit, comprising the steps of: forming an interconnect comprising upper and lower lateral surfaces; forming a lateral diffusion stop layer between said lateral surfaces; and forming a capping layer.

Abstract: Methods of forming an integrated circuit device may include forming an insulating layer on an integrated circuit substrate, forming a first conductive layer on the insulating layer, and forming a second conductive layer on the first conductive layer so that the first conductive layer is between the second conductive layer and the insulating layer. Moreover, the first conductive layer may be a layer of a first material, the second conductive layer may be a layer of a second material, and the first and second materials may be different. A hole may be formed in the second conductive layer so that portions of the first conductive layer are exposed through the hole. After forming the hole in the second conductive layer, the first and second conductive layers may be patterned so that portions of the first and second conductive layers surrounding portions of the first conductive layer exposed through the hole are removed while maintaining portions of the first conductive layer previously exposed through the hole.

Abstract: An on-chip vertical coplanar waveguide with tunable characteristic impedance, a design structure, and a method of making the same. An on-chip transmission line includes a signal line, an upper ground line spaced apart from and above the signal line, and a lower ground line spaced apart from and below the signal line. The signal line, the upper ground line and the lower ground line are substantially vertically aligned in a dielectric material.

Abstract: A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.

Abstract: In a method of forming a contact hole and a method of manufacturing a semiconductor device having the same, a first insulation interlayer is formed on a substrate. A dummy pattern is formed on the first insulation interlayer. A second insulation interlayer is formed to cover the dummy pattern. A photoresist pattern is formed on the second insulation interlayer. The photoresist pattern has an exposed portion. The dummy pattern under the photoresist pattern is arranged to cross over the exposed portion of the photoresist pattern. The first and second insulation interlayers are etched using the photoresist pattern and the dummy pattern as an etching mask, to form a plurality of contact holes on both sides of the dummy pattern. Accordingly, the contact holes may be formed to have a smaller width.

Abstract: A method for fabricating a semiconductor memory device includes forming an insulation layer including a contact plug over a substrate structure, forming a metal line structure over the insulation layer, the metal line structure including a patterned diffusion barrier layer and a metal line and contacting the contact plug, and oxidizing a surface of the metal line to form a passivation layer over the metal line.

Abstract: A method for manufacturing a semiconductor device, including: forming a first conductive layer on a first insulating film; forming a second insulating film so as to cover the first conductive layer; forming a resist mask on the second insulating film; forming a hole reaching the first conductive layer in the second insulating film by a first etching using the resist mask; removing the resist mask; removing the first conductive layer exposed at the bottom of the hole by a second etching, so that the hole reaches the first insulating film and the first conductive layer exposes at a side surface within the hole; forming a conductive plug in contact with the first conductive layer exposed at the side surface within the hole by burying a conductive material in the hole; and forming a second conductive layer to be connected to the conductive plug on the second insulating film.

Abstract: A flat panel display device that includes a clad unit that may prevent terminals of a pad unit from becoming corroded or damaged by an etching solution during etching. The flat panel display device may include a display unit, a pad unit which may include a plurality of terminals electrically connecting the display unit to external devices, and a clad unit which may cover at least side end portions of the terminals, in which the clad unit may be composed of an insulating material.

Abstract: In a film substrate (FB) including a film base material (1) and conductor wiring (23) that is formed on the film base material (1), the conductor wiring (23) is arranged such that the conductor wiring thickness of an external connection portion on the film substrate to which another panel or substrate is connected is thicker than the conductor wiring thickness of conductor wiring portions (bent portions) (25) at other positions.

Abstract: In a semiconductor device and a method of fabricating the same, the semiconductor device includes a contact pad in a first interlayer insulating layer on a semiconductor substrate, a contact hole in a second interlayer insulating layer on the first interlayer insulating layer, selectively exposing the contact pad, a contact spacer on internal walls of the contact hole, a first contact plug connected to the contact pad exposed by the contact hole having the contact spacer on the internal walls thereof, the first contact plug partially filling the contact hole, a metal silicide layer on a surface of the first contact plug, and a second contact plug on the metal silicide layer and partially filling the remaining portion of the contact hole.

Abstract: An ESD device with a protection structure utilizing radiated heat dissipation to prevent or reduce thermal failures. The device includes a voltage switchable polymer 10 between electrodes 11 and 12, which is configured to provide a heat radiating surface 40 for radiating heat when an ESD condition occurs. A radiation transmission material 19 is disposed between the heat radiating surface and the environment for radiating heat 20 when an ESD event occurs. One embodiment adds a spacer 50 for accurately spacing electrodes. A method for fabricating the device is further illustrated.

Abstract: A method of fabricating metal film stacks is described that reduces or eliminates adverse effects of photolithographic misalignments. A bottom critical dimension is increased by removal of a bottom titanium nitride barrier.

Abstract: A method of reworking a semiconductor substrate and a method of forming a pattern of semiconductor device using the same without damage to an organic anti-reflective coating (ARC) is provided. The method of reworking a semiconductor substrate includes forming a photoresist pattern on a substrate having the organic ARC formed thereon. An entire surface of the substrate having the photoresist pattern formed thereon may be exposed when a defect is present in the photoresist pattern. The entire-surface-exposed photoresist pattern may be removed by performing a developing process without damage to the organic ARC.

Abstract: A method of reforming a metal pattern for improving the productivity and reliability of a manufacturing process, an array substrate and a method of manufacturing the array substrate are disclosed. In the method, a first wiring pattern is formed on an insulation substrate. The first wiring pattern is removed. A second wiring pattern is formed on an embossed pattern by using the embossed pattern as an alignment mask. The embossed pattern is defined by a recess formed on a surface of the insulation substrate. Accordingly, the insulation substrate having the recess formed thereon may not be discarded, and may be reused in forming the first wiring pattern. In addition, the embossed pattern defined by the recess is used as an alignment mask, so that the alignment reliability of a metal pattern may be improved.

Abstract: The invention relates to electro-optic displays and methods for driving such displays. The invention provides (i) electrochromic displays with solid charge transport layers; (ii) apparatus and methods for improving the contrast and reducing the cost of electrochromic displays; (iii) apparatus and methods for sealing electrochromic displays from the outside environment and preventing ingress of contaminants into such a display; and (iv) methods for adjusting the driving of electro-optic displays to allow for environmental and operating parameters.

Abstract: A manufacturing method of a dual damascene structure is provided. First, a first dielectric layer, a second dielectric layer, and a mask layer are formed. A first trench structure is formed in the mask layer. A via structure is formed in the mask layer, the second dielectric layer, and the first dielectric layer. A portion of the second dielectric layer is then removed, so as to transform the first trench structure into a second trench structure. Here, a bottom of the second trench structure exposes the first dielectric layer.

Abstract: A fabrication method is used in conjunction with a semiconductor device having a metal oxide active layer less than 100 nm thick and the upper major surface and the lower major surface have material in abutting engagement to form underlying interfaces and overlying interfaces. The method of fabrication includes controlling interfacial interactions in the underlying interfaces and the overlying interfaces to adjust the carrier density in the adjacent metal oxide by selecting a metal oxide for the metal oxide active layer and by selecting a specific material for the material in abutting engagement. The method also includes one or both steps of controlling interactions in underlying interfaces by surface treatment of an underlying material forming a component of the underlying interface and controlling interactions in overlying interfaces by surface treatment of the metal oxide film performed prior to deposition of material on the metal oxide layer.

Abstract: A method for manufacturing a semiconductor device including, forming a first insulating film above a silicon substrate, forming an impurity layer in the first insulating film by ion-implanting impurities into a predetermined depth of the first insulating film, and modifying the impurity layer to a barrier insulating film by annealing the first insulating film after the impurity layer is formed, is provided.

Abstract: A semiconductor device having a device substrate is provided. The semiconductor device comprises an electrically-conductive pad formed overlying the device substrate, an electrically-conductive platform formed overlying the electrically-conductive pad and enclosing a cavity, the electrically-conductive platform having a perimeter portion extending away from the electrically-conductive pad and a capping portion atop the perimeter portion, and a cushioning material disposed in the cavity.

Abstract: A method for integrating ruthenium (Ru) metal cap layers and modified Ru metal cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in bulk Cu metal. In one embodiment, the method includes providing a planarized patterned substrate containing a Cu metal surface and a dielectric layer surface, depositing first Ru metal on the Cu metal surface, and depositing additional Ru metal on the dielectric layer surface, where the amount of the additional Ru metal is less than the amount of the first Ru metal. The method further includes at least substantially removing the additional Ru metal from the dielectric layer surface to improve the selective formation of a Ru metal cap layer on the Cu metal surface. Other embodiments further include incorporating one or more types of modifier elements into the dielectric layer surface, the Cu metal surface, the Ru metal cap layer, or a combination thereof.

Abstract: A method for forming interconnect wiring, includes: (i) covering a surface of a connection hole penetrating through interconnect dielectric layers formed on a substrate for interconnect wiring, with an underlying alloy layer selected from the group consisting of an alloy film containing ruthenium (Ru) and at least one other metal atom (M), a nitride film thereof, a carbide film thereof, and an nitride-carbide film thereof, and (ii) filling copper or a copper compound in the connection hole covered with the underlying layer.

Abstract: An integrated component includes a semiconductor substrate; at least one interconnect applied on the semiconductor substrate; an insulating layer applied on the at least one interconnect; and at least one opening through the insulating layer which interrupts the at least one interconnect into a first section and a second section.

Abstract: A method and apparatus are described for fabricating an ultra low-k interconnect structure by depositing and curing a first via layer (43) of ultra low dielectric constant (ULK) material, depositing a second uncured trench layer (51) of the same ULK material, selectively etching a via opening (62) and trench opening (72) with a dual damascene etch process which uses a trench etch end point signal from the chemical differences between uncured trench layer (51) and the underlying cured via layer (43), and then curing the second trench layer (83) before forming an interconnect structure (91) by filling the trench opening (72) and via opening (62) with an interconnection material so that there is no additional interface or higher dielectric constant material left behind.

Abstract: The present method of fabricating a resistive memory device includes the steps of providing a first electrode, oxidizing a portion of the first electrode with an oxidizing agent, providing a metal body on the oxidized portion of the first electrode, oxidizing the entire metal body with an oxidizing agent, and providing a second electrode on the oxidized metal body.

Abstract: A method of fabricating a semiconductor device includes etching a silicon oxide film, a silicon nitride film, a polycrystalline silicone film, and a gate insulating film in a predetermined pattern including a first opening width corresponding to a first trench and a second opening width corresponding to a second trench, the second opening width being larger than the first opening width, and etching the semiconductor substrate to simultaneously form the first and second trenches so that a first depth of the first trench is equal to a second depth of the second trench, and a first angle between a first side surface and a first bottom surface of the first trench is smaller than a second angle between a second side surface and a second bottom surface of the second trench, and the first trench includes a curved portion at an upper portion of the first side surface.

Abstract: Methods are provided for forming a semiconductor device comprising a semiconductor substrate. In accordance with an exemplary embodiment, a method comprises the steps of forming a high-k dielectric layer overlying the semiconductor substrate, forming a metal-comprising gate layer overlying the high-k dielectric layer, forming a doped silicon-comprising capping layer overlying the metal-comprising gate layer, and depositing a silicon-comprising gate layer overlying the doped silicon-comprising capping layer.

Abstract: A three-dimensional (3D) semiconductor structure with high density and method of fabricating the same are disclosed. The 3D semiconductor structure comprises at least a first memory cell and a second memory cell stacked on the first memory cell. The first memory cell comprises a first conductive line and a second conductive line. The second memory cell comprises another first conductive line opposite to the first conductive line of the first memory cell, and the second conductive line formed between said two first conductive lines of the first and second memory cells. The first and second memory cells share the second conductive line when the 3D semiconductor structure is programming and erasing, and each of the first and second memory cells has a diode.

Abstract: A foldable microcircuit is initially a planar semiconductor wafer on which circuitry has been formed. The wafer is segmented into a plurality of tiles, and a plurality of hinge mechanisms are coupled between adjacent pairs of tiles such that the segmented wafer can be folded into a desired non-planar configuration having a high fill-factor and small gaps between tiles. The hinge mechanisms can comprise an organic material deposited on the wafer such that it provides mechanical coupling between adjacent tiles, with metal interconnections between tiles formed directly over the organic hinges, or routed between adjacent tiles via compliant bridges. Alternatively, the interconnection traces between tiles can serve as part or all of a hinge mechanism. The foldable microcircuit can be, for example, a CMOS circuit, with the segmented tiles folded to form, for example, a semi-spherical structure arranged to provide a wide FOV photodetector array.

Abstract: The present invention provides a method of fabricating a semiconductor apparatus including a vertical transistor and a semiconductor apparatus fabricated thereby which protect a pillar-shaped channel region to stabilize an operating characteristic of the semiconductor apparatus. The method of fabricating the semiconductor apparatus according to the present invention comprises: forming a pillar-shaped pattern on a semiconductor substrate; depositing a conductive layer surrounding the pattern; changing a feature of some portion of the conductive layer through an ion implanting process to form an oxide film; and removing the oxide film using an etching selectivity difference.

Abstract: A method of fabricating a self-aligned contact is provided. A first dielectric layer is formed on a substrate having a contact region thereon. Next, a lower opening corresponding to the contact region is formed in the first dielectric layer. Thereafter, a second dielectric layer is formed on the first dielectric layer, and then an upper opening self-aligned to and communicated with the lower opening is formed in the second dielectric layer, wherein the upper opening and the lower opening constitute a self-aligned contact opening. Afterwards, the self-aligned contact opening is filled with a conductive layer.