Abstract: Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.

Abstract: A semiconductor integrated circuit device with enhanced reliability is provided. The semiconductor integrated circuit device includes a semiconductor substrate; a gate insulation film that is provided on the semiconductor substrate; a gate electrode that is provided on the gate insulation film; and a sidewall spacer that is provided on side walls of the gate insulation film and the gate electrode and includes, wherein the sidewall spacer has a first sidewall spacer in contact with the gate electrode and a second sidewall spacer formed on the side walls of the first sidewall spacer, and a ratio of an Si—OH area to an Si—O area in at least one of the first and second sidewall spacers is 0.05 or less, as measured by Fourier Transform InfraRed (FTIR).

Abstract: A method of making an integrated circuit includes providing a low-k dielectric layer on a substrate, the low-k dielectric layer including or adjacent to a plurality of conductive features; patterning the low-k dielectric layer to form trenches; patterning the low-k dielectric layer to form conductive vias and dummy vias, wherein each of the conductive vias is aligned with at least one of the plurality of the conductive features and at least one of the trenches, and each of the dummy vias is a distance above the plurality of conductive features; filling the trenches, conductive vias, and dummy vias using one or more conductive materials; and planarizing the conductive material(s).

Abstract: A contact arrangement is manufactured by providing a substrate that includes first regions that are arranged along a row direction and a second region. An interlayer is provided that covers the first regions and the second region. A buried mask including a first trim opening above the first regions is provided. A top mask including first template openings is provided, where each first template opening is arranged above one of the first regions. A second template opening is provided above the second region. The fill material and the interlayer are etched to form contact trenches above the first regions and the second region. Substrate area efficient chains of evenly spaced contacts are provided.

Abstract: A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises providing a substrate with a logic device region and a memory device region. A logic device with a first silicide region and a first silicide block region and a memory device with a second silicide region and a second silicide block region are formed in the logic device region and the memory device region, respectively. A first insulating layer is formed covering the first and second silicide block regions. A silicide process is performed to form a silicide layer on the first and second silicide regions. An underlying second insulating layer and an insulating barrier layer are formed covering the first insulating layer and the silicide layer.

Abstract: The invention comprises a copper interconnect structure that includes a noble metal cap with dielectric immediately adjacent the copper/noble metal cap interface recessed from the noble metal cap.

Abstract: A semiconductor device having one or more through-silicon vias (TSVs) is provided. The TSVs are formed such that sidewalls of the TSVs have a scalloped surface. In an embodiment, the sidewalls of the TSVs are sloped wherein a top and bottom of the TSVs have different dimensions. The TSVs may have a V-shape wherein the TSVs have a wider dimension on a circuit side of the substrate, or an inverted V-shape wherein the TSVs have a wider dimension on a backside of the substrate. The scalloped surfaces of the sidewalls and/or sloped sidewalls allow the TSVs to be more easily filled with a conductive material such as copper.

Abstract: A method for fabricating a semiconductor device includes forming an interlayer insulating film over a semiconductor substrate. The interlayer insulating film is selectively etched to form a hole defining a storage node region. A lower electrode is formed in the hole. A support layer is formed over the lower electrode. The support layer fills an upper part of the hole and exposes the interlayer insulating film. A dip-out process is performed to remove the interlayer insulating film. The supporting layer is removed to expose the lower electrode. A dielectric film is formed over the semiconductor substrate including the lower electrode. A plate electrode is formed over the semiconductor substrate to fill the dielectric film and the lower electrode.

Abstract: The present invention describes a method including: providing a substrate; stacking interlevel dielectric layers over said substrate, and separating said interlevel dielectric layers with a dielectric separator layer.

Abstract: A circuit structure has a first dielectric layer, a first circuit pattern embedded in the first dielectric layer and having a first via pad, a first conductive via passing through the first dielectric layer and connecting to the first via pad, and an independent via pad disposed on a surface of the first dielectric layer away from the first via pad and connecting to one end of the first conductive via. The circuit structure further has a second dielectric layer disposed over the surface of the first dielectric layer where the independent via pad is disposed, a second conductive via passing through the second dielectric layer and connecting to the independent via pad, and a second circuit pattern embedded in the second dielectric layer, located at a surface thereof away from the independent via pad, and having a second via pad connected to the second conductive via.

Abstract: Embodiments of an apparatus and methods for providing improved flash memory cell characteristics are generally described herein. Other embodiments may be described and claimed.

Abstract: Different types of transistors, such as memory cells, higher voltage, and higher performance transistors, may be formed on the same substrate. A transistor may be formed with a first polysilicon layer covered by a dielectric. A second polysilicon layer over the dielectric may be etched to form a sidewall spacer on the gate of the transistor. The sidewall spacer may be used to form sources and drains and to define sub-lithographic lightly doped drains. After removing the spacer, the underlying dielectric may protect the lightly doped drains.

Abstract: A semiconductor memory has a composite floating structure in which quantum dots composed of Si and coated with a Si oxide thin film are deposited on an insulating film formed on a semiconductor substrate, quantum dots coated with a high-dielectric insulating film are deposited on the quantum dots, and quantum dots composed of Si and coated with a high-dielectric insulating film are further deposited. Each of the quantum dots includes a core layer and a clad layer which covers the core layer. The electron occupied level in the core layer is lower than that in the clad layer.

Abstract: The present invention provides a method of fabricating a biosensor. The method includes providing a substrate which has a surface coating. The surface coating is deformable and the substrate includes a layered structure which has at least two electrically conductive layers separated by at least one electrically insulating layer. The method also includes imprinting a structure into the surface coating. Further, the method includes etching at least a region of the imprinted structure and the substrate to remove at least a portion of the structure and the substrate. The structure is shaped so that the etching forms at least a portion of the biosensor in the substrate and exposes at least a portion of each electrically conductive layer to form electrodes of the biosensor.

Abstract: A metal line of a semiconductor device includes an insulation layer formed on a semiconductor substrate and having a metal line forming region. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer. The diffusion barrier has a multi-layered structure of a V layer, a VxNy layer and a VxNyOz layer. A metal layer is formed on the diffusion barrier to fill the metal line forming region of the insulation layer.

Abstract: A method for fabricating an insulation layer includes forming an insulation layer over a nitride layer using a silicon source and a phosphorus source, wherein the insulation layer includes a first insulation layer contacting the nitride layer and a second insulation layer formed on the first insulation layer, wherein the first insulation layer is formed using a higher flow rate of the silicon source and a lower flow rate of the phosphorus source than used with the second insulation layer.

Abstract: A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.

Abstract: Exuding of a interconnecting material to a substrate, which occurs because of a thinned state of and a beak in a barrier metal layer is prevented, irrespective of a laminated state of the barrier metal layer. In the present invention, a protective layer is formed on a side wall by using an insulating film or the like after the deposition of the barrier metal layer, whereby the interconnecting material can be prevented from exuding to the substrate due to influence of heat treatment such as alloying, irrespective of the laminated state of the side wall of the contact hole and the barrier metal layer. Further, the formation of the protective layer allows the side wall to be smoother to thereby improve coverage of the interconnecting material at the same time.

Abstract: Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.

Abstract: Aimed at improving adhesiveness between upper and lower interconnects in semiconductor devices, a semiconductor device of the present invention includes a second dielectric multi-layered film formed on a substrate, and containing a lower interconnect; a first dielectric multi-layered film formed on the second dielectric multi-layered film, and having a recess; an MOx film formed on the inner wall of the recess, and containing a metal M and oxygen as major components; an M film formed on the MOx film, and containing the M as a major component; and an electric conductor formed on the M film so as to fill the recess, and containing Cu as a major component, wherein the surficial portion of the interconnect fallen straight under the bottom of the recess has an oxygen concentration of 1% or smaller.

Abstract: A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is deposited over the nucleation layer, the tungsten layer having a thickness less than or equal to a critical film thickness sufficient to provide for film integrity and adhesion stability. A stress relief layer of titanium nitride is formed over the tungsten layer and a subsequent tungsten layer is deposited over the stress relief layer. The subsequent tungsten layer has a thickness less than or equal to the critical film thickness. The method further includes planarizing to expose the interlevel dielectric layer and a top of the TSV and backgrinding a bottom surface of the substrate sufficient to expose a bottom portion of the TSV.

Abstract: A method for controlling etching during photolithography in the fabrication of an integrated circuit in connection with first and second features that are formed on the integrated circuit having a gap there between comprising depositing a layer of photoresist on the integrated circuit, selectively exposing portions of the photoresist through at least one photolithography mask having a pattern including means for alleviating line end shortening of the first and second lines adjacent the gap, and developing the photoresist after the selective exposing step.

Abstract: Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm.

Abstract: A method of fabricating a gate of a semiconductor device is provided. In an embodiment, the method includes forming a gate dielectric layer on a semiconductor substrate. An interface layer is formed on the gate dielectric layer. In an embodiment, the gate dielectric layer includes HfO2 and the interface layer includes Hf—N. A work function metal layer may be formed on the interface layer. A device is also provided.

Abstract: Memory elements and methods for making memory elements. One method of making a memory element includes forming a first electrode, forming an electrically conductive current densifying element and a memory cell on the first electrode, the memory cell and the current densifying element adjacent to each other. A second electrode is formed over the current densifying element and the memory cell. The memory elements may be resistance random access memory elements.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.

Abstract: Methods of processing a substrate are provided herein. In some embodiments, a method of processing a substrate may include providing a substrate to a process chamber comprising a dielectric layer having a feature formed therein. A barrier layer may be formed within the feature. A coating of a first conductive material may be formed atop the barrier layer. A seed layer of the first conductive material may be formed atop the coating. The feature may be filled with a second conductive material. In some embodiments, the seed layer may be formed while maintaining the substrate at a temperature of greater than about 40 degrees Celsius.

Abstract: A method of forming a gate of a semiconductor device includes providing a semiconductor substrate over which a first conductive layer, a dielectric layer and a second conductive layer are formed. The second conductive layer is patterned to expose a part of the dielectric layer. A first protection layer is formed on sidewalls of the second conductive layer. A first etch process is performed to remove the exposed dielectric layer and to expose a part of the first conductive layer. A second protection layer is formed on sidewalls of the second conductive layer. A second etch process is performed to remove the exposed first conductive layer.

Abstract: A method for forming interconnect structure includes providing a substrate; forming a low-k dielectric layer over the substrate; forming an opening in the low-k dielectric layer; after the step of forming the opening, performing a silicon/germanium soaking process to exposed surfaces of the low-k dielectric layer; and after the silicon/germanium soaking process, filling the opening.

Abstract: Semiconductor interconnect structures including a surface-repair material, e.g., a noble metal or noble metal alloy, that fills hollow-metal related defects located within a conductive material are provided. The filling of the hollow-metal related defects with the surface repair material improves the electromigration (EM) reliability of the structure as well as decreasing in-line defect related yield loss.

Abstract: A method and apparatus for depositing organosilicate dielectric layers having good adhesion properties and low dielectric constant. Embodiments are described in which layers are deposited at low temperature and at high temperature. The low temperature layers are generally post-treated, whereas the high temperature layers need no post treating. Adhesion of the layers is promoted by use of an initiation layer.

Abstract: Methods of selectively forming metal silicides on a memory device are provided. The methods can include forming a mask layer over the memory device; forming a patterned resist over the mask layer; removing upper portions of the patterned resist; forming a patterned mask layer by removing portions of the mask layer that are not covered by the patterned resist; and forming metal silicides on the memory device by a chemical reaction of a metal layer formed on the memory device with portions of the memory device that are not covered by the patterned mask layer. By preventing silicidation of underlying silicon containing layers/components of the memory device that are covered by the patterned mask layer, the methods can selectively form the metal silicides on the desired portions of the memory device.

Abstract: A method is provided for integrating ruthenium (Ru) metal deposition into manufacturing of semiconductor devices to improve electromigration and stress migration in copper (Cu) metal. Embodiments of the invention include treating patterned substrates containing metal layers and low-k dielectric materials with NHx (x?3) radicals and H radicals to improve selective formation of ruthenium (Ru) metal cap layers on the metal layers relative to the low-k dielectric materials.

Abstract: A system and method for manufacturing a semiconductor device including a low dielectric constant porous material layer. Ions are implanted into the low dielectric constant porous material layer which thereby provides the porous material layer with sufficient mechanical strength for withstanding semiconductor manufacturing processes. The ions implanted in the porous material layer further facilitate disposition of a conductive layer on the porous material layer.

Abstract: Described herein are methods for fabricating dual-damascene interconnect structures. In one embodiment, the interconnect structures are fabricated with a dual-damascene method having trenches then vias formed. The method includes novel liner depositions after the trench and via etches. The method includes etching trenches in a dielectric layer. Next, the method includes depositing a first liner layer on the dielectric layer. Next, the method includes etching vias in the dielectric layer and an etch stop layer. Next, the method includes depositing a second liner layer on the first liner layer. The second liner layer is deposited on the exposed surfaces of the first liner layer, dielectric layer, etch stop layer, and the first metal layer. Then, a second metal layer is deposited on the second liner layer.

Abstract: A method of forming an interconnect structure is provided. The method includes depositing a cobalt metal layer in an interconnect opening formed within a dielectric material containing a dielectric reactant element. The method further includes, in any order, thermally reacting at least a portion of the cobalt metal layer with at least a portion of the dielectric material to form a diffusion barrier containing a compound of the reactive metal from the cobalt metal layer and the dielectric reactant element from the dielectric material, and forming a cobalt nitride adhesion layer in the interconnect opening. The method further includes filling the interconnect opening with Cu metal, where the diffusion barrier and the cobalt nitride adhesion layer surround the Cu metal in the interconnect opening.

Abstract: A semiconductor device includes a substrate; a first via provided in the substrate extending from a first side of the substrate to a first depth into the substrate, the first depth being less than a thickness of the substrate and the first via having a first width in one direction; a first conductive material provided in the first via; a second via provided in the substrate extending from a second side of the substrate to a second depth into the substrate, the second via having a second width in one direction, the second width being greater than the first width; and a second conductive material provided in the second via so as to form an electrical connection with the first conductive material provided in the first via.

Abstract: Structures and methods of forming through substrate vias are disclosed. In one embodiment, the method includes forming a through substrate opening from a top surface of a substrate, the top surface including active devices, and filling the first through substrate opening with an ancillary material. A conductive capping layer is formed over the ancillary material to cap the first through substrate opening. The substrate is thinned from a back surface to expose a portion of the ancillary material, the back surface being opposite to the top surface. The ancillary material is removed from the first through substrate opening, and a conductor is formed by filling a conductive material into the through substrate opening.

Abstract: A copper interconnection structure includes an insulating layer, an interconnection body including copper and a barrier layer surrounding the interconnection body. The barrier layer includes a first barrier layer formed between a first portion of the interconnection body and the insulating layer. The first portion of the interconnection body is part of the interconnection body that faces the insulating layer. The barrier layer also includes a second barrier layer formed on a second portion of the interconnection body. The second portion of the interconnection body is part of the interconnection body not facing the insulating layer. Each of the first and the second barrier layers is formed of an oxide layer including manganese, and each of the first and the second barrier layers has a position where the atomic concentration of manganese is maximized in their thickness direction of the first and the second barrier layers.

Abstract: A microelectromechanical system (MEMS) structure and a fabricating method thereof are described. The MEMS structure includes a fixed part and a movable part. The fixed part is disposed on and connects with a substrate. The movable part including at least two first metal layers, a first protection ring and a first dielectric layer is suspended on the substrate. The first protection ring connects two adjacent first metal layers, so as to define a first enclosed space between the two adjacent first metal layers. The first dielectric layer is disposed in the enclosed space and connects the two adjacent first metal layers.

Abstract: A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is processed to produce a top surface of the dielectric layer that is not coplanar with a top surface of the conductive line to form a stepped topography.

Abstract: An integrated circuit including an insulating layer having first and second opposite surfaces. The circuit includes, in a first area, first conductive portions of a first conductive material, located in the insulating layer, flush with the first surface and continued by first vias of the first conductive material, of smaller cross-section and connecting the first conductive portions to the second surface. The circuit further includes, in a second area, second conductive portions of a second material different from the first conductive material and arranged on the first surface and second vias of the first conductive material, in contact with the second conductive portions and extending from the first surface to the second surface.

Abstract: A method for fabricating a microstructure is to form at least one insulation layer including a micro-electro-mechanical structure therein over an upper surface of a silicon substrate. The micro-electro-mechanical structure includes at least one microstructure and a metal sacrificial structure that are independent with each other. In the metal sacrificial structure are formed a plurality of metal layers and a plurality of metal via layers connected to the respective metal layers. A barrier layer is formed over an upper surface of the insulation layer, and an etching stop layer is subsequently formed over a lower surface of the silicon substrate. An etching operation is carried out from the lower surface of the silicon substrate to form a space corresponding to the micro-electro-mechanical structure, and then the metal sacrificial structure is etched, thus achieving a microstructure suspension.

Abstract: A non-volatile semiconductor memory device according to the present invention includes a substrate; a first word-line provided above the substrate surface, the first word-line having a plate shape in an area where a memory cell is formed; a second word-line provided above the first word-line surface, the second word-line having a plate shape; a plurality of metal wirings connecting the first and second word-lines with a driver circuit; and a plurality of contacts connecting the first and second word-lines with the metal wirings. The contact of the first word-line is formed in a first word-line contact area. The contact of the second word-line is formed in a second word-line contact area. The first word-line contact area is provided on a surface of the first word-line that is drawn to the second word-line contact area.

Abstract: Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof.

Abstract: A semiconductor device includes an insulation film 6 formed on a silicon substrate 1, a buried metal interconnect 8 formed in the insulation film 6, and a barrier metal film 7 formed between the insulation film 6 and the metal interconnect 8. The barrier metal film 7 is a metal compound film. The metal compound film is characterized by including at least one of elements forming the insulation film.

Abstract: Methods of forming through wafer vias (TWVs) and standard contacts in two separate processes to prevent copper first metal layer puddling and shorts are presented. In one embodiment, a method may include forming a TWV into a substrate and a first dielectric layer over the substrate; forming a second dielectric layer over the substrate and the TWV; forming, through the second dielectric layer, at least one contact to the TWV and at least one contact to other structures over the substrate; and forming a first metal wiring layer over the second dielectric layer, the first metal wiring layer contacting at least one of the contacts.

Abstract: A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving space. The lifting layer and conductive layer are formed in the receiving space, wherein the conductive layer extends for connection to a bump. The lifting layer is partially connected to the dielectric layer. As a result, the conductive layer can be stably deposited on the edge of the dielectric layer for enhancing the reliability of the packaging conductive structure.