Abstract: A semiconductor device includes a film substrate, an adhesive on a first surface of the film substrate, an electronic component on the adhesive, a wiring layer on a second surface of the film substrate opposite from the first surface, and a reinforcement member in an area around the electronic component on the adhesive. The wiring layer is connected to the electronic component through a via hole piercing through the film substrate and the adhesive. The reinforcement member has a thickness smaller than the thickness of the electronic component.

Abstract: A feeder exchanging device capable of exchanging feeder provided with fixed blade and movable blade for cutting top film that is peeled from bottom tape as components are supplied to a component mounter. The feeder exchanging device comprises robot hand that includes pair of arms on which claws capable of clamping feeder are formed, and sliders that move robot hand in the X-axis, Y-axis, and Z-axis directions, with an actuator (rod actuator) for driving movable blade provided on robot hand.

Abstract: A method of producing electronic components each including a substrate-type terminal and a device connected to the substrate-type terminal is performed such that the substrate-type terminal includes a substrate body including a rectangular or substantially rectangular first principal surface extending in first and second directions perpendicular or substantially perpendicular to each other. The device is disposed on the first principal surface. The method includes supporting a substrate that is to become an assembly in which the plurality of substrate-type terminals are arranged in a matrix using a first support member, cutting the substrate supported by the first support member into the plurality of substrate-type terminals, and mounting the device on the first principal surface of the substrate body of each of the plurality of substrate-type terminals obtained by cutting.

Abstract: According to one embodiment, a display device includes a first substrate includes an insulating substrate including a pierced portion, a pad electrode formed on the insulating substrate, and a signal line electrically connected to the pad electrode, a wiring board includes an interconnecting wiring and located under the insulating substrate, and a conductive material provided in the pierced portion and electrically connecting the pad electrode and the interconnecting wiring to each other.

Abstract: This invention provides an electro-optical module with reduced noise in driving voltage. The invention can include a power supply substrate that is arranged separately from the flexible substrate having a driver, so that the noise of the driving voltage supplied from the power supply substrate is reduced.

Abstract: A liquid crystal display device includes: a TFT substrate that includes gate lines; and a driver circuit section that includes a gate driver that is connected to the gate lines. A frame region includes a wiring substrate that sandwiches the gate lines. The wiring substrate includes: a first wiring substrate that has first wiring lines that are connected to the gate lines; a second wiring substrate that has second wiring lines that are connected to the first wiring lines; and a third wiring substrate that is attached to the second wiring substrate and has third wiring lines that are connected to the second wiring lines and a gate driver.

Abstract: An adhesive composition includes an acrylic polymer (A), a heat curable resin (B) having unsaturated hydrocarbon group, and a coupling agent (C) having reactive a double bond group.

Abstract: A method of manufacture of an integrated circuit package system includes: attaching a first die to a first die pad; connecting electrically a second die to the first die through a die interconnect positioned between the first die and the second die; connecting a first lead adjacent the first die pad to the first die; connecting a second lead to the second die, the second lead opposing the first lead and adjacent the second die; and providing a molding material around the first die, the second die, the die interconnect, the first lead and the second lead, with a portion of the first lead exposed.

Abstract: An adhesive composition for a semiconductor includes an acrylic polymer (A), an epoxy-based heat curable resin (B), a heat curing agent (C), a silane compound (D) having an organic functional group, molecular weight of 300 or more and an alkoxy equivalent of larger than 13 mmol/g, and a silane compound (E) having an organic functional group, molecular weight of 300 or less and an alkoxy equivalent of 13 mmol/g or less.

Abstract: A description is given of a method. In one embodiment the method includes providing a semiconductor chip with semiconductor material being exposed at a first surface of the semiconductor chip. The semiconductor chip is placed over a carrier with the first surface facing the carrier. An electrically conductive material is arranged between the semiconductor chip and the carrier. Heat is applied to attach the semiconductor chip to the carrier.

Abstract: A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias.

Abstract: A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias.

Abstract: A semiconductor device has a substrate with a plurality of conductive vias and conductive layer formed over the substrate. A semiconductor die is mounted over a carrier. The substrate is mounted to the semiconductor die opposite the carrier. An encapsulant is deposited between the substrate and carrier around the semiconductor die. A plurality of conductive TMVs is formed through the substrate and encapsulant. The conductive TMVs protrude from the encapsulant to aid with alignment of the interconnect structure. The conductive TMVs are electrically connected to the conductive layer and conductive vias. The carrier is removed and an interconnect structure is formed over a surface of the encapsulant and semiconductor die opposite the substrate. The interconnect structure is electrically connected to the conductive TMVs. A plurality of semiconductor devices can be stacked and electrically connected through the substrate, conductive TMVs, and interconnect structure.

Abstract: A method of manufacturing a semiconductor device is disclosed. One embodiment includes placing multiple semiconductor chips onto a carrier, each of the semiconductor chips having a first face and a second face opposite to the first face. An encapsulation material is applied over the multiple semiconductor chips and the carrier to form an encapsulating body having a first face facing the carrier and a second face opposite to the first face. A redistribution layer is applied over the multiple semiconductor chips and the first face of the encapsulating body. An array of external contact elements are applied to the second face of the encapsulating body.

Abstract: A method of forming an integrated circuit structure is provided. The method includes providing an interposer wafer; mounting the interposer wafer onto a handling wafer; thinning a backside of the interposer wafer; removing the handling wafer from the interposer wafer after the step of thinning; securing the interposer wafer on a fixture; and bonding a die on the interposer wafer.

Abstract: A method of manufacture of an integrated circuit package system includes providing a first frame having a first removable backing element connecting a first die attach pad and a first plurality of terminal leads. A first die is attached to the first die attach pad. A substrate is provided. A second die is attached to the substrate. The first die is attached to the second die with a plurality of die interconnects. The first removable backing element is removed after connecting the first die to the second die.

Abstract: A chip-mounted film package includes a base film, an effective film package defined on the base film by a cutting line, a driving chip mounted on the effective film package, a plurality of input pads arranged on an input area of the effective film package and connected to the driving chip, and a plurality of output pads arranged on an output area of the effective film package and connected to the driving chip, wherein the output area includes at least one extended portion that protrudes from a side of the effective film package in a horizontal direction of the base film.

Abstract: A semiconductor device is made by disposing a plurality of semiconductor die on a carrier and creating a gap between each of the semiconductor die. A first insulating material is deposited in the gap. A portion of the first insulating material is removed. A conductive layer is formed over the semiconductor die. A conductive lining is conformally formed on the remaining portion of the first insulating material to form conductive via within the gap. The conductive vias can be tapered or vertical. The conductive via is electrically connected to a contact pad on the semiconductor die. A second insulating material is deposited in the gap over the conductive lining. A portion of the conductive via may extend outside the first and second insulating materials. The semiconductor die are singulated through the gap. The semiconductor die can be stacked and interconnected through the conductive vias.

Abstract: A silicon-based wafer such as a TSV interposer wafer having a first and second surfaces wherein a glass carrier is mounted on the second surface by a UV tape is held by a vacuum holder applied on the first surface and the glass carrier is removed from the silicon-based wafer by irradiating the UV tape with a UV light through the glass carrier. The silicon-based wafer is then flipped and placed onto a vacuum plate and secured to the vacuum plate by applying vacuum to the vacuum plate. The vacuum holder is then released from the silicon-based wafer leaving the silicon-based wafer secured to the vacuum plate for subsequent processing steps.

Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.

Abstract: The present invention provides a process for producing a wiring circuit board which can be inhibited from developing whiskers and can be reduced in the unevenness of connectivity with electronic parts while retaining the connectivity. According to the present invention, a wiring pattern 12 comprising a thin metal film 31 and a conductor layer 33 is formed on a base insulating layer BIL. A tin-plated layer 34 is formed by electroless plating so as to coat the wiring pattern 12 therewith. The wiring pattern 12 and the tin-plated layer 34 are then subjected to a heat treatment. The heat treatment temperature and heat treatment period are regulated to 175 to 225° C. and 2 to 10 minutes, respectively. By the heat treatment, a mixture layer 35 comprising copper and tin is formed. Thereafter, a solder resist SOL is formed over the base insulating layer so as to cover the wiring pattern 12 and tin-plated layer 34 in given regions. Subsequently, the solder resist SOL is subjected to a heat curing treatment.

Abstract: A wafer laser processing method for forming deteriorated layers in the inside of a wafer having devices which are formed in a plurality of areas sectioned by a plurality of streets formed in a lattice pattern on the front surface along the streets by applying a laser beam along the streets, comprising: a first deteriorated layer forming step for forming a first deteriorated layer along the streets near the front surface of the wafer by applying a laser beam having a wavelength of 1,064 nm from the rear surface side of the wafer along the streets with its focal spot set to a position near the front surface of the wafer; and a second deteriorated layer forming step for forming a second deteriorated layer along the streets at a position closer to the rear surface of the wafer than the first deteriorated layer by applying a laser beam having a wavelength of 1,342 nm from the rear surface side of the wafer along the streets with its focal spot set to a position closer to the rear surface than the first deteriorate

Abstract: The present invention is directed to a method for fabricating a metal line of a semiconductor device. The method comprises the steps of forming an insulation layer, a metal layer and an organic anti-reflection coating in order on a semiconductor substrate on which devices or lower lines are formed, forming a photoresist pattern having an opening of certain width on the organic anti-reflection coating, forming a buffer layer of certain thickness on the photoresist pattern, and selectively removing the metal layer at a lower side of the opening by performing a dry etching process.

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: A method of forming an integrated circuit structure is provided. The method includes providing an interposer wafer; mounting the interposer wafer onto a handling wafer; thinning a backside of the interposer wafer; removing the handling wafer from the interposer wafer after the step of thinning; securing the interposer wafer on a fixture; and bonding a die on the interposer wafer.

Abstract: Particle formation in semiconductor fabrication process chambers is reduced by preventing condensation on the door plates that seal off the process chambers. Particles can be formed in a process chamber when reactant gases condense on the relatively cool surfaces of a door plate. This particle formation is minimized by heating the door plate to a temperature high enough to prevent condensation before flowing reactant gases into the process chamber. The door plate can be heated using a heat source, e.g., a resistive heater, that is in direct contact with the door plate or the heat source can heat the door plate from a distance by radiative or inductive heating. In addition, the door plate can open to allow loading and unloading of a wafer load. As it passes flanges near the door plate, the wafer load can transfer heat to those flanges. To prevent overheating, the flange is provided with a coolant-containing channel having walls that are spaced from the flange by O-rings.

Abstract: A semiconductor-chip exfoliating device for exfoliating a semiconductor chip 1 from an adhesive sheet 6 is provided. The device includes a backup holder 28 for holding the adhesive sheet 6 so that semiconductor chips 1 turn upward, a pair of needle pins arranged on a backside of the holder 28 to lift off the adhesive sheet 6 from the holder 28 through through-holes 31a, 31b in the holder 28 and a sliding unit 33 arranged on the backside of the holder 28 to slide one needle pin 30b in a direction to depart from the other needle pin 30a. By the sliding unit 33, the interval between the needle pins 30a, 30b can be changed so as to cope with a variation of semiconductor chips 1, 1A.

Abstract: A process for fabricating a chip embedded package structure is provided. A stiffener is disposed on a tape. A chip is disposed on the tape inside a chip opening of the stiffener such that an active surface of the chip faces the tape. Through holes are formed passing the tape and exposing bonding pads of the chip on the active surface respectively. Conductive material is deposited into the though holes to form a plurality of conductive vias which are connected to the bonding pads respectively. A multi-layered interconnection structure is formed on the tape on the opposite of the chip, wherein the multi-layered interconnection structure comprises an inner circuit which is connected to the conductive vias, and the inner circuit has a plurality of metallic pads on a surface of the multi-layered interconnection structure away from the tape.

Abstract: The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, and which exhibits no drop in bonding strength during panel bonding carried out after mounting of semiconductor chips, whereby reliability and productivity of a semiconductor chip mounting line is enhanced. The invention also provides a method of producing the COF flexible printed wiring board.

Abstract: A method of making an exposed-pad ball-grid array package (11) includes applying a conductive sheet (16) to an adhesive tape (18). Stamping the conductive sheet (16) to form a die pad (24) and separating the remainder (26) of the sheet from the adhesive tape (18) so that only the die pad (24) remains on the adhesive tape (18). A substrate (28) is applied to the adhesive tape (18) proximate to the die pad (24). A die (30) is attached to the die pad (24) and electrically coupled to the substrate (28). An encapsulant (34) is formed around at least a portion of the die (30), the die pad (24) and the substrate (28) above the adhesive tape (18). The adhesive tape (18) is removed from the die pad (24), substrate (28) and encapsulant (34). Conductive balls (36) are attached to the substrate (28).

Abstract: Salient electrodes on a semiconductor chip and leads on a film substrate are to be connected together with a high accuracy. A change in lead pitch which occurs at the time of connecting salient electrodes on a semiconductor chip and inner leads on a film substrate with each other is taken into account and a correction is made beforehand to the pitch of the inner leads. Likewise, a change in lead pitch which occurs at the time of connecting electrodes on a liquid crystal substrate and outer leads on the film substrate with each other is taken into account and a correction is made beforehand to the pitch of the outer leads.

Abstract: The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, to thereby enhance reliability and productivity of a semiconductor chip mounting line, and also provides a method of producing the COF flexible printed wiring board. The COF flexible printed wiring board contains an insulating layer, a wiring pattern, on which a semiconductor chip being mounted, formed of a conductor layer provided on at least one side of the insulating layer and a releasing layer, wherein the releasing layer is formed from a releasing agent containing at least one species selected from a silane compound and silica sol and is provided on a surface of the insulating layer, which is opposite to the mounting side of the semiconductor chip.

Abstract: Methods for fabricating stiffeners for flexible substrates, including, but not limited to, tapes, films, or other connective structures, which are configured to be secured to other semiconductor device components, are fabricated under control of a program. The stiffeners may be formed by selectively depositing or consolidating unconsolidated material. They may include a plurality of mutually adhered regions. The stiffeners may be configured to prevent torsional flexion or bending of the connective structure to which they are to be secured, to reinforce sprocket or indexing holes in connective structures or to include apertures through which intermediate conductive elements or other structures secured to the connective structure may be exposed or protrude.