Dielectric Regions, E.g., Epic Dielectric Isolation, Locos; Trench Refilling Techniques, Soi Technology, Use Of Channel Stoppers (epo) Patents (Class 257/E21.545)

  • Patent number: 7595558
    Abstract: A semiconductor device includes a first well formed in a predetermined region of a semiconductor substrate, a second well formed in a predetermined region in the first well, and a third well formed in the first well with the third well being spaced apart from the second well at a predetermined distance. A multiple well of the semiconductor substrate, the first well, the second well, the first well, and the third well, which are sequentially disposed, is formed. Accordingly, a breakdown voltage can be increased and a leakage current can be reduced. It is therefore possible to prevent the drop of an erase voltage and to reduce the error of an erase operation.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: September 29, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventor: Wan Cheul Shin
  • Patent number: 7592676
    Abstract: A cell includes a plurality of diffusion region pairs, each of the diffusion region pairs being formed by a first impurity diffusion region which is a constituent of a transistor and a second impurity diffusion region such that the first and second impurity diffusion regions are provided side-by-side in a gate length direction with a device isolation region interposed therebetween. In each of the diffusion region pairs, the first and second impurity diffusion regions have an equal length in the gate width direction and are provided at equal positions in the gate width direction, and a first isolation region portion, which is part of the device isolation region between the first and second impurity diffusion regions, has a constant separation length. In the diffusion region pairs, the first isolation region portions have an equal separation length.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: September 22, 2009
    Assignee: Panasonic Corporation
    Inventor: Kazuyuki Nakanishi
  • Publication number: 20090233413
    Abstract: A method for fabricating a semiconductor device using a SOI substrate, includes the steps of: preparing a SOI substrate, comprises a semiconductor support layer; an insulating layer formed on the semiconductor support layer; and a SOI layer formed on the insulating layer; forming an active region on the SOI layer, so that a part of the semiconductor support layer is exposed; and forming a specific mark on the exposed part of the semiconductor support layer.
    Type: Application
    Filed: March 9, 2009
    Publication date: September 17, 2009
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Takeshi Katayama
  • Patent number: 7586177
    Abstract: A method of fabricating a semiconductor-on-insulator semiconductor wafer is described that includes providing first and second semiconductor substrates. A first insulating layer is formed on the first substrate with a first predetermined stress and a second insulating layer is formed on the second substrate with a second predetermined stress different than the first predetermined stress. The first insulating layer is bonded to the second insulating layer to form a composite insulating layer bonding the first substrate to the second substrate and a portion of the one substrate is removed to form a thin crystalline active layer on the composite insulating layer. The first and second insulating layers are formed with different stresses to provide a desired composite stress, which can be any stress from compressive to unstressed to tensile, depending upon the desired application.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: September 8, 2009
    Assignee: Translucent, Inc.
    Inventor: Petar B. Atanakovic
  • Patent number: 7585745
    Abstract: A technique is provided which permits formation within a single chip both a field effect transistor of high reliability capable of suppressing the occurrence of a crystal defect and a field effect transistor of a high integration degree. In a mask ROM section having an element isolation region with an isolation width of smaller than 0.3 ?m, a planar shape of each active region ACT is made polygonal by cutting off the corners of a quadrangle, thereby suppressing the occurrence of a crystal defect in the active region ACT and diminishing a leakage current flowing between the source and drain of a field effect transistor. In a sense amplifier data latch section which is required to have a layout of a small margin in the alignment between a gate G of a field effect transistor and the active region ACT, the field effect transistor is disposed at a narrow pitch by making the active region ACT quadrangular.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: September 8, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Tetsuo Adachi, Akihiko Sato
  • Publication number: 20090206407
    Abstract: A semiconductor device and method of manufacturing is disclosed which has a tensile and/or compressive strain applied thereto. The method includes forming at least one trench in a material; and filling the at least one trench by an oxidation process thereby forming a strain concentration in a channel of a device. The structure includes a gate structure having a channel and a first oxidized trench on a first of the channel, respectively. The first oxidized trench creates a strain component in the channel to increase device performance.
    Type: Application
    Filed: February 19, 2008
    Publication date: August 20, 2009
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak, Edmund J. Sprogis
  • Publication number: 20090203187
    Abstract: To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. After partially forming a mask oxide film 23 on the surface of a substrate 12 constituted of single crystal silicon, oxygen ions 16 are implanted into the surface of the substrate through the mask oxide film, and the substrate is annealed to form an buried oxide film 13 inside the substrate. Further included is a step of forming a predetermined-depth concave portion 12c deeper than substrate surface 12b serving as a bulk area on which the mask oxide film is formed on the substrate surface 12a serving as an SOI area by forming a thermally grown oxide film 21 on the substrate surface 12a serving as an SOI area on which the mask oxide film is not formed between the step of forming the mask oxide film and the step of implanting oxygen ions.
    Type: Application
    Filed: April 14, 2009
    Publication date: August 13, 2009
    Applicants: SUMCO CORPORATION, KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuya NAKAI, Bong-Gyun KO, Takeshi HAMAMOTO, Takashi YAMADA
  • Publication number: 20090200633
    Abstract: A semiconductor structure with dual isolation structures is disclosed. The semiconductor structure may include a protruding isolation structure in a pixel array region of a substrate and an embedded isolation structure in a peripheral device region of the same substrate. A region of the protruding isolation structure extends from an upper surface of the substrate, while another region of the protruding isolation structure may, optionally, be embedded within the substrate. The embedded isolation structure is formed within the substrate and includes an upper surface that is substantially coplanar with the upper surface of the substrate. A method of forming the semiconductor structure with dual isolation structure is also disclosed.
    Type: Application
    Filed: February 7, 2008
    Publication date: August 13, 2009
    Applicant: Micron Technology, Inc.
    Inventors: James M. Chapman, Salman Akram
  • Publication number: 20090194843
    Abstract: An integrated circuit arrangement. In one embodiment, the arrangement includes at least one first semiconductor zone of a first conduction type which is doped more highly than the basic doping of a first semiconductor layer and which is arranged at a distance from a first component zone adjoining the first semiconductor layer. At least one connecting zone extends as far as the at least one first semiconductor zone proceeding from the first side. A second semiconductor zone of the second conduction type, is arranged in the first semiconductor layer and is electrically conductively connected to the at least one connecting zone.
    Type: Application
    Filed: February 1, 2008
    Publication date: August 6, 2009
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Joachim Weyers, Peter Nelle
  • Publication number: 20090191683
    Abstract: According to some embodiments of the invention, a method of forming a transistor includes forming a device isolation layer in a semiconductor substrate. The device isolation layer is formed to define at least one active region. A channel region is formed in a predetermined portion of the active region of the semiconductor substrate. Two channel portion holes are formed to extend downward from a main surface of the semiconductor substrate to be in contact with the channel region. Gate patterns fill the channel portion holes and cross the active region. The resulting transistor is capable of ensuring a constant threshold voltage without being affected by an alignment state of the channel portion hole and the gate pattern.
    Type: Application
    Filed: April 3, 2009
    Publication date: July 30, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-Ho SHIN, Jin-Woo LEE, Eun-Cheol LEE
  • Publication number: 20090184402
    Abstract: A method of fabricating a shallow trench isolation structure is provided. First, a pad oxide layer and a mask layer are formed sequentially on a substrate. Then, the mask layer and the pad oxide layer are patterned and the substrate is etched to form a trench. After that, a first liner is formed in the trench. Thereafter, a portion of the first liner is removed to expose corners of the trench. Then, a second liner is formed over the substrate to cover the corners of the trench and the first liner. The material of the second liner is different from that of the first liner. An insulation layer is further formed over the substrate to fill up the trench. The insulation layer, the second liner, the mask layer and the pad oxide layer outside the trench are eventually removed.
    Type: Application
    Filed: January 22, 2008
    Publication date: July 23, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventor: Chung-Chih Chen
  • Publication number: 20090179298
    Abstract: A superjunction semiconductor device is provided having at least one column of a first conductivity type and at least one column of a second conductivity type extending from a first main surface of a semiconductor substrate toward a second main surface of the semiconductor substrate opposed to the first main surface. The at least one column of the second conductivity type has a first sidewall surface proximate the at least one column of the first conductivity type and a second sidewall surface opposed to the first sidewall surface. A termination structure is proximate the second sidewall surface of the at least one column of the second conductivity type. The termination structure includes a layer of dielectric of an effective thickness and consumes about 0% of the surface area of the first main surface. Methods for manufacturing superjunction semiconductor devices and for preventing surface breakdown are also provided.
    Type: Application
    Filed: January 12, 2009
    Publication date: July 16, 2009
    Applicant: Icemos Technology Ltd.
    Inventor: Xu Cheng
  • Patent number: 7560389
    Abstract: A method for fabricating a semiconductor element on a semiconductor substrate having a support substrate and a semiconductor layer above the support substrate. The method includes preparing the semiconductor substrate having a transistor formation region and an element isolation region both defined thereon; forming a pad oxide film on the semiconductor layer of the semiconductor substrate; forming an oxidation-resistant mask layer on the pad oxide film; forming a resist mask to cover the transistor formation region on the oxidation-resistant mask layer; performing a first etching process for etching the oxidation-resistant mask layer using the resist mask as a mask to expose the pad oxide film of the element isolation region; and removing the resist mask and oxidizing the semiconductor layer below the exposed pad oxide film by LOCOS using the exposed oxidation-resistant mask layer as a mask to form an element isolation layer.
    Type: Grant
    Filed: May 8, 2006
    Date of Patent: July 14, 2009
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Kousuke Hara
  • Publication number: 20090173991
    Abstract: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic structures for use in a wide range of electronic devices and systems. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge traps.
    Type: Application
    Filed: March 23, 2009
    Publication date: July 9, 2009
    Inventors: Eugene P. Marsh, Brenda D. Kraus
  • Patent number: 7557415
    Abstract: A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing the corner portion of the semiconductor substrate, a nitride liner formed on the first oxide film, a second oxide film formed in contact with the upper end of the first oxide film and on the exposed corner portion and an upper surface of the semiconductor substrate, a field insulating film formed on the nitride liner to substantially fill the trench, and a field protecting film formed in contact with the second oxide film and filling a trench edge recess formed between the field insulating film and the second oxide film.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: July 7, 2009
    Assignee: Samsung Electroncis Co., Ltd.
    Inventors: Ki-seog Youn, Jong-hyon Ahn, Kwan-jong Roh, Hye-kyoung Lee
  • Patent number: 7557430
    Abstract: An improved semiconductor seal ring and method therefore is described. The seal ring comprises a thick layer wherein at least a portion of the thick layer is removed from a singulation street prior to singulation, thereby avoiding damage to the thick layer during the singulation process. A thin moisture-proof barrier layer is preferably deposited over at least a portion of the thick layer to seal at least an edge of the thick layer. A thick nonmetallic layer preferably used for fabrication of active circuit elements may advantageously be employed as the thick layer (for example, an aluminum nitride (AlN) layer in, for example, a bulk acoustic wave (BAW) filter device). A thin amorphous nonmetallic layer (e.g., a silicon nitride (SiN) layer) may preferably be deposited over the thick layer. Alternatively, other materials may be used.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: July 7, 2009
    Assignee: Skyworks Solutions, Inc.
    Inventors: Bradley Barber, Tony LoBianco, David T. Young
  • Publication number: 20090170280
    Abstract: A method of forming isolation layers of a semiconductor device, comprising providing a semiconductor substrate in which a tunnel dielectric layer and a conductive layer are formed in active regions having two ends and trenches are formed in isolation regions; rounding both ends of each active region by performing an O2 plasma process on the semiconductor substrate; forming a first insulating layer on sidewalls of each trench; and, forming a second insulating layer, preferably having a greater fluidity than that of the first insulating layer, on the first insulating layer.
    Type: Application
    Filed: June 27, 2008
    Publication date: July 2, 2009
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Bo Min Park
  • Publication number: 20090170281
    Abstract: The present invention relates to a method of forming an isolation layer of a semiconductor memory device. According to a method of fabricating a semiconductor memory device in accordance with an aspect of the present invention, a tunnel insulating layer and a charge trap layer are formed over a semiconductor substrate. An isolation trench is formed by etching the charge trap layer and the tunnel insulating layer. A passivation layer is formed on the entire surface including the isolation trench. A first insulating layer is formed at a bottom of the isolation trench. Portions of the passivation layer, which are oxidized in the formation process of the first insulating layer, are removed. A second insulating layer is formed on the entire surface including the first insulating layer.
    Type: Application
    Filed: June 27, 2008
    Publication date: July 2, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventors: Jong Hye CHO, Whee Won CHO, Eun Soo KIM
  • Publication number: 20090160011
    Abstract: The present invention relates to an isolator and a method of manufacturing the same. An isolator according to the present invention includes a silicon wafer, protective devices formed in predetermined regions of the silicon wafer, and a transformer formed in a predetermined region on the silicon wafer, the transformer having at least two coil patterns spaced apart from each other. According to the present invention, an isolator can be protected from impulses generated by ESD and surge, so that its reliability can be improved, and its size can be considerably decreased. Further, the number of wire bonding times is decreased, so that performance of a chip can be enhanced, and packaging efficiency can be improved, thereby increasing productivity.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 25, 2009
    Applicant: PETARI INCORPORATION
    Inventor: Young Jin PARK
  • Publication number: 20090162988
    Abstract: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.
    Type: Application
    Filed: February 27, 2009
    Publication date: June 25, 2009
    Inventors: Thomas Keena, Ki Chang, Francine Y. Robb, Mingjiao Liu, Ali Salih, John Michael Parsey, JR., George Chang
  • Patent number: 7547618
    Abstract: A system and method is disclosed for providing a deep connection to a substrate or buried layer of a semiconductor device. Three shallow trenches are etched halfway through a layer of epitaxial silicon that is located on a substrate. A second doped layer is created in the epitaxial silicon layer at the bottom of the central shallow trench. First and third doped layers are created in the epitaxial silicon layer adjacent to the central shallow trench. An oxide layer is then deposited to fill the three trenches. The second doped layer is diffused vertically down to the substrate. The first and third doped layers are diffused vertically down to the second doped layer. Lateral diffusion of the first and third doped layers is constrained by the oxide layer in the three trenches.
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: June 16, 2009
    Assignee: National Semiconductor Corporation
    Inventor: Richard W. Foote
  • Patent number: 7545020
    Abstract: Embodiments relate to a CMOS image sensor. In embodiments, the CMOS image sensor may include a semiconductor substrate, a photodiode, a first conduction type impurity region, a first insulating layer, a conduction layer, and a second insulating layer. The semiconductor substrate may have a trench in which a device isolation layer is to be formed. The photodiode may be formed in an active region of the semiconductor substrate, and the first conduction type impurity region may be formed in sidewalls of the trench. The first insulating layer may be formed inside the trench, and a conduction layer may be formed inside the trench and doped with second conduction type impurities. A second insulating layer may be formed inside the trench.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: June 9, 2009
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Joung Ho Lee
  • Publication number: 20090140377
    Abstract: A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor substrate of a low impurity concentration are laminated one over another. The semiconductor substrate includes a first semiconductor region of a first conductive type having a high impurity concentration, a second semiconductor region of a second conductive type having a high impurity concentration arranged so as to surround the first semiconductor region, a first main electrode joined to a surface of the first semiconductor region, and a second main electrode joined to a surface of the second semiconductor region. A first dielectric portion is arranged adjacent the embedded dielectric layer so as to surround a region of the support substrate superposed on the first semiconductor region in a direction of lamination thereof, and a wire connected with the first main electrode.
    Type: Application
    Filed: December 29, 2008
    Publication date: June 4, 2009
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Hajime Akiyama
  • Patent number: 7541247
    Abstract: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure. The semiconductor structure includes a semiconductor substrate. The method further includes simultaneously forming a first doped transistor region of a first transistor and a first doped guard-ring region of a guard ring on the semiconductor substrate. The first doped transistor region and the first doped guard-ring region comprise dopants of a first doping polarity. The method further includes simultaneously forming a second doped transistor region of the first transistor and a second doped guard-ring region of the guard ring on the semiconductor substrate. The second doped transistor region and the second doped guard-ring region comprise dopants of the first doping polarity. The second doped guard-ring region is in direct physical contact with the first doped guard-ring region. The guard ring forms a closed loop around the first and second doped transistor regions.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: June 2, 2009
    Assignee: International Business Machines Corporation
    Inventor: Steven Howard Voldman
  • Publication number: 20090126773
    Abstract: A plurality of photoelectric conversion elements delimited by connection line regions and isolation line regions are provided on a glass substrate having an external profile of a right triangle. A connection line region is configured to connect photoelectric conversion elements in series. An isolation line region is configured to electrically isolate adjacent photoelectric conversion elements and to separate (divide) photoelectric conversion elements by a predetermined area. A connection line region is orthogonal to an isolation line region. The external profile of a photoelectric conversion elements represents a rectangle. An external interconnection to electrically connect photoelectric conversion elements is formed at an outer circumferential region of the glass substrate at the side outer to the region where photoelectric conversion elements are formed.
    Type: Application
    Filed: February 8, 2006
    Publication date: May 21, 2009
    Inventor: Akira Shimizu
  • Publication number: 20090127648
    Abstract: A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a first deposition step to fill a first dielectric material into the opening using a first deposition method. The first deposition method has a bottom deposition rate substantially greater than a sidewall deposition rate. The method further includes isotropically etching the first dielectric material, wherein at least a bottom portion of the first dielectric material remains after the etching; and performing a second deposition step to fill a remaining portion of the opening with a second dielectric material. The first deposition method may be a high-density plasma chemical vapor deposition. The second deposition method may be a high-aspect ratio process.
    Type: Application
    Filed: January 3, 2008
    Publication date: May 21, 2009
    Inventors: Neng-Kuo Chen, Chih-Hsiang Chang, Cheng-Yuan Tsai, Wei-Chung Wang, Chun-Te Li
  • Publication number: 20090127624
    Abstract: A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.
    Type: Application
    Filed: November 4, 2008
    Publication date: May 21, 2009
    Applicant: DENSO CORPORATION
    Inventors: Masakiyo Sumitomo, Makoto Asai, Nozomu Akagi, Yasuhiro Kitamura, Hiroki Nakamura, Tetsuo Fujii
  • Publication number: 20090130818
    Abstract: A method for preparing a recessed gate structure comprises the steps of: forming a shallow trench isolation structure surrounding an active area in a silicon substrate, wherein an etching barrier layer is formed on the surface of the shallow trench isolation structure; forming a plurality of gate trenches in the active area of the silicon substrate by performing an etching process; and forming a recessed gate structure by filling the gate trench with a predetermined height.
    Type: Application
    Filed: January 29, 2008
    Publication date: May 21, 2009
    Applicant: PROMOS TECHNOLOGIES INC.
    Inventor: TSUNG TE LIN
  • Patent number: 7531403
    Abstract: SOI semiconductor components and methods for their fabrication are provided wherein the SOI semiconductor components include an MOS transistor in the supporting semiconductor substrate. In accordance with one embodiment the component comprises a semiconductor on insulator (SOI) substrate having a first semiconductor layer, a layer of insulator on the first semiconductor layer, and a second semiconductor layer overlying the layer of insulator. The component includes source and drain regions of first conductivity type and first doping concentration in the first semiconductor layer. A channel region of second conductivity type is defined between the source and drain regions. A gate insulator and gate electrode overlie the channel region. A drift region of first conductivity type is located between the channel region and the drain region, the drift region having a second doping concentration less than the first doping concentration of first conductivity determining dopant.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: May 12, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ali Icel, Qiang Chen, Mario M. Pelella
  • Publication number: 20090117705
    Abstract: The present invention relates to a method of forming isolation layers of a semiconductor device. According to a method of forming isolation layers of a semiconductor device in accordance with an aspect of the present invention, a tunnel insulating layer, a charge trap layer, and a hard mask layer are sequentially formed over a semiconductor substrate. First trenches are formed by etching the hard mask layer, the charge trap layer, the tunnel insulating layer, and the semiconductor substrate. A spacer layer is formed on the entire surface including the first trenches. Second trenches are formed by etching the spacer layer, which is formed at a bottom of the first trenches, and the semiconductor substrate. An insulating layer for isolation is formed on the entire surface including the second trenches.
    Type: Application
    Filed: June 27, 2008
    Publication date: May 7, 2009
    Applicant: Hynix Semiconductor Inc.
    Inventor: Kwang Seok Oh
  • Patent number: 7528463
    Abstract: An apparatus and a method for forming the apparatus include a semiconductor layer on an insulating substrate, where the substrate is a different material than the semiconductor layer, and has a coefficient of thermal expansion substantially equal to that of the semiconductor layer. The semiconductor layer can also be formed having a thickness such that it does not yield due to temperature-induced strain at device processing temperatures. A silicon layer bonded to a silicon oxycarbide glass substrate provides a silicon on insulator wafer in which circuitry for electronic devices is fabricated.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: May 5, 2009
    Assignee: Micron Technolgy, Inc.
    Inventor: Leonard Forbes
  • Patent number: 7521333
    Abstract: A device isolation structure of semiconductor device includes a semiconductor substrate having a cell region, a low voltage region and a high voltage region defined therein. A cell trench isolation region is disposed in the cell region. A low voltage trench isolation region is disposed in the low voltage region and extends deeper into the substrate than the cell trench isolation region. A first high voltage trench isolation region is disposed in the high voltage region and extends deeper into the substrate than the low voltage trench isolation region. A second high voltage trench isolation region is disposed in the high voltage region and extends deeper into the substrate than the low voltage trench isolation region but shallower than the first high voltage trench isolation region.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: April 21, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun-Young Choi, Jung-Min Son
  • Publication number: 20090096055
    Abstract: An STI field oxide element in an IC which includes a layer of epitaxial semiconductor on sidewalls of the STI trench to increase the width of the active area adjacent to the STI trench and decrease a width of dielectric material in the STI trench is disclosed. STI etch residue is removed from the STI trench surface prior to growth of the epitaxial layer. The epitaxial semiconductor composition is matched to the composition of the adjacent active area. The epitaxial semiconductor may be undoped or doped to match the active area. The STI trench with the epitaxial layer is compatible with common STI passivation and fill processes. The thickness of the as-grown epitaxial semiconductor layer is selected to provide a desired active area width or a desired STI dielectric width.
    Type: Application
    Filed: August 7, 2008
    Publication date: April 16, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Clint L. Montgomery, Brian K. Kirkpatrick, Weize Xiong, Steven L. Prins
  • Patent number: 7518214
    Abstract: An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: April 14, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-chan Lim, Byung-hee Kim, Tae-ho Cha, Hee-sook Park, Geum-jung Seong
  • Patent number: 7514317
    Abstract: A method of making a semiconductor device is disclosed. A semiconductor body, an STI region, a gate and a silicided source/drain region are provided. The STI area is etched, and a liner is formed at the upper surface.
    Type: Grant
    Filed: September 15, 2006
    Date of Patent: April 7, 2009
    Assignee: Infineon Technologies AG
    Inventor: Richard Lindsay
  • Publication number: 20090085128
    Abstract: A semiconductor device includes a semiconductor substrate including a plurality of device regions and a device isolation region defining the device regions, and a semiconductor element located in a major surface of the semiconductor substrate and formed in at least one of the device regions. The device isolation region has a DTI (deep trench isolation) structure and has a bottom exposed to a backside of the semiconductor substrate.
    Type: Application
    Filed: September 29, 2008
    Publication date: April 2, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuki Nakamura, Masaaki Yamamoto, Katsu Honna, Hisanori Furumi
  • Patent number: 7510981
    Abstract: A semiconductor device includes an element isolation film, which exhibits less variations in the height dimension from the surface of the substrate and has a desired height dimension from the surface of the substrate. A process for manufacturing a semiconductor device includes: providing a predetermined pattern of a silicon nitride film and a protective film which covers the silicon nitride film, on a semiconductor substrate; selectively etching the semiconductor substrate using the protective film as a mask to form a trenched portion; removing the protective film to expose the silicon nitride film; depositing an element isolation film, so as to fill the trenched portion therewith and cover the silicon nitride film; removing the element isolation film formed on the silicon nitride film by polishing thereof until the silicon nitride film is exposed; and removing the silicon nitride film.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: March 31, 2009
    Assignee: NEC Electronics Corporations
    Inventors: Akira Mitsuiki, Tomoo Nakayama, Osamu Fujita
  • Publication number: 20090079039
    Abstract: A semiconductor device includes a semiconductor chip, a moisture resistant ring provided in the semiconductor chip and having a chamfered flat part in a position corresponding to a corner of the semiconductor chip, and a first monitor pattern formed inside the moisture resistant ring. At least a part of the first monitor pattern is disposed inside an n-sided polygonal area (n is a natural number which is 4 or higher than 4) situated within the moisture resistant ring, and outside a quadrangular area situated inside the n-sided polygonal area. The n-sided polygonal area has a vertex at least at each of a first end and a second end of the chamfered flat part, and the quadrangular area has a vertex at least at a middle point of the chamfered flat part.
    Type: Application
    Filed: September 10, 2008
    Publication date: March 26, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Kazushi FUJITA, Ryota NANJO
  • Publication number: 20090078991
    Abstract: A stress-enhanced semiconductor device is provided which includes a substrate having an inactive region and an active region, a first-type stress layer overlying at least a portion of the active region, and a second-type stress layer. The active region includes a first lateral edge which defines a first width of the active region, and a second lateral edge which defines a second width of the active region. The second-type stress layer is disposed adjacent the second lateral edge of the active region.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Akif SULTAN, Mark MICHAEL, David WU, Donna Michael
  • Publication number: 20090078318
    Abstract: A photovoltaic cell can include an interfacial layer in contact with a semiconductor layer.
    Type: Application
    Filed: September 24, 2008
    Publication date: March 26, 2009
    Applicant: First Solar, Inc.
    Inventors: Peter Meyers, Akhlesh Gupta, David Eaglesham
  • Publication number: 20090057798
    Abstract: There is provided a method of producing a semiconductor device. The method includes the steps of: forming a first hard mask having an opening above a substrate; forming a sacrificial film above a side surface of the opening of the first hard mask; forming a second hard mask in the opening having the sacrificial film above the side surface; removing the sacrificial film after the second hard mask is formed; ion implanting a first conductivity-type impurity through the first hard mask; and ion implanting a second conductivity-type impurity through the first and second hard masks.
    Type: Application
    Filed: August 18, 2008
    Publication date: March 5, 2009
    Applicant: Sony Corporation
    Inventor: Yasufumi Miyoshi
  • Patent number: 7498265
    Abstract: Memory cell structures, including PSOIs, NANDs, NORs, FinFETs, etc., and methods of fabrication have been described that include a method of epitaxial silicon growth. The method includes providing a silicon layer on a substrate. A dielectric layer is provided on the silicon layer. A trench is formed in the dielectric layer to expose the silicon layer, the trench having trench walls in the <100> direction. The method includes epitaxially growing silicon between trench walls formed in the dielectric layer.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: March 3, 2009
    Assignee: Micron Technology, Inc.
    Inventors: David H. Wells, Du Li
  • Patent number: 7491563
    Abstract: A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: February 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Fred Buehrer, Anthony I. Chou, Toshiharu Furukawa, Renee T Mo
  • Publication number: 20090035916
    Abstract: When manufacturing a semiconductor device, an isolation layer is formed on a semiconductor substrate to define an active region that includes gate forming area. Portions of the isolation layer that are adjacent to the gate forming area of the active region are etching by a dry cleaning process which utilizes NH3 gas and HF gas to form a fin pattern, in which the gate forming area of the active region protrude. Gate is formed on the fin pattern and on the etched portions of the isolation layer to surround the fin pattern. The dry cleaning process has a high etch selectivity between the semiconductor substrate and the isolation layer, which allows for the effective adjustment of the height of the fin patterns.
    Type: Application
    Filed: May 12, 2008
    Publication date: February 5, 2009
    Inventor: Jung Nam KIM
  • Patent number: 7485544
    Abstract: In various method embodiments, a device region is defined in a semiconductor substrate and isolation regions are defined adjacent to the device region. The device region has a channel region, and the isolation regions have volumes. The volumes of the isolation regions are adjusted to provide the channel region with a desired strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from a crystalline region to an amorphous region to expand the volumes of the isolation regions and provide the channel region with a desired compressive strain. In various embodiments, adjusting the volumes of the isolation regions includes transforming the isolation regions from an amorphous region to a crystalline region to contract the volumes of the isolation regions to provide the channel region with a desired tensile strain. Other aspects and embodiments are provided herein.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: February 3, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Paul A. Farrar
  • Patent number: 7482243
    Abstract: The present invention provides a method of forming a thin channel MOSFET having low external resistance. The method comprises forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: January 27, 2009
    Assignee: International Business Machines Corporation
    Inventors: Diane C. Boyd, Bruce B. Doris, Meikei Ieong, Devendra K. Sadana
  • Patent number: 7482245
    Abstract: High density plasma (HDP) techniques form silicon oxide films having sequentially modulated stress profiles. The HDP techniques use low enough temperatures to deposit silicon oxide films in transistor architectures and fabrication processes effective for generating channel strain without adversely impacting transistor integrity. Methods involve partially filling a trench on a substrate with a portion of deposited dielectric using a high density plasma chemical vapor deposition process. The conditions of the process are configured to produce a first stress condition in the first portion of the deposited dielectric. The deposition process condition may then be modified to produce a different stress condition in deposited dielectric. The partially-filled trench may be further filled using the modified deposition process to produce additional dielectric and can be repeated until the trench is filled. Transistor strain can be generated in NMOS or PMOS devices using stress profile modulation in STI gap fill.
    Type: Grant
    Filed: June 20, 2006
    Date of Patent: January 27, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Jengyi Yu, Chi-I Lang, Judy H. Huang
  • Patent number: 7468302
    Abstract: A method of forming a trench type isolation film of a semiconductor device, including the steps of sequentially forming a pad oxide film and a nitride film for a hard mask on a semiconductor substrate in which a cell region and a peri region are defined; patterning the nitride film using an etch process employing a cell array mask; coating a photoresist on the entire structure including the patterned nitride film; patterning the photoresist using a peri ISO mask; sequentially etching the nitride film, the pad oxide film, and the semiconductor substrate using the patterned photoresist as an etch mask, thereby forming first trenches; stripping the photoresist; etching the semiconductor substrate of the cell region and the peri region using the patterned nitride film as an etch mask, thereby forming second trenches in the cell region and third trenches, which are consecutive to the first trenches, in the peri region; and, forming an isolation film within the second and third trenches.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: December 23, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyeon Sang Shin
  • Publication number: 20080305613
    Abstract: Methods are provided for fabricating a semiconductor on insulator (SOI) component on a semiconductor layer/insulator/substrate structure. The method includes forming one or more shallow trench isolation (STI) regions extending through the semiconductor layer to the insulator. First and second openings are etched through the STI and the insulator using the remaining SOI material in the semiconductor layer as an etch mask. N— and P-type ions are implanted into the substrate through the openings to form to form N-doped and P-doped regions therein, such as an anode and a cathode of a semiconductor diode structure. The N-doped and P-doped regions are closely spaced and precisely aligned to each other by the SOI material in the semiconductor layer. Electrical contacts are then made to the N-doped and P-doped regions.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 11, 2008
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Mario M. PELELLA, Darin A. CHAN
  • Publication number: 20080303075
    Abstract: A method for forming an element isolation structure of a semiconductor device, includes: a trench forming step of forming a trench on a semiconductor substrate; and a laminating step of forming alternately multilayered film in the trench by sequentially and alternately laminating a plurality of first insulating films that apply tensile stress to the semiconductor substrate and a plurality of second insulating films that apply compression stress to the semiconductor substrate so that the trench is filled with the alternately multilayered film.
    Type: Application
    Filed: June 9, 2008
    Publication date: December 11, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Tsuyoshi SETOKUBO