Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.

Abstract: A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.

Abstract: A method for forming an isolation structure of a semiconductor device is provided. The method includes forming a patterned dielectric structure in a first area and a second area of a substrate; forming a first isolation structure in the first area and forming a second isolation structure in the second area of the substrate; forming a cap layer over the first area and the second area of the substrate and performing an etching process to etch the cap layer of the second area completely; and performing an oxidation process on the second area to form a first oxide region over the second isolation structure and under the bottom surface of the patterned dielectric structure of the second area.

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a plurality of element-separating insulators, and contacts. The plurality of element-separating insulators partition the upper layer portion into a plurality of active areas extending in a first direction. The contacts are connected to the active areas. A recess is made in a part in the first direction of an upper surface of each of the active areas. The recess is made across the entire active area in a second direction orthogonal to the first direction. Positions in the first direction of two of the contacts connected respectively to mutually-adjacent active areas are different from each other. One of the contacts is in contact with a side surface of the recess and not in contact with a bottom surface of the recess.

Abstract: A trench MOSFET comprising source regions having a doping profile of a Gaussian-distribution along the top surface of epitaxial layer and floating dummy cells formed between edge trench and active area is disclosed. A SBR of n region existing at cell corners renders the parasitic bipolar transistor difficult to turn on, and the floating dummy cells having no parasitic bipolar transistor act as buffer cells to absorb avalanche energy when gate bias is increasing for turning on channel, therefore, the UIS failure issue is avoided and the avalanche capability of the trench MOSFET is enhanced.

Abstract: Disclosed are methods for manufacturing a floating gate memory device and the floating gate memory device thus obtained. In one embodiment, a method is disclosed that includes providing a semiconductor-on-insulator substrate, forming at least two trenches in the semiconductor-on-insulator substrate, and, as a result of forming the at least two trenches, forming at least one elevated structure. The method further includes forming isolation regions at a bottom of the at least two trenches by partially filling the at least two trenches, thermally oxidizing sidewall surfaces of at least a top portion of the at least one elevated structure, thereby providing a gate dielectric layer on at least the exposed sidewall surfaces; and forming a conductive layer over the at least one elevated structure, the gate dielectric layer, and the isolation regions to form at least one floating gate semiconductor memory device.

Abstract: A semiconductor process is provided. A mask layer is formed on a substrate and has a first opening exposing a portion of the substrate. Using the mask layer as a mask, a dry etching process is performed on the substrate to form a second opening therein. The second opening has a bottom portion and a side wall extending upwards and outwards from the bottom portion, wherein the bottom portion is exposed by the first opening and the side wall is covered by the mask layer. Using the mask layer as a mask, a vertical ion implantation process is performed on the bottom portion. A conversion process is performed, so as to form converting layers on the side wall and the bottom portion of the second opening, wherein a thickness of the converting layer on the side wall is larger than a thickness of the converting layer on the bottom portion.

Abstract: A method of processing copper backside metal layer for semiconductor chips is disclosed. The backside of a semiconductor wafer, with electronic devices already fabricated on the front side, is first coated with a thin metal seed layer by either electroless plating or sputtering. Then, the copper backside metal layer is coated on the metal seed layer. The metal seed layer not only increases the adhesion between the front side metal layer and the copper backside metal layer through backside via holes, but also prevents metal peeling from semiconductor's substrate after subsequent fabrication processes, which is helpful for increasing the reliability of device performances. Suitable materials for the metal seed layer includes Pd, Au, Ni, Ag, Co, Cr, Pt, or their alloys, such as NiP, NiB, AuSn, Pt—Rh and the likes. The use of Pd as seed layer is particularly useful for the copper backside metal layer, because the Pd layer also acts as a diffusion barrier to prevent Cu atoms entering the semiconductor wafer.

Abstract: The present invention relates to a semiconductor device with a plurality of mark through substrate vias, including a semiconductor substrate, a plurality of original through substrate vias and a plurality of mark through substrate vias. The original through substrate vias and the mark through substrate vias are disposed in the semiconductor substrate and protrude from the backside surface of the semiconductor substrate. The mark through substrate vias are added at a specific position and/or in a specific pattern and serve as a fiducial mark, which facilitates identifying the position and direction on the backside surface. Thus, the redistribution layer (RBL) or the special equipment for achieving the backside alignment (BSA) is not necessary.

Abstract: Methods are provided for fabricating a semiconductor device. A method comprises forming a layer of a first semiconductor material overlying the bulk substrate and forming a layer of a second semiconductor material overlying the layer of the first semiconductor material. The method further comprises creating a fin pattern mask on the layer of the second semiconductor material and anisotropically etching the layer of the second semiconductor material and the layer of the first semiconductor material using the fin pattern mask as an etch mask. The anisotropic etching results in a fin formed from the second semiconductor material and an exposed region of first semiconductor material underlying the fin. The method further comprises forming an isolation layer in the exposed region of first semiconductor material underlying the fin.

Abstract: A silicon on insulator (SOI) complementary metal oxide semiconductor (CMOS) with an isolation formed at a low temperature and methods for constructing the same. An example method includes infusing an insulation material at a low temperature to form a silicon-based insulator between the active regions.

Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.

Abstract: A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A semiconductor substrate is prepared. The semiconductor substrate has a first region and a second region other than the first region. A first mask is formed over the first region. The first mask has a first line-and-space pattern extending in a first direction. A first removing process is performed. The first removing process selectively removes the first region with the first mask to form a first groove extending in the first direction. The first removing process removes an upper part of the second region while a remaining part of the second region having a first surface facing upward. The bottom level of the first groove is higher than the level of the first surface.

Abstract: A method of forming a capacitor structure includes forming a pad oxide layer overlying a substrate, a nitride layer overlying the pad oxide layer, an interlayer dielectric layer overlying the nitride layer, and a patterned polysilicon mask layer overlying the interlayer dielectric layer. The method then applies a first RIE process to form a trench region through a portion of the interlayer dielectric layer using the patterned polysilicon mask layer and maintaining the first RIE to etch through a portion of the nitride layer and through a portion of the pad oxide layer. The method stops the first RIE when a portion of the substrate has been exposed. The method then forms an oxide layer overlying the exposed portion of the substrate and applies a second RIE process to continue to form the trench region by removing the oxide layer and removing a portion of the substrate to a predetermined depth.

Abstract: A semiconductor device including a CMP dummy pattern and a method for manufacturing the same are provided. The warpage of a wafer can be prevented by forming the CMP dummy pattern in the same direction and/or at the same angle as a pattern of a cell region. Accordingly, overlay error caused by etching residues is reduced, thereby improving the yield of the semiconductor device.

Abstract: A method for dissolving the buried oxide layer of a SeOI wafer in order to decrease its thickness. The SeOI wafer includes a thin working layer made from one or more semiconductor material(s); a support layer, and a buried oxide (BOX) layer between the working layer and the support layer. The dissolution rate of the buried oxide layer is controlled and set to be below 0.06 ?/sec.

Abstract: A substrate may have active areas at different levels separated by a mask. Along the mask may be a shallow trench isolation. Along the shallow trench isolation may be a LOCOS isolation. The shape of a substrate transition region between the levels may be tunably controlled. The shallow trench isolation may reduce the bird's beak effect.

Abstract: The invention is directed to a semiconductor device having a via hole and a method of manufacturing the same that achieve both the prevention of a barrier layer insufficiently covering the via hole and the control of via resistance at the same time. A semiconductor substrate having a pad electrode on its front surface is prepared. The semiconductor substrate is etched from its back surface to its front surface to form a via hole exposing the pad electrode. A first barrier layer is then formed in the via hole by a sputtering method or a PVD method and reverse-sputtering (etching). By this reverse-sputtering, the barrier layer on the bottom of the via hole is removed to expose the pad electrode. A second barrier layer is then formed on the pad electrode exposed in the via hole. The via resistance is controlled by adjusting only the thickness of the second barrier layer.

Abstract: A method of filling a trench comprises heating a semiconductor substrate having a trench formed therein and an oxide film formed at least on the sidewall of the trench and supplying an aminosilane gas to the surface of the substrate so as to form a seed layer on the semiconductor substrate, heating the semiconductor substrate having the seed layer formed thereon and supplying a monosilane gas to the surface of the seed layer so as to form a silicon film on the seed layer, filling the trench of the semiconductor substrate, which has the silicon film formed thereon, with a filling material that shrinks by burning, and burning the semiconductor substrate coated by the filling material filling the trench in an atmosphere containing water and/or a hydroxy group while changing the filling material into a silicon oxide and changing the silicon film and the seed layer into a silicon oxide.

Abstract: The present invention discloses methods for depositing a material, particularly a conductive material, in cavities of a substrate and forming bonding contacts or pads thereon. An intracavity structure may be utilized in conjunction with embodiments of the present invention to provide efficient filling of diverse cavities within the substrate. Also provided are embodiments for interconnection structures using filled cavities, along with electrically conductive or reactive structures which may include capacitors fabricated within a substrate.

Abstract: A semiconductor device has: a silicon substrate; trench formed downward from the surface of the silicon substrate, the trench defining active regions on the surface of the silicon substrate; a first liner layer of a silicon nitride film covering an inner wall of the trench; a second liner layer of a silicon nitride layer formed on the first liner layer; an element isolation region of an insulator formed on the second liner layer; a p-channel MOS transistor formed in and on one of the active regions; a contact etch stopper layer of a silicon nitride layer not having a ultraviolet shielding ability, formed above the silicon substrate, and covering the p-channel MOS transistor; and a light shielding film of a silicon nitride layer having the ultraviolet shielding ability and formed above the contact etch stopper layer.

Abstract: A trench MOSFET structure having improved avalanche capability is disclosed, wherein the source region is formed by performing source Ion Implantation through contact open region of a contact interlayer, and further diffused to optimize a trade-off between Rds and the avalanche capability. Thus, only three masks are needed in fabrication process, which are trench mask, contact mask and metal mask. Furthermore, said source region has a doping concentration along channel region lower than along contact trench region, and source junction depth along channel region shallower than along contact trench, and source doping profile along surface of epitaxial layer has Guassian-distribution from trenched source-body contact to channel region.

Abstract: A manufacturing method for a semiconductor-device isolation structure comprises providing a substrate with at least one shallow trench isolation structure, performing a salicide process that forms a recess on the surface of the shallow trench isolation structure, forming a cap film covering the substrate and filling the recess, performing an etching process to remove the cap film outside the recess, and forming a contact etch stop layer covering the substrate and filling the recess. Due to the filling recess with the cap film first, the contact etch stop layer covering the substrate and filling the recess does not have seams or voids.

Abstract: In accordance with the teachings described herein, a method for fabricating a patterned polysilicon layer having a planar surface may include the steps of: depositing a polysilicon film above a substrate material; depositing an oxide-resistant mask over the polysilicon film; patterning and etching the oxide-resistant mask to form a patterned mask layer over the polysilicon film, such that the polysilicon film includes masked and unmasked portions; etching the unmasked portions of the polysilicon film for a first amount of time; oxidizing the etched polysilicon film for a second amount of time to form an oxide layer that defines the patterned polysilicon layer; and removing the patterned mask layer; wherein the first and second amounts of time are selected such that the oxide layer and the patterned polysilicon layer have about the same thickness and form a planar surface.

Abstract: A method of forming a fine pattern of a semiconductor device uses a double patterning technique. A first mask pattern is formed on a first hard mask layer disposed on a substrate. A conformal buffer layer is formed over the first mask pattern. A second mask pattern is formed such that segments of the buffer layer are interposed between the first and second mask patterns, and each topographical feature of the second mask pattern is disposed between two adjacent ones of each respective pair of topographical features of the first mask pattern. A first hard mask pattern is formed by etching the first hard mask layer using the first mask pattern, the second mask pattern, and/or the buffer layer as an etch mask. A trench is formed by etching the substrate using the first hard mask pattern as an etch mask. An isolation layer, of a material that is different from that of first hard mask pattern, is formed in the trench.

Abstract: Provided are a semiconductor device and a method of forming the same. According to the method, a first buried oxide layer is locally formed in a semiconductor substrate and a core semiconductor pattern of a line form, a pair of anchor-semiconductor patterns and a support-semiconductor pattern are formed by patterning a semiconductor layer on the first buried oxide layer to expose the first buried oxide layer. The pair of anchor-semiconductor patterns contact both ends of the core semiconductor pattern, respectively, and the support-semiconductor pattern contacts one sidewall of the core semiconductor pattern, the first buried oxide layer below the core semiconductor pattern is removed. At this time, a portion of the first buried oxide layer below each of the anchor-semiconductor patterns and a portion of the first buried oxide layer below the support-semiconductor pattern remain. A second buried oxide layer is formed to fill a region where the first buried oxide layer below the core semiconductor pattern.

Abstract: In-situ semiconductor process that can fill high aspect ratio (typically at least 6:1, for example 7:1 or higher), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots is provided. This deposition part of the process may involve the use of any suitable high density plasma chemical vapor deposition (HDP CVD) chemistry. Prior to etch back, the feature gap is plugged with an etch selectivity layer. The etch back part of the process involves multiple steps including a sputter etch to reduce the top hat formations followed by a reactive plasma etch to open the gap. This method improves gapfill, reduces the use of high cost fluorine-based etching and produces interim gaps with better sidewall profiles and aspect ratios.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a first surface and a second surface which is arranged opposite to the first surface. The semiconductor substrate includes a plurality of trench structures extending from the first surface into the semiconductor substrate. The thickness of the semiconductor substrate is then reduced by removing semiconductor material at the second surface to obtain a processed second surface with exposed bottom portions of the trench structures. At least a first mask is formed on the processed second surface in a self-aligned manner with respect to the bottom portions of the trench structures, and doping regions are formed in the semiconductor substrate between the trench structures.

Abstract: Methods for forming thin dielectric films by selectively depositing a conformal film of dielectric material on a high aspect ratio structure have uses in semiconductor processing and other applications. A method for forming a dielectric film involves providing in a deposition reaction chamber a substrate having a gap on the surface. The gap has a top opening and a surface area comprising a bottom and sidewalls running from the top to the bottom. A conformal silicon oxide-based dielectric film is selectively deposited in the gap by first preferentially applying a film formation catalyst or a catalyst precursor on a portion representing less than all of the gap surface area. The substrate surface is then exposed to a silicon-containing precursor gas such that a silicon oxide-based dielectric film layer is preferentially formed on the portion of the gap surface area.

Abstract: A method for producing a micromechanical diaphragm sensor, and a micromechanical diaphragm sensor produced with the method. The micromechanical diaphragm sensor has at least one first diaphragm as well as a second diaphragm, which is disposed essentially on top of the first diaphragm. Furthermore, the micromechanical diaphragm sensor has a first cavity and a second cavity, which is essentially disposed above the first cavity.

Abstract: A method for manufacturing a semiconductor device that controls the influence of a thickness of a stopper film even if there is a change in the thickness of the stopper film by measuring the thickness prior to etching to a predetermined thickness.

Abstract: A low-temperature co-fired ceramics (LTCC) substrate includes a plurality of substrate units and at least one cutting pattern. The cutting pattern is disposed between neighboring two of the substrate units. A semiconductor package including the LTCC substrate is also disclosed.

Abstract: A method of filling a recess with an insulation film includes: introducing an alkoxysilane or aminosilane precursor containing neither a Si—C bond nor a C—C bond into a reaction chamber where a substrate having an irregular surface including a recess is placed; and depositing a flowable Si-containing insulation film on the irregular surface of the substrate to fill the recess therewith by plasma reaction at ?50° C. to 100° C.

Abstract: In a method of manufacturing a semiconductor device including a planar type transistor and a fin type transistor, a substrate having a first region and a second region is partially to form an isolation trench defining an isolation region and an active region. An insulation layer liner is formed on sidewalls of the isolation trench in the first region and the second region. An isolation layer fills an inner portion of the isolation trench. The insulation layer liner is partially removed to expose an upper surface of the substrate in the gate region of the first region, and an upper surface and sidewalls of the substrate in the gate region of the second region. A gate oxide layer and a gate electrode are formed on the exposed substrate.

Abstract: A trench MOSFET structure having improved avalanche capability is disclosed, wherein the source region is formed by performing source Ion Implantation through contact open region of a thick contact interlayer, and further diffused to optimize a trade-off between Rds and the avalanche capability. Thus, only three masks are needed in fabrication process, which are trench mask, contact mask and metal mask. Furthermore, said source region has a doping concentration along channel region lower than along contact trench region, and source junction depth along channel region shallower than along contact trench, and source doping profile along surface of epitaxial layer has Gaussian-distribution from trenched source-body contact to channel region.

Abstract: Disclosed are a transistor and a method for fabricating the same capable of increasing a threshold voltage and a driving current of the transistor. The method includes the steps of forming a first etch mask on a silicon substrate, forming a trench by etching the exposed isolation area, forming a first insulation layer in the trench and the first etch mask, forming a second insulation layer on the first insulation layer, removing the second insulation layer and the first insulation layer until the first etch mask is exposed, forming a trench type isolation layer on the isolation area, forming a second etch mask on an entire surface of the silicon substrate, etching the exposed channel area, performing an etching process with respect to a resultant substrate structure, and forming a gate in the recess.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a first transistor having a first active area, and a second transistor having a second active area. A top surface of the first active area is elevated or recessed with respect to a top surface of the second active area, or a top surface of the first active area is elevated or recessed with respect to a top surface of at least portions of an isolation region proximate the first transistor.

Abstract: A semiconductor device including an active pattern having a channel recess portion, and a method of fabricating the same, are disclosed. In one embodiment, the semiconductor device includes an active pattern including first active regions and a second active region interposed between the first active regions. The active pattern protrudes above a surface of a semiconductor substrate and includes a channel recess portion above the second active region and between the first active regions. A device isolation layer surrounds the active pattern and has a groove exposing side walls of the recessed second active region. A distance between opposing side walls of the first active regions exposed by the channel recess portion is greater than a distance between side walls of the groove. A gate pattern is located in the channel recess portion and extends along the groove.

Abstract: A method of forming a dielectric layer is provided. A first dielectric layer is formed on a substrate having metal layers formed thereon. The first dielectric layer includes overhangs in the spaces between two neighboring metal layers and voids under the overhangs. The first dielectric layer is partially removed to cut off the overhangs and expose the voids and therefore openings are formed. A second dielectric layer is formed on the dielectric layer to fill up the opening.

Abstract: A manufacturing method for a semiconductor-device isolation structure comprises providing a substrate with at least one shallow trench isolation structure, performing a salicide process that forms a recess on the surface of the shallow trench isolation structure, forming a cap film covering the substrate and filling the recess, performing an etching process to remove the cap film outside the recess, and forming a contact etch stop layer covering the substrate and filling the recess. Due to the filling recess with the cap film first, the contact etch stop layer covering the substrate and filling the recess does not have seams or voids.

Abstract: Provided is a method that includes forming a first semiconductor layer on a semiconductor substrate, growing a second semiconductor layer on the first semiconductor layer, forming composite shapes on the first semiconductor layer, each composite shape comprising of an overlying oxide-resistant shape and an underlying second semiconductor shape, with portions of the first semiconductor layer exposed between the composite shapes, forming spacers on sides of the composite shapes, forming buried silicon oxide regions in exposed top portions of the first semiconductor layer, and in portions of the first semiconductor layer located underlying second semiconductor shapes, selectively removing the oxide-resistant shapes and spacers resulting in the second semiconductor shapes, and forming a semiconductor device in a second semiconductor shape wherein a first portion of the semiconductor device overlays the first semiconductor layer and wherein second portions of the semiconductor device overlays a buried silicon oxid

Abstract: Methods for forming thin dielectric films by selectively depositing a conformal film of dielectric material on a high aspect ratio structure have uses in semiconductor processing and other applications. A method for forming a dielectric film involves providing in a deposition reaction chamber a substrate having a gap on the surface. The gap has a top opening and a surface area comprising a bottom and sidewalls running from the top to the bottom. A conformal silicon oxide-based dielectric film is selectively deposited in the gap by first preferentially applying a film formation catalyst or a catalyst precursor on a portion representing less than all of the gap surface area. The substrate surface is then exposed to a silicon-containing precursor gas such that a silicon oxide-based dielectric film layer is preferentially formed on the portion of the gap surface area.

Abstract: A silicon oxide film formation method includes generating plasma inside a process chamber of a plasma processing apparatus, by use of a process gas having an oxygen ratio of 1% or more, and a process pressure of 133.3 Pa or less; and oxidizing by the plasma a silicon surface exposed inside a recessed part formed in a silicon layer on a target object, thereby forming a silicon oxide film.

Abstract: An oxide pattern forming method comprises forming an oxide layer on a semiconductor substrate, implanting boron ions of not less than 1.0×1016 atoms/cm2 onto the oxide layer in a given region, and wet-etching the oxide layer in the remaining region where the boron ions are not implanted.

Abstract: Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.

Abstract: A PMOS transistor and a method for fabricating a PMOS transistor. The method may include providing a semiconductor wafer having a PMOS transistor gate stack, source/drain extension regions, and active regions. The method may also include forming epi sidewalls, performing a ex-situ recess etch, and performing an in-situ recess etch. The ex-situ recess etch and the in-situ recess etch form recessed active regions. The PMOS transistor is formed by a method using ex-situ and in-situ etch and has epitaxial SiGe regions with a greatest width at the surface of the semiconductor wafer.

Abstract: A process for digging deep trenches in a body of semiconductor material includes forming a mask having an opening, above a surface of a semiconductor body. A passivating layer is conformally formed on the mask and on the semiconductor body within the opening. A directional etch is extended to first remove the passivating layer from on top of the semiconductor body and then etch the semiconductor body through the opening. Forming the passivating layer and executing the directional etch are carried out repeatedly in sequence so as to form a trench through the opening. A tapered portion of the trench is formed, which has a transverse dimension decreasing as a distance from the surface of the semiconductor body increases.

Abstract: A device isolation structure of semiconductor device includes a semiconductor substrate having a cell region, a low voltage region and a high voltage region defined therein. A cell trench isolation region is disposed in the cell region. A low voltage trench isolation region is disposed in the low voltage region and extends deeper into the substrate than the cell trench isolation region. A first high voltage trench isolation region is disposed in the high voltage region and extends deeper into the substrate than the low voltage trench isolation region. A second high voltage trench isolation region is disposed in the high voltage region and extends deeper into the substrate than the low voltage trench isolation region but shallower than the first high voltage trench isolation region.

Abstract: Double-sided waffle packs and methods of using the same are provided. In one aspect, a waffle pack is provided that includes a body that has a first side and second side opposite the first side. The first side has a first cavity for enabling a semiconductor die to be seated therein when the body is in a first orientation. The second side has a second cavity for enabling a semiconductor die to be seated therein when the body is in a second orientation opposite the first orientation. The first cavity has a first footprint and the second cavity has a second footprint. The first and second footprints are substantially aligned vertically.

Abstract: An isolation method of active area for semiconductor forms an isolated active area in a substrate. The substrate is a p-type silicon substrate. A pad oxide layer is formed on the substrate. A patterned sacrificial layer and an upper mask layer are formed on the pad oxide layer, where the upper mask layer is formed over the isolation region of the substrate. A gap is formed between the patterned sacrificial layer and the upper mask layer. An implantation process is performed to dope ions into the substrate through the gap, which forms an n-type barrier to surround the active areas. Lastly, the patterned sacrificial layer is stripped, and an anodization process is utilized to convert p-type bulk silicon into porous silicon. Then, an oxidation process is performed to oxidize the porous silicon to form a silicon dioxide isolation region for the active areas.